On 06/12/2013 02:00 AM, Scott Wood wrote:
On 06/09/2013 05:24:05 AM, Chunhe Lan wrote:
+/* W**G* - Flash, localbus */
+/* This will be changed to *I*G* after relocation to RAM. */
+SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+
If hwconfig does not contains en_cpc then by default all cpcs are enabled
If this config is defined then only those individual cpcs which are defined
in the subargument of en_cpc will be enabled e.g en_cpc:cpc1,cpc2; (this
will enable cpc1 and cpc2) or en_cpc:cpc2; (this enables just cpc2)
-Original Message-
From: Wood Scott-B07421
Sent: Thursday, June 13, 2013 6:29 AM
To: Zhang Ying-B40530
Cc: u-boot@lists.denx.de; aflem...@gmail.com; Xie Xiaobo-R63061; Zhang
Ying-B40530
Subject: Re: [PATCH] powerpc/p1022ds: nand: introduce the TPL based on the SPL
On 06/09/2013
P1023RDB Specification:
---
Memory subsystem:
512MB DDR3 (Fixed DDR on board)
64MB NOR flash
128MB NAND flash
Ethernet:
eTSEC1: Connected to Atheros AR8035 GETH PHY
eTSEC2: Connected to Atheros AR8035 GETH PHY
PCIe:
Three mini-PCIe slots
USB: Two USB2.0
On 02/04/13 22:10, a.wlodarc...@samsung.com wrote:
From: Arkadiusz Wlodarczyk arek@AMDC384.(none)
Signed-off-by: Arkadiusz Wlodarczyk a.wlodarc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Tested-by: Arkadiusz Wlodarczyk a.wlodarc...@samsung.com
Cc: Minkyu Kang
Signed-off-by: Axel Lin axel@ingics.com
---
Forgot to CC mailing list, so here is a resend.
drivers/spi/tegra114_spi.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c
index b11a0a1..4d2af48 100644
---
It's done in spi_alloc_slave(), thus remove the redundant code.
Signed-off-by: Axel Lin axel@ingics.com
---
drivers/spi/tegra20_sflash.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c
index 9322ce7..7c3a3fc 100644
---
On 12/05/13 03:19, Simon Glass wrote:
On Wed, Apr 3, 2013 at 6:11 AM, Rajeshwari Shinde
rajeshwar...@samsung.com wrote:
These should not be in the header since not every C file needs them.
Move them to the file that needs them.
Signed-off-by: Simon Glass s...@chromium.org
Signed-off-by:
On 30/05/13 13:47, Simon Glass wrote:
On Tue, May 28, 2013 at 11:36 PM, Rajeshwari Birje
rajeshwari.bi...@gmail.com mailto:rajeshwari.bi...@gmail.com wrote:
Hi Andy,
U seem to be busy. I you have no issues can I ask Minkyu Kang to take
them in u-boot-samsung tree. Please do
On 06/04/13 07:21, Naveen Krishna Chatradhi wrote:
From: Naveen Krishna Chatradhi ch.nav...@samsung.com
This patch implements the mux_addr bit fields defined in tmu_control
register (used for debugging purpose)
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Reviewed-by:
On 06/04/13 07:21, Naveen Krishna Chatradhi wrote:
From: Naveen Krishna Chatradhi ch.nav...@samsung.com
This patch does the folowing
1. change the data types for unsigned int variable to unsigned
2. change the tmu_base type to struct exynos5_tmu_reg *
3. Add timer functionality for
Hello,
First of all I want to mention that I am quite new on the development at
this level on the mpc5200 based boards. It might be that I'll ask dumb or
wrong questions so I want to apologize for this.
I am using a custom board based on icecube 5200 reference card but with an
Hi Albert,
On Tue, 11 Jun 2013 14:47:29 +0200, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
Hi Albert,
On Tue, 11 Jun 2013 14:17:29 +0200, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
This series optimizes relocation by ensuring ARM
binaries only use one type of relocation
Hi Jagan, Dale,
On Thu, 13 Jun 2013 08:09:04 +0530, Jagan Teki
jagannadh.t...@gmail.com wrote:
Hi,
Thanks for sending this.
Few comments.
1. Please use subject prefix with version number this case it should
be PATH v3
Plus if it is v3, then it should have patch history too.
On Thu, Jun 13, 2013 at 2:39 PM, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
Hi Jagan, Dale,
On Thu, 13 Jun 2013 08:09:04 +0530, Jagan Teki
jagannadh.t...@gmail.com wrote:
Hi,
Thanks for sending this.
Few comments.
1. Please use subject prefix with version number this case it should
Hi Albert,
On 13/06/13 17:43, Albert ARIBAUD wrote:
Hi Chris,
On Thu, 13 Jun 2013 13:16:17 +1200, Chris Packham
judge.pack...@gmail.com wrote:
On Thu, Jun 13, 2013 at 12:02 PM, Chris Packham judge.pack...@gmail.com
wrote:
Hi,
I've just found a crash in usb_stor_get_info (actually
Dear Axel Lin,
Signed-off-by: Axel Lin axel@ingics.com
---
Forgot to CC mailing list, so here is a resend.
drivers/spi/tegra114_spi.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c
index b11a0a1..4d2af48
Dear Axel Lin,
It's done in spi_alloc_slave(), thus remove the redundant code.
Signed-off-by: Axel Lin axel@ingics.com
---
drivers/spi/tegra20_sflash.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c
index
Make it similar to the code in mips64/start.S, in order to
allow further unifications.
Signed-off-by: Gabor Juhos juh...@openwrt.org
Cc: Daniel Schwierzeck daniel.schwierz...@googlemail.com
---
arch/mips/cpu/mips32/start.S |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff
The patch-set changes some parts of the low-level assembly
code in order to minimize the difference between the mips32,
mips64 and xburst implementation. Do it in small steps to
make review easier.
The series is based on the testing branch of the MIPS custodian tree.
Cc: Daniel Schwierzeck
Synchronize the code with mips64/cache.S, in order to
allow further unifications.
Signed-off-by: Gabor Juhos juh...@openwrt.org
Cc: Daniel Schwierzeck daniel.schwierz...@googlemail.com
---
arch/mips/cpu/mips32/cache.S |8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
Synchronize the code with mips{32,64}/start.S, in order to
allow further unifications.
Signed-off-by: Gabor Juhos juh...@openwrt.org
Cc: Daniel Schwierzeck daniel.schwierz...@googlemail.com
---
arch/mips/cpu/xburst/start.S |8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff
Synchronize the code with mips64/start.S, in order to
allow further unifications.
Signed-off-by: Gabor Juhos juh...@openwrt.org
Cc: Daniel Schwierzeck daniel.schwierz...@googlemail.com
---
arch/mips/cpu/mips32/start.S | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
Synchronize the code with mips{32,64}/start.S, in order to
allow further unifications.
Signed-off-by: Gabor Juhos juh...@openwrt.org
Cc: Daniel Schwierzeck daniel.schwierz...@googlemail.com
---
arch/mips/cpu/xburst/start.S | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
Synchronize the code with mips64/cache.S, in order to
allow further unifications.
Signed-off-by: Gabor Juhos juh...@openwrt.org
Cc: Daniel Schwierzeck daniel.schwierz...@googlemail.com
---
arch/mips/cpu/mips32/cache.S |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Synchronize the code with mips{32,64}/start.S, in order to
allow further unifications.
Signed-off-by: Gabor Juhos juh...@openwrt.org
Cc: Daniel Schwierzeck daniel.schwierz...@googlemail.com
---
arch/mips/cpu/xburst/start.S |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
Make it similar to the code in mips{32,64}/start.S, in order to
allow further unifications.
Signed-off-by: Gabor Juhos juh...@openwrt.org
Cc: Daniel Schwierzeck daniel.schwierz...@googlemail.com
---
arch/mips/cpu/xburst/start.S |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff
Synchronize the code with mips{32,64}/start.S, in order to
allow further unifications.
Signed-off-by: Gabor Juhos juh...@openwrt.org
Cc: Daniel Schwierzeck daniel.schwierz...@googlemail.com
---
arch/mips/cpu/xburst/start.S | 18 +-
1 file changed, 9 insertions(+), 9
(for GIT URL and Changelog see below)
ARM CPUs with the virtualization extension have a new mode called
HYP mode, which allows hypervisors to safely control and monitor
guests. The current hypervisor implementations (KVM and Xen)
require the kernel to be entered in that HYP mode.
This patch
Synchronize the code with mips64/cache.S, in order to
allow further unifications.
Signed-off-by: Gabor Juhos juh...@openwrt.org
Cc: Daniel Schwierzeck daniel.schwierz...@googlemail.com
---
arch/mips/cpu/mips32/cache.S |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
armv7.h contains some useful constants, but also C prototypes.
To include it also in assembly files, protect the non-assembly
part appropriately.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/include/asm/armv7.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
A prerequisite for using virtualization is to be in HYP mode, which
requires the CPU to be in non-secure state first.
Add new file in arch/arm/cpu/armv7 to hold a monitor handler routine
which switches the CPU to non-secure state by setting the NS and
associated bits.
According to the ARM
Currently the non-secure switch is only done for the boot processor.
To enable full SMP support, we have to switch all secondary cores
into non-secure state also.
So we add an entry point for secondary CPUs coming out of low-power
state and make sure we put them into WFI again after having
For the KVM and XEN hypervisors to be usable, we need to enter the
kernel in HYP mode. Now that we already are in non-secure state,
HYP mode switching is within short reach.
While doing the non-secure switch, we have to enable the HVC
instruction and setup the HYP mode HVBAR (while still secure).
Hi Marek,
On Wed, 12 Jun 2013 22:57:56 +0200, Marek Vasut ma...@denx.de wrote:
The following changes since commit 58bb8f5f6138fa56875574a709f5af98c600c2a9:
cosmetic: arm: fix comments in arch/arm/lib/crt0.S (2013-06-10 21:24:22
+0200)
are available in the git repository at:
To enable hypervisors utilizing the ARMv7 virtualization extension
on the Versatile Express board with the A15 core tile, we add the
respective configuration variable.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
include/configs/vexpress_ca15_tc2.h | 2 ++
1 file changed, 2
While actually switching to non-secure state is one thing, the
more important part of this process is to make sure that we still
have full access to the interrupt controller (GIC).
The GIC is fully aware of secure vs. non-secure state, some
registers are banked, others may be configured to be
To actually trigger the non-secure switch we just implemented, call
the switching routine from within the bootm command implementation.
This way we automatically enable this feature without further user
intervention.
The core specific part of the work is done in the assembly routine
in
Thanks Mr.Kang
Best Regards,
Jaehoon Chung
On 06/13/2013 05:45 PM, Minkyu Kang wrote:
On 30/05/13 13:47, Simon Glass wrote:
On Tue, May 28, 2013 at 11:36 PM, Rajeshwari Birje
rajeshwari.bi...@gmail.com mailto:rajeshwari.bi...@gmail.com wrote:
Hi Andy,
U seem to be busy. I you
Hi Chris,
On Thu, 13 Jun 2013 22:19:54 +1200, Chris Packham
judge.pack...@gmail.com wrote:
Hi Albert,
On 13/06/13 17:43, Albert ARIBAUD wrote:
Hi Chris,
On Thu, 13 Jun 2013 13:16:17 +1200, Chris Packham
judge.pack...@gmail.com wrote:
On Thu, Jun 13, 2013 at 12:02 PM, Chris
Hi Frederic,
On Mon, 10 Jun 2013 15:30:53 +0200, Frederic Leroy fr...@starox.org
wrote:
From: Frédéric Leroy fr...@starox.org
For big disk support, we need LBA addressing on 64 bits
---
include/configs/lacie_kw.h | 1 +
1 file changed, 1 insertion(+)
diff --git
Hi Frank,
On Tue, Jan 22, 2013 at 10:11 PM, Vipin Kumar vipin.ku...@st.com wrote:
On 1/22/2013 7:40 PM, Frank Dols wrote:
Hello Vipin,
As discussed, see included the patches to make your
u-boot/drivers/net/designware Ethernet device driver cache support aware.
You dont need to write
On Thu, Jun 13, 2013 at 1:28 AM, Wolfgang Denk w...@denx.de wrote:
Dear Shigeru Yoshida,
In message
camqom_0gl2czu_xm-c9_zonmgmyi1m6w_ysxuv2etaebuvr...@mail.gmail.com you
wrote:
diff --git a/board/wandboard/README b/board/wandboard/README
index e0b0b33..8bf646d 100644
---
Hello,
I just tried to write with dfu and dfu-util on the host
to a not empty partiton on a nand flash. After the dfu
returned without error, I wanted to read the nand partiton
with nand read and I get ECC errors. This is on an am335x
based board (mainline patches coming soon) with ECC BCH8
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 06/13/2013 08:15 AM, Heiko Schocher wrote:
Hello,
I just tried to write with dfu and dfu-util on the host to a not
empty partiton on a nand flash. After the dfu returned without
error, I wanted to read the nand partiton with nand read and I
On 06/12/2013 12:54 PM, Dan Murphy wrote:
Detect if we are running on a panda revision A1-A6,
or an ES panda board. This can be done by reading
the level of GPIOs and checking the processor revisions.
This should result in:
Panda 4430:
GPIO171, GPIO101, GPIO182: 0 1 1 = A1-A5
On Wed, Jun 12, 2013 at 12:54:27PM -0500, Dan Murphy wrote:
Detect if we are running on a panda revision A1-A6,
or an ES panda board. This can be done by reading
the level of GPIOs and checking the processor revisions.
This should result in:
Panda 4430:
GPIO171, GPIO101, GPIO182: 0 1 1
Hello Tom,
Am 13.06.2013 14:33, schrieb Tom Rini:
On 06/13/2013 08:15 AM, Heiko Schocher wrote:
Hello,
I just tried to write with dfu and dfu-util on the host to a not
empty partiton on a nand flash. After the dfu returned without
error, I wanted to read the nand partiton with nand read
Le 13/06/2013 13:33, Albert ARIBAUD a écrit :
With gcc version 4.7.2 (Ubuntu/Linaro 4.7.2-2ubuntu1) this patch causes
the following warning for all boards:
cmd_ide.c:992:4: warning: right shift count = width of type [enabled
by default]
Amicalement,
I will convert every ide block number
Hi Frédéric,
On Thu, 13 Jun 2013 15:03:49 +0200, Frédéric Leroy fr...@starox.org
wrote:
Le 13/06/2013 13:33, Albert ARIBAUD a écrit :
With gcc version 4.7.2 (Ubuntu/Linaro 4.7.2-2ubuntu1) this patch causes
the following warning for all boards:
cmd_ide.c:992:4: warning: right shift count
Hi,
I am trying to port the u-boot2013:04 to sdk.During compilation,I am
running into error:*Undefined reference to _GLOBAL_OFFSET_TABLE*.I checked
in u-boot.lds file thr is no definition of _GLOBAL_OFFSET_TABLE.I have
added this piece of code in u-boot.lds:
.reloc :
{
Le 13/06/2013 15:21, Albert ARIBAUD a écrit :
I guess CONFIG_LBA48 is also broken in common/cmd_ide.c :
ulong ide_write(int device, ulong blknr, lbaint_t blkcnt, const void
*buffer)
{
ulong n = 0;
unsigned char c;
#ifdef CONFIG_LBA48
unsigned char lba48 = 0;
2013/6/13 Otavio Salvador ota...@ossystems.com.br
http://git.denx.de/?p=u-boot/u-boot-imx.git;a=commitdiff;h=8c4983779ed50090b74d56498be17cde31892a64
Already fixed.
This patch worked my environment.
Thank you!
___
U-Boot mailing list
On 13-06-2013 16:18, Marek Vasut wrote:
Dear Axel Lin,
Signed-off-by: Axel Lin axel@ingics.com
---
Forgot to CC mailing list, so here is a resend.
drivers/spi/tegra114_spi.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/spi/tegra114_spi.c
On 13-06-2013 16:18, Marek Vasut wrote:
Dear Axel Lin,
It's done in spi_alloc_slave(), thus remove the redundant code.
Signed-off-by: Axel Lin axel@ingics.com
---
drivers/spi/tegra20_sflash.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/spi/tegra20_sflash.c
On Thu, Jun 13, 2013 at 4:08 AM, Simon Glass s...@chromium.org wrote:
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-t...@xilinx.com wrote:
Initialized bank_sel variable to 0 to support the updated read
ops for flashes which has 16Mbytes.
2013/6/13 krishna dwivedi krishna.dwived...@gmail.com:
Hi,
I am trying to port the u-boot2013:04 to sdk.During compilation,I am
running into error:*Undefined reference to _GLOBAL_OFFSET_TABLE*.I checked
in u-boot.lds file thr is no definition of _GLOBAL_OFFSET_TABLE.I have
added this piece
On Thu, Jun 13, 2013 at 08:23:13AM +0530, Jagan Teki wrote:
Hi Simon,
On Thu, Jun 13, 2013 at 3:48 AM, Simon Glass s...@chromium.org wrote:
Hi Jagan,
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-t...@xilinx.com wrote:
This patch provides
Hello Tom,
The following changes since commit
4596dcc1d4ea5763e0f92cf5becd9fc7d4c6e674:
am33xx/omap: Move save_omap_boot_params to omap-common/boot-common.c
(2013-06-05 08:46:49 -0400)
are available in the git repository at:
git://git.denx.de/u-boot-arm master
for you to fetch changes
On Thu, Jun 13, 2013 at 05:53:17AM +0200, Heiko Schocher wrote:
move s_init from every board code to a common place.
Signed-off-by: Heiko Schocher h...@denx.de
Cc: Tom Rini tr...@ti.com
Cc: Matt Porter mpor...@ti.com
Cc: Lars Poeschel poesc...@lemonage.de
Cc: Tom Rini tr...@ti.com
Cc:
On 06/13/2013 02:02:46 AM, Chunhe Lan wrote:
On 06/12/2013 02:00 AM, Scott Wood wrote:
On 06/09/2013 05:24:05 AM, Chunhe Lan wrote:
+/* W**G* - Flash, localbus */
+/* This will be changed to *I*G* after relocation to RAM. */
+SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE,
Detect if we are running on a panda revision A1-A6,
or an ES panda board. This can be done by reading
the level of GPIOs and checking the processor revisions.
This should result in:
Panda 4430:
GPIO171, GPIO101, GPIO182: 0 1 1 = A1-A5
GPIO171, GPIO101, GPIO182: 1 0 1 = A6
Panda ES:
Fix the checkpatch warning on the panda.c file for leading
spaces.
Fix the CHECK warnings on the panda.c file for parenthesis alignment.
Signed-off-by: Dan Murphy dmur...@ti.com
---
board/ti/panda/panda.c | 26 +-
1 files changed, 13 insertions(+), 13 deletions(-)
diff
On 06/13/2013 01:59:51 AM, Sandeep Singh wrote:
If hwconfig does not contains en_cpc then by default all cpcs are
enabled
If this config is defined then only those individual cpcs which are
defined
in the subargument of en_cpc will be enabled e.g en_cpc:cpc1,cpc2;
(this
will enable cpc1
On 13-06-2013 13:47, Axel Lin wrote:
Signed-off-by: Axel Lin axel@ingics.com
Acked-by: Marek Vasut ma...@denx.de
Reviewed-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
Forgot to CC mailing list, so here is a resend.
drivers/spi/tegra114_spi.c | 4 +---
1 file changed, 1
On 11-06-2013 19:27, Axel Lin wrote:
Signed-off-by: Axel Lin axel@ingics.com
Reviewed-by: Marek Vasut ma...@denx.de
Acked-by: Ajay Bhargav ajay.bhar...@einfochips.com
Reviewed-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
drivers/spi/armada100_spi.c | 11 ++-
1 file
On 13-06-2013 13:51, Axel Lin wrote:
It's done in spi_alloc_slave(), thus remove the redundant code.
Signed-off-by: Axel Lin axel@ingics.com
Acked-by: Marek Vasut ma...@denx.de
Reviewed-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
drivers/spi/tegra20_sflash.c | 2 --
1
Move the linux and usb compat files to the
include/linux/usb directory in order for the files to be
reused.
Added GPLv2 license to the linux and usb compat as well.
Signed-off-by: Dan Murphy dmur...@ti.com
---
drivers/usb/musb-new/linux-compat.h| 114 --
Hi Jagan,
On Thu, Jun 13, 2013 at 10:46 AM, Willis, Max max.wil...@spansion.comwrote:
Hi Jagan, Simon - Adding Bacem and Gernot from Spansion. Would you be able
to add them to the other open threads as well? --Max
-
Max Willis, PhD
Division
Hi Simon,
On Thu, Jun 13, 2013 at 11:23 PM, Simon Glass s...@chromium.org wrote:
Hi Jagan,
On Thu, Jun 13, 2013 at 10:46 AM, Willis, Max max.wil...@spansion.com
wrote:
Hi Jagan, Simon - Adding Bacem and Gernot from Spansion. Would you be able
to add them to the other open threads as well?
Signed-off-by: Robert Winkler robert.wink...@boundarydevices.com
---
board/boundary/nitrogen6x/nitrogen6x.c| 4 +++-
board/freescale/mx6qsabrelite/mx6qsabrelite.c | 4 +++-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c
The following changes since commit 48e0b2bd2b6ecc80cd25181ca2fb9c0eaffef320:
powerpc/esdhc: Correct judgement for DATA PIO mode (2013-05-15 18:18:16 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-spi.git master
for you to fetch changes up to
On 30-05-2013 19:19, Jagannadha Sutradharudu Teki wrote:
As the per the ID tabl the flash is under Uniform 64-kB sector
architecture, hence updated with proper name.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v2:
- none
drivers/mtd/spi/spansion.c |
On Wed, Jun 12, 2013 at 10:25:47PM +0200, Marek Vasut wrote:
The following changes since commit e1208c2fe5e07f9a248cfbf9bbb212aa34ad2806:
MIPS: asm/errno.h: switch to asm-generic/errno.h (2013-06-08 23:10:10 +0200)
are available in the git repository at:
On 06/13/2013 11:05 AM, Albert ARIBAUD wrote:
Hi Albert,
On Tue, 11 Jun 2013 14:47:29 +0200, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
Hi Albert,
On Tue, 11 Jun 2013 14:17:29 +0200, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
This series optimizes relocation by ensuring ARM
On 30-05-2013 19:19, Jagannadha Sutradharudu Teki wrote:
This patch corrected the nr_blocks used for W25Q32DW SPI flash.
nr_blcoks are incorrectly assigned on below patch
sf: winbond: add W25Q32DW
(sha1: 772ba15474f73adc942e817cc072b6e9750836cc)
Signed-off-by: Jagannadha Sutradharudu Teki
On 30-05-2013 19:19, Jagannadha Sutradharudu Teki wrote:
Add support for Winbond W25Q80BW SPI flash.
This patch corrected the flash name, nr_blocks and
also commit message header from below patch.
sf: winbond: add W25Q32
(sha1: c969abc47033d6f810d3c9dbdb994ea9d691d038)
Signed-off-by:
Move the linux and usb compat files to the
include/linux/usb directory in order for the files to be
reused.
Added GPLv2 license to the linux and usb compat as well.
Signed-off-by: Dan Murphy dmur...@ti.com
---
v2 - Fix checkpatch issues only for newly introduced code -
On 06/13/2013 12:55 PM, Dan Murphy wrote:
Move the linux and usb compat files to the
include/linux/usb directory in order for the files to be
reused.
Added GPLv2 license to the linux and usb compat as well.
Signed-off-by: Dan Murphy dmur...@ti.com
---
drivers/usb/musb-new/linux-compat.h
On 06/13/2013 02:44:17 AM, Chunhe Lan wrote:
+/*
+ * Memory map
+ *
+ * 0x_ 0x1fff_ DDR 500M
Cacheable
+ * 0x8000_ 0xbfff_ PCI Express Mem 1G
non-cacheable
+ * 0xc000_ 0xdfff_ PCI 512M
non-cacheable
+ * 0xe100_ 0xe3ff_ PCI IO range 4M
On Thu, Jun 13, 2013 at 8:56 PM, Tom Rini tr...@ti.com wrote:
On Thu, Jun 13, 2013 at 08:23:13AM +0530, Jagan Teki wrote:
Hi Simon,
On Thu, Jun 13, 2013 at 3:48 AM, Simon Glass s...@chromium.org wrote:
Hi Jagan,
On Tue, Jun 11, 2013 at 12:23 PM, Jagannadha Sutradharudu Teki
Frédéric Leroy fr...@starox.org writes:
I will convert every ide block number to 64 bit for disk and partitions.
I guess CONFIG_LBA48 is also broken in common/cmd_ide.c :
FWIW, I have a patch pending for this already. But it's necessarily
pretty invasive and I'm not even sure yet that I've
Add support for Numonyx N25Q512A SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v4:
- none
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/stmicro.c | 6 ++
1 file changed, 6 insertions(+)
diff --git
Bank/Extended addr commands are specific to particular
flash vendor so discover them based on the idocode0.
Assign the discovered bank commands to spi_flash members
so-that the bank read/write will use their specific operations.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
This patch updated the spi_flash read func to support all
sizes of flashes using bank reg addr facility.
The same support has been added in below patch for erase/write
spi_flash functions:
sf: Support all sizes of flashes using bank addr reg facility
(sha1:
Updated the spi_flash framework to handle all sizes of flashes
using bank/extd addr reg facility
The current implementation in spi_flash supports 3-byte address mode
due to this up to 16Mbytes amount of flash is able to access for those
flashes which has an actual size of 16MB.
As most of the
Add support for Spansion S25FL512S_64K SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v4:
- none
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/spansion.c | 7 +++
1 file changed, 7 insertions(+)
diff --git
There is no other call other than spi_flash_cmd_wait_ready(),
hence removed spi_flash_cmd_poll_bit and use the poll status code
spi_flash_cmd_wait_ready() itself.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Reviewed-by: Simon Glass s...@chromium.org
---
Changes for v4:
Use the existing spi_flash_addr() for 3-byte addressing
cmd filling in write call.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Reviewed-by: Simon Glass s...@chromium.org
---
Changes for v4:
- none
Changes for v3:
- none
Changes for v2:
- none
Add support for Numonyx N25Q1024A SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v4:
- none
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/stmicro.c | 6 ++
1 file changed, 6 insertions(+)
diff --git
Add support for Numonyx N25Q512 SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v4:
- none
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/stmicro.c | 6 ++
1 file changed, 6 insertions(+)
diff --git
This patch provides support to program a flash bank address
register.
extended/bank address register contains an information to access
the 4th byte addressing in 3-byte address mode.
reff' the spec for more details about bank addr register
in Page-63, Table 8.16
Read the flash bank addr register to get the state of bank in
a perticular flash. and also bank write happens only when there is
a change in bank selection from user.
bank read only valid for flashes which has 16Mbytes those are
opearted in 3-byte addr mode, each bank occupies 16Mytes.
Suppose
Add support for Numonyx N25Q1024 SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v4:
- none
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/stmicro.c | 6 ++
1 file changed, 6 insertions(+)
diff --git
This is a v4 patch series with some modifications on previous series with same
head sf: Update sf framework to support all sizes of flashes
These patches removes some redundents and better coding when comapred
to v3.
The current implementation in sf supports 3-byte address mode due
to this up to
Flag status register polling is required for micron 512Mb flash
devices onwards, for performing erase/program operations.
Like polling for WIP(Write-In-Progress) bit in read status register,
spi_flash_cmd_wait_ready will poll for PEC(Program-Erase-Control)
bit in flag status register.
Defined bank addr code on CONFIG_SPI_FLASH_BAR macro, to reduce the
size for existing boards which has 16Mbytes SPI flashes.
It's upto user which has provision to use the bank addr code for
flashes which has 16Mbytes.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Reviewed-by:
On 06/13/2013 02:27:44 AM, Zhang Ying-B40530 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Thursday, June 13, 2013 6:29 AM
To: Zhang Ying-B40530
Cc: u-boot@lists.denx.de; aflem...@gmail.com; Xie Xiaobo-R63061;
Zhang Ying-B40530
Subject: Re: [PATCH] powerpc/p1022ds: nand:
(Sorry to those on to/cc; I'm resending this so it goes to the correct
mailing list)
Commit 020bbcb usb: hub: Power-cycle on root-hub ports causes a
regression on Tegra systems.
The first time usb start is executed, it appears to work correctly.
However, any subsequent time it is executed, it
Keys required for signing images will be in a specific directory. Add a
-k option to specify that directory.
Also update the mkimage man page with this information and a clearer list
of available commands.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Marek Vasut ma...@denx.de (v1)
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