From: Soren Brinkmann soren.brinkm...@xilinx.com
Remove hard coded clock divider setting and use the Zynq clock framework
to dynamically calculate appropriate dividers at run time.
Signed-off-by: Soren Brinkmann soren.brinkm...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
On Wed, Jan 22, 2014 at 5:19 AM, Markus Niebel list-09_u-b...@tqsc.de wrote:
IOMUX_CONFIG_SION is used everywhere for I2C dedicated pins - partly hard
coded for
mx6q - so yes, should be used fro enet_clk, too
Yes, looks good.
Regards,
Fabio Estevam
This change allows updating environment stored on MMC by dfu or thor.
New setting:
- params.bin mmc 0x38 0x8
File params.bin can be generated by: tools/mkenvimage.
e.g. ./mkenvimage -s 4096 -o params.bin env_text_file
Every new env variable in text file should start with a new line.
Sample env
Command provides just dump subcommand for showing clock
frequencies in a soc.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
README | 1 +
common/Makefile | 1 +
common/cmd_clk.c | 51
include/clk.h
From: Soren Brinkmann soren.brinkm...@xilinx.com
Enable and implement dump clock command which shows
soc frequencies.
Signed-off-by: Soren Brinkmann soren.brinkm...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
On the top of Zynq clk patches I have sent.
All paches
CC
On 01/22/2014 12:02 PM, Przemyslaw Marczak wrote:
This change allows updating environment stored on MMC by dfu or thor.
New setting:
- params.bin mmc 0x38 0x8
File params.bin can be generated by: tools/mkenvimage.
e.g. ./mkenvimage -s 4096 -o params.bin env_text_file
Every new env
Hi Przemyslaw,
This change allows updating environment stored on MMC by dfu or thor.
New setting:
- params.bin mmc 0x38 0x8
File params.bin can be generated by: tools/mkenvimage.
e.g. ./mkenvimage -s 4096 -o params.bin env_text_file
Every new env variable in text file should start
Hi Haijun,
On Jan 10, 2014, at 7:52 AM, Haijun Zhang wrote:
Card detection pin is ineffective on T4240QDS Rev1.0.
There are two cards can be connected to board.
1. eMMC card is built-in board, can not be removed. so
For eMMC card it is always there.
2. Card detecting pin is functional for
Hi Haijun,
On Jan 10, 2014, at 7:52 AM, Haijun Zhang wrote:
The upper 4 data signals of esdhc are shared with spi flash.
So detect if the upper 4 pins are assigned to esdhc before
enable sdhc 8 bit width.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V3:
Hi Haijun,
On Jan 10, 2014, at 7:52 AM, Haijun Zhang wrote:
On BSC9131, BSC9132, P1010 : For High Capacity SD Cards ( 2 GBytes), the
32-bit source address specifies the memory address in block address
format. Block length is fixed to 512 bytes as per the SD High Capacity
specification. So we
Hi York,
On Jan 22, 2014, at 12:01 AM, York Sun wrote:
Pantelis,
On 01/09/2014 09:52 PM, Haijun Zhang wrote:
Card detection pin is ineffective on T4240QDS Rev1.0.
There are two cards can be connected to board.
1. eMMC card is built-in board, can not be removed. so
For eMMC card it is
Hi Michal,
On 22/01/2014 12:02, Michal Simek wrote:
Command provides just dump subcommand for showing clock frequencies
in a soc.
i.MXes has already an own command for this functionality - see command
clocks in arch/arm. However, I like that we can have a common
command for all SOCs.
Hi Stefano,
On 01/22/2014 01:46 PM, Stefano Babic wrote:
Hi Michal,
On 22/01/2014 12:02, Michal Simek wrote:
Command provides just dump subcommand for showing clock frequencies
in a soc.
i.MXes has already an own command for this functionality - see command
clocks in arch/arm. However,
From: Fabio Estevam fabio.este...@freescale.com
Similarly as it was done on commit 6584a1b526 (ARM: mx6: Change the FDT loading
address to avoid overlaping), we need to adjust the fdt_addr in order to be
able to boot FSL 3.10 kernel.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
On Wed, Jan 22, 2014 at 12:23 PM, Fabio Estevam feste...@gmail.com wrote:
From: Fabio Estevam fabio.este...@freescale.com
Similarly as it was done on commit 6584a1b526 (ARM: mx6: Change the FDT
loading
address to avoid overlaping), we need to adjust the fdt_addr in order to be
able to boot
This patchset adds runtime variables for Samsung boards that describe
build configuration (arch, soc, board, vendor).
Additionally, more envs describing platform (soc and board revision) are added
to Samsung common code.
For boards Trats and Trats2, based on the added envs, 'fdtfile' env is set
This patch enables to read cpu revision on Exynos CPU.
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
Changes for V2:
- none
arch/arm/include/asm/arch-exynos/cpu.h |8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
This patch sets envs that describe board information.
The following envs are set: soc_id, soc_rev, board_rev.
Based on this information, if CONFIG_OF_LIBFDT is enabled,
the 'fdtfile' env is set as:
fdtfile=${soc_family}${soc_id}-${board}.dtb
The generated envs are intenionally not saved to
This patch adds variables describing platform (soc, board, vendor)
to default environment.
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Cc: Mateusz Zalega m.zal...@samsung.com
---
Changes for V2:
- rebased on patchset [PATCH v6 00/11]
This patch adds variables describing platform (soc, board, vendor)
to default environment.
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Cc: Lukasz Majewski l.majew...@samsung.com
---
Changes for V2:
- rebased on patchset [PATCH v6
This patch adds variables describing platform (soc, board, vendor)
to default environment.
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
Changes for V2:
- rebased on patchset [PATCH v6 00/11] Introduce Samsung misc file and LCD menu
This patch adds s5p_cpu_rev.
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
Changes for V2:
- none
arch/arm/include/asm/arch-s5pc1xx/cpu.h |7 +++
1 file changed, 7 insertions(+)
diff --git
This patch adds variables describing platform (soc, board, vendor)
to default environment.
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Cc: Przemyslaw Marczak p.marc...@samsung.com
---
Changes for V2:
- rebased on patchset [PATCH v6
This patch modifies envs to enable dual kernel boot
- with separated DTB if the DTB file is loaded successfully;
- with DTB apppended to uImage if DTB file is not found;
This is neccesssary for backward compatibilty.
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin
Thanks Alexey.
Hi Heiko,
I believe this patch should be good for apply. Would need your help
then. :) Thanks
Chin Liang
On Wed, 2014-01-15 at 15:51 +, Alexey Brodkin wrote:
On Wed, 2014-01-15 at 09:45 -0600, Chin Liang See wrote:
Changes for v2
- Removed the function check_params()
On Tue, Jan 21, 2014 at 03:07:40PM -0800, York Sun wrote:
Tom,
The following changes since commit b44bd2c73c4cfb6e3b9e7f8cf987e8e39aa74a0b:
Prepare v2014.01 (2014-01-20 17:52:59 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-mpc85xx.git master
for you
Hi Tom,
SF code optimized stuff and few fixes.
--
Thanks!
Jagan.
The following changes since commit b44bd2c73c4cfb6e3b9e7f8cf987e8e39aa74a0b:
Prepare v2014.01 (2014-01-20 17:52:59 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-spi.git master
for you to fetch
From: Alexey Brodkin alexey.brod...@synopsys.com
Up until now this driver only worked with data cache disabled.
To make it work with enabled data cache following changes were required:
* Flush Tx/Rx buffer descriptors their modification
* Invalidate Tx/Rx buffer descriptors before reading its
Hi Alexey,
On 22.01.2014 17:49, Alexey Brodkin wrote:
From: Alexey Brodkin alexey.brod...@synopsys.com
Up until now this driver only worked with data cache disabled.
To make it work with enabled data cache following changes were required:
* Flush Tx/Rx buffer descriptors their modification
With this change driver will benefit from existing phylib and thus
custom phy functionality implemented in the driver will go away:
* Instantiation of the driver is now much shorter - 2 parameters
instead of 4.
* Simplified phy management/functoinality in driver is replaced with
rich
Hello Alexey,
In general, a very nice, clean patch.
+ /* Flush modified buffer descriptor */
+ flush_dcache_range((unsigned long)desc_p,
+(unsigned long)desc_p + sizeof(struct dmamacdescr));
+
If I remember correctly, there is some bit that tells you if the
Hi Mischa,
On Wed, 2014-01-22 at 17:10 +, Mischa Jonker wrote:
Hello Alexey,
In general, a very nice, clean patch.
+ /* Flush modified buffer descriptor */
+ flush_dcache_range((unsigned long)desc_p,
+ (unsigned long)desc_p + sizeof(struct dmamacdescr));
Tom,
The following changes since commit e222b1f36fedb0363dbc21e0add7dc3848bae553:
powerpc/mpc85xx:Increase binary size for P, B T series boards. (2014-01-21
14:06:30 -0800)
are available in the git repository at:
git://git.denx.de/u-boot-mpc85xx.git master
for you to fetch changes up to
On Wed, Jan 22, 2014 at 2:53 PM, Michal Simek michal.si...@xilinx.com wrote:
Zynq common configuration is placed in zynq-common.h
not zynq_common.h.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
include/configs/zynq_zc70x.h | 2 +-
include/configs/zynq_zed.h | 2 +-
2 files
On Wed, Jan 22, 2014 at 2:53 PM, Michal Simek michal.si...@xilinx.com wrote:
icache is already enabled by default.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
board/xilinx/zynq/board.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/board/xilinx/zynq/board.c
On Wed, Jan 22, 2014 at 2:53 PM, Michal Simek michal.si...@xilinx.com wrote:
Enable dcache.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm/cpu/armv7/zynq/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/cpu/armv7/zynq/cpu.c
On Wed, Jan 22, 2014 at 2:53 PM, Michal Simek michal.si...@xilinx.com wrote:
These numbers will be reused by SPL.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm/include/asm/arch-zynq/hardware.h | 6 ++
board/xilinx/zynq/board.c | 6 --
2 files
Hi Bhupesh,
U-boot doesn't have ARM trusted firmware support as of now. U-boot for
ARMv8 starts in EL3, whereas UEFI starts in EL2 as trusted firmware itself
is working in EL3.
Since the ATF software doesn't really care whether it is loading uefi or
u-boot
and since it wants to load
On Wed, Jan 22, 2014 at 12:02 +0100, Michal Simek wrote:
--- /dev/null
+++ b/common/cmd_clk.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include common.h
+#include command.h
+#include clk.h
+
+int __weak
From: Stephen Warren swar...@nvidia.com
Since all code that sets or interprets MASK_BITS_* now uses the enums
to define/compare the values, there is no need for MASK_BITS_* to have
a specific integer value. In fact, having a specific integer value may
encourage people to hard-code those values,
From: Tom Warren twarren.nvi...@gmail.com
Some clock sources have 3-bit muxes in bits 31:29. Implement core
support for this mux field.
Signed-off-by: Tom Warren twar...@nvidia.com
[swarren, extracted from a larger patch by Tom]
Signed-off-by: Stephen Warren swar...@nvidia.com
---
From: Jimmy Zhang jimmzh...@nvidia.com
Based on the Tegra114 TRM, the system clock (which is the AVP clock) can
run up to 275MHz. On power on, the default sytem clock source is set to
PLLP_OUT0. In function clock_early_init(), PLLP_OUT0 will be set to
408MHz which is beyond system clock's upper
From: Stephen Warren swar...@nvidia.com
OUT_CLK_SOURCE_ are currently named after the number of bits the mask
they represent includes. However, bit count is not the only possible
variable; bit position may also vary. Rename OUT_CLK_SOURCE_ to
OUT_CLK_SOURCE_31_30_ and OUT_CLK_SOURCE4_ to
From: Stephen Warren swar...@nvidia.com
The only place where the MASK_BITS_* values are used is in
adjust_periph_pll(), which interprets the value 4 (old MASK_BITS_29_28,
new MASK_BITS_31_28) as being associated with mask OUT_CLK_SOURCE4_MASK,
i.e. bits 31:28. Rename the MASK_BITS_ macro to
From: Stephen Warren swar...@nvidia.com
Not all code that set or interpreted mux_bits was using the named
macros, but rather some was simply using hard-coded integer constants.
This makes it hard to determine which pieces of code are affected by
changes to those constants.
Replace the integer
From: Stephen Warren swar...@nvidia.com
Tegra114 and later's PMC module removes the pwrgate_timer_on register
and replaces it with a clamp_status register. Adjust pmc.h to reflect
this, and update any code affected by the change.
The cpu.c change in this patch was extracted from a much larger
From: Fabio Estevam fabio.este...@freescale.com
Currently when we boot a mx6dual U-boot reports that it is a mx6quad.
Report it as MX6D instead:
CPU: Freescale i.MX6D rev1.2 at 792 MHz
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
Tested-by: Otavio Salvador ota...@ossystems.com.br
From: Tom Warren twarren.nvi...@gmail.com
The enum used to define the set of register bits used to represent a
clock's input mux, MUX_BITS_*, is defined separately for each SoC at
present. Move this definition to a common location to ease fixing up
some issues with the definition, and the code
On Mon, 2014-01-20 at 17:10 -0500, Murali Karicheri wrote:
This patch introduces a configurable mechanism to disable subpage writes
in the DaVinci NAND driver.
Signed-off-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Murali Karicheri m-kariche...@ti.com
---
Stephen,
On Wed, Jan 22, 2014 at 1:20 PM, Stephen Warren swar...@wwwdotorg.orgwrote:
From: Tom Warren twarren.nvi...@gmail.com
The enum used to define the set of register bits used to represent a
clock's input mux, MUX_BITS_*, is defined separately for each SoC at
present. Move this
On 01/22/2014 02:35 PM, Tom Warren wrote:
...
Thanks for doing these patches - nice job. LGTM.
Applies cleanly to u-boot-tegra/next after applying Alban's 2 patches,
your other 3 patches, and then this series of 6. Building all now, I'll
test later.
Great! Just FYI, I tested MMC and DHCP
On Wed, Jan 22, 2014 at 2:54 PM, Stephen Warren swar...@wwwdotorg.orgwrote:
On 01/22/2014 02:35 PM, Tom Warren wrote:
...
Thanks for doing these patches - nice job. LGTM.
Applies cleanly to u-boot-tegra/next after applying Alban's 2 patches,
your other 3 patches, and then this series of
The R7S72100 has same IP as serial with SH.
This adds support R7S72100 to serial_sh.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
drivers/serial/serial_sh.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/serial/serial_sh.h
The R7S72100 of ARM SoC that Renesas manufactured has one Ether port.
This has the same IP SH-Ether. This patch adds support of the R7S72100
in SH-Ether.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
drivers/net/sh_eth.c | 10 ---
drivers/net/sh_eth.h | 81
This fixes checkpatch's warning.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
drivers/net/sh_eth.c | 35 ++-
drivers/net/sh_eth.h | 9 -
2 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/drivers/net/sh_eth.c
'r' of rESR_RTLF is a mistake of E.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
drivers/net/sh_eth.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 2909659..d0d9aaa 100644
--- a/drivers/net/sh_eth.h
On 10/08/2013 02:13 AM, Thierry Reding wrote:
On Tue, Oct 08, 2013 at 12:42:53AM +0200, Tom Warren wrote:
This provides SPL support for T124 boards - AVP
early init, plus CPU (A15) init/jump to main U-Boot.
+#if defined(CONFIG_TEGRA124)
+ struct clk_rst_ctlr *clkrst = (struct
On 01/22/2014 01:21 PM, Stephen Warren wrote:
From: Jimmy Zhang jimmzh...@nvidia.com
Based on the Tegra114 TRM, the system clock (which is the AVP clock) can
run up to 275MHz. On power on, the default sytem clock source is set to
PLLP_OUT0. In function clock_early_init(), PLLP_OUT0 will be
Hi All,
I would like to read a configuration file from an ext4 disk partition in u-boot
and parse its contents. In order to malloc a buffer of sufficient size to read
the entire file contents, I would need to know the file size before actually
reading it.
As far as I understand, the current
On Tue, 2014-01-14 at 09:52 +0800, FengHua wrote:
hi bhupesh,
Hi David,
In reference to my mail above, I see that the transition to EL2 (from EL3)
which occurs very early
in start.S needs to be changed on lines of the ARMv7 code, i.e. the EL2
transition should happen just
before
On 14-01-22 04:29 PM, Scott Wood-2 [via U-Boot] wrote:
On Tue, 2014-01-14 at 09:52 +0800, FengHua wrote:
hi bhupesh,
Hi David,
In reference to my mail above, I see that the transition to EL2 (from EL3)
which occurs very early
in start.S needs to be changed on lines of the ARMv7 code,
Many thanks.
Pantelis and York
How about below patch?
http://patchwork.ozlabs.org/patch/283002/
It's about esdhc, but is in york's backyard.
Regards
Haijun
On 01/22/2014 08:01 PM, Pantelis Antoniou wrote:
Hi York,
On Jan 22, 2014, at 12:01 AM, York Sun wrote:
Pantelis,
On 01/09/2014
+Tom
Hi,
On 20 January 2014 11:47, Marek Vasut ma...@denx.de wrote:
On Monday, January 20, 2014 at 01:40:52 PM, rakesh ranjan wrote:
Hi,
I have a beagle board and want to create a u-boot that verifies the
kernel
and rootfs before booting it. Any pointers on how it can be achieved will
+Stephen
Hi Frank,
On 22 January 2014 16:01, Frank Bormann fborm...@yahoo.com wrote:
Hi All,
I would like to read a configuration file from an ext4 disk partition in
u-boot and parse its contents. In order to malloc a buffer of sufficient
size to read the entire file contents, I would need
For low freq boot mode(ARM boot up with 396MHz), ROM
will not set AHB clock to 132MHz, and the reset value of
AHB divider is incorrect which will lead to wrong AHB
rate, need to correct it. To enable low freq boot mode,
need to set BOOT_CFG2[2] to high, tested on i.MX6Q/DL
SabreSD board and
Boot ROM may mask MMDC_CHx_MASK in CCM_CCDR(such as i.MX6SL TO1.2),
it will cause warm reset fail, need to clear this MMDC_CHx_MASK field
to make sure all the i.MX6 series SOCs reset function work. Otherwise,
uboot reset command will fail, tested on i.MX6SL EVK board with TO1.2.
Signed-off-by:
Hi, experts:
I found ARMv8/Exceptions.S only created a 8 items vector table.
But based on ARMv8 Arch Ref Manual, it should create 16 items in a
vector table:
Current Exception level with SP_EL0 : 4 items
Current Exception level with SP_Elx : 4 items
EL immediately lower than target_EL is using
Hello aarch64 experts,
Since commit 3865ceb (vexpress/armv7: Fix incorrect ethernet controller),
I have many warning messages when I compile vexpress board.
smc9.c: In function ‘poll4int’:
smc9.h:252:25: warning: cast to pointer from integer of different size
[-Wint-to-pointer-cast]
Hi Darwin,
-Original Message-
From: u-boot-boun...@lists.denx.de [mailto:u-boot-boun...@lists.denx.de]
On Behalf Of drambo
Sent: Thursday, January 23, 2014 12:32 AM
To: u-boot@lists.denx.de
Subject: Re: [U-Boot] how to get u-boot code with arm64: core support
Hi Bhupesh,
Hi Mashiro,
-Original Message-
From: u-boot-boun...@lists.denx.de [mailto:u-boot-boun...@lists.denx.de]
On Behalf Of Masahiro Yamada
Sent: Thursday, January 23, 2014 12:38 PM
To: u-boot@lists.denx.de
Subject: [U-Boot] Warnings on arm64 build
Hello aarch64 experts,
Since
On 01/22/2014 08:44 PM, Gerhard Sittig wrote:
On Wed, Jan 22, 2014 at 12:02 +0100, Michal Simek wrote:
--- /dev/null
+++ b/common/cmd_clk.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include common.h
+#include command.h
Hi, bhupesh and drambo:
I think current uboot ARMv8's start.S could handle EL2/EL1 case.
I have tested it on FVP model, let arm trusted firmware boot u-boot.bin.
It seemed ok.
The command I used is:
./Foundation_v8 --cores=4 --no-secure-memory --no-gicv3
--data=./bl1.bin@0x0
From: Sonic Zhang sonic.zh...@analog.com
Signed-off-by: Sonic Zhang sonic.zh...@analog.com
---
arch/blackfin/lib/board.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c
index 392d72d..facbc7a 100644
---
From: Bob Liu lliu...@gmail.com
Signed-off-by: Bob Liu lliu...@gmail.com
Signed-off-by: Sonic Zhang sonic.zh...@analog.com
---
arch/blackfin/cpu/start.S |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/blackfin/cpu/start.S b/arch/blackfin/cpu/start.S
index
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com
As per the below commit
mmc: sdhci: add the quirk for broken r1b response
(sha1: 3a6383207be3f71b39004e64464a6e99290b16fa)
need to add quirk SDHCI_QUIRK_BROKEN_R1B, when the
response type is R1b.
Signed-off-by: Siva Durga Prasad
From: Novasys Ingenierie xil...@novasys-ingenierie.com
When ARCH_DMA_MINALIGN is greater than header size of the bit file, and buf is
not aligned, new_buf address became greater then buf_start address and the
load_word loop corrupts bit file data.
A work around is to decrease new_buf of
From: Aaron Wu aaron...@analog.com
EMAC_VLANx regs is not properly initiallized in u-boot, once it's overwrite in
the
kernel when DSA enabled, hot reset will lead to bringing up EMAC fail in u-boot.
Signed-off-by: Aaron Wu aaron...@analog.com
Signed-off-by: Sonic Zhang sonic.zh...@analog.com
From: Michael Burr michael.b...@logicpd.com
Fixed bug with alen == 0 in 'i2c_write', 'i2c_read'
Further minor corrections:
- Write 'address' register before 'data' register.
- Write 'transfer_size' register before 'address' register.
Signed-off-by: Michael Burr michael.b...@logicpd.com
From: Michael Burr michael.b...@logicpd.com
Initialize the second i2c controller.
Signed-off-by: Michael Burr michael.b...@logicpd.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2: None
Changes in v1:
- Based on original thread from Michael Burr
Hi All,
The T4240 on the T4QDS board is a PPC e6500 core (64 bit), but it is
configured in U-Boot as an e500 core, which is 32 bit. Why is this? Can
it be updated to e6500?
This leads directly into another question: can U-Boot be compiled and
run 64-bit? So far, I have been unable to make
Timeout calculation should be out of the data loop.
This patch increase spi bandwidth for 30%.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/spi/xilinx_spi.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/xilinx_spi.c
From: Sonic Zhang sonic.zh...@analog.com
Signed-off-by: Sonic Zhang sonic.zh...@analog.com
---
include/configs/bf609-ezkit.h | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h
index
On 21/01/2014 22:00, Marek Vasut wrote:
The name the Linux kernel expects is 'mxc_nand' , not 'mxc-nand' .
This patch renames the driver name.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Stefano Babic sba...@denx.de
---
include/configs/m53evk.h | 4 ++--
1 file changed, 2 insertions(+),
Dear Danny Gale,
In message 52df18b3.1080...@coloradoengineeringinc.com you wrote:
The T4240 on the T4QDS board is a PPC e6500 core (64 bit), but it is
configured in U-Boot as an e500 core, which is 32 bit. Why is this?
Becuase it simply works :-)
Can it be updated to e6500?
Yes - if you
Hi Alexey,
I failed to apply your patch on the 2014.01 release head.
Regards,
Sonic Zhang
Applying: net/designware - switch driver to phylib usage
/home/sonic/projects/u-boot-blackfin.up/.git/rebase-apply/patch:66:
space before tab in indent.
u16 val)
error: patch
Zynq common configuration is placed in zynq-common.h
not zynq_common.h.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
include/configs/zynq_zc70x.h | 2 +-
include/configs/zynq_zed.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/configs/zynq_zc70x.h
Enable dcache.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm/cpu/armv7/zynq/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c
index 9af340e..c771759 100644
--- a/arch/arm/cpu/armv7/zynq/cpu.c
+++
icache is already enabled by default.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
board/xilinx/zynq/board.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index a5b9bde..08932a2 100644
--- a/board/xilinx/zynq/board.c
+++
Extend max kernel image size. Gunzip is checking
this value. If kernel is larger, message below is shown.
Uncompressing Kernel Image ... Error: inflate() returned -5
GUNZIP: uncompress, out-of-mem or overwrite error -
must RESET board to recover
Signed-off-by: Michal Simek
For saving content of memory via tftp to file.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
include/configs/zynq-common.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 08b53d0..6591372 100644
---
These numbers will be reused by SPL.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm/include/asm/arch-zynq/hardware.h | 6 ++
board/xilinx/zynq/board.c | 6 --
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git
board_eth_init can be also called in cases where CMD_NET
is not enabled.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
board/xilinx/zynq/board.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 08932a2..27aeaa4 100644
---
Hi Sonic,
On Wed, 2014-01-22 at 17:10 +0800, Sonic Zhang wrote:
Hi Alexey,
I failed to apply your patch on the 2014.01 release head.
Indeed this one requires 2 other patches which didn't made it to
mainline yet.
Do you mind to try to apply both patches
Define both serial uarts in the driver and return
default uart based on board configuration.
- Move baseaddresses to hardware.h
- Define default baudrate and clock values
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
On the top of zynq series [7/7] I have just sent.
Forget to add it on
This patch set includes changes required to:
- properly use of all gpios
- introduce common file for Samsung misc code
- keys support (PWR, VOL:UP,DOWN)
- console support on LCD
- 16bpp logo support
- introduce LCD menu on Samsung devices
Each version changes are described in each patch commit
Old s5p gpio coding method was not clean and was not working properly
for all parts and banks. New method is clean and easy to extend.
Gpio coding mask:
0x00ff - pin number
0x0000 - bank offset
0xff00 - part number
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
---
Changes
Now fimd BPP color mode depends on vl_bpp value in struct panel_info.
There is only 16BPP mode check, default mode is 24BPP.
Other fimd modes are usually unneeded and also needs some fimd driver
modifications and tests.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
---
Changes v2:
-
16 bpp mode is required by LCD console mode.
This change updates exynos board files.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
---
Changes v2:
-- new patch
Changes v3:
- none
Changes v4:
- none
Changes v5:
- none
Changes v6:
- none
board/samsung/trats/trats.c |
Changes:
- le16_to_cpu() to get_unaligned_le16()
- le32_to_cpu() to get_unaligned_le32()
when access fields in struct bmp header.
This changes avoids data abort exception caused by unaligned data access.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Acked-by: Anatolij Gustschin
Remove wrong and unused env variables
Trats2 is not as GT-I8800.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Acked-by: Jaehoon Chung jh80.ch...@samsung.com
Cc: Piotr Wilczek p.wilc...@samsung.com
---
Changes v2:
- none
Changes v3:
- none
Changes v4:
- add include pmic.h to
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