This algorithm will be useful on Tegra as well, plus we will need it for
making _psci_target_pc per-CPU.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/arm/cpu/armv7/psci.S | 14 ++
arch/arm/cpu/armv7/sunxi/psci.S | 17 +++--
2 files changed, 21
Use a per-CPU variable for saving the target PC during CPU_ON
operations. This allows us to run this service independently on targets
that have more than 2 cores and also core-local power control.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/arm/cpu/armv7/psci.S | 8 ++--
This is based on Thierry Reding's work and uses Ian Campell's
preparatory patches. It comes with full support for CPU_ON/OFF PSCI
services. The algorithm used in this version for turning CPUs on and
off was proposed by Thierry Reding in
In this case the secure code lives in RAM, and hence the memory node in
the device tree needs to be adjusted. This avoids that the OS will map
and possibly access the reservation.
Add support for setting CONFIG_ARMV7_SECURE_RESERVE_SIZE to carve out
such a region. We only support cutting off
Will be used for unpowergating CPUs.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/arm/cpu/tegra-common/powergate.c | 2 +-
arch/arm/include/asm/arch-tegra/powergate.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/tegra-common/powergate.c
This function will be used to initialize CPU power management for Tegra
SOCs. For now it does nothing.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/arm/include/asm/arch-tegra/ap.h | 5 +
board/nvidia/common/board.c | 4
2 files changed, 9 insertions(+)
diff --git
From: Ian Campbell i...@hellion.org.uk
The secure world code is relocated to the MB just below the top of 4G, we
reserve it in the FDT (by setting CONFIG_ARMV7_SECURE_RESERVE_SIZE) but it is
not protected in h/w. See next patch.
Signed-off-by: Ian Campbell i...@hellion.org.uk
Signed-off-by: Jan
We only set CNTFRQ in arch_timer_init for the boot CPU. But this has to
happen for all cores.
Fixing this resolves problems of KVM with emulating the generic
timer/counter.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/arm/cpu/armv7/tegra-common/psci.S | 13 +
1 file
From: Ian Campbell i...@hellion.org.uk
These registers can be used to prevent non-secure world from accessing a
megabyte aligned region of RAM, use them to protect the u-boot secure monitor
code.
At first I tried to do this from s_init(), however this inexplicably causes
u-boot's networking
Move parts of sunxi's psci_cpu_off into psci_cpu_off_common, namely
cache disabling and flushing, clrex and the disabling of SMP for the
dying CPU. These steps are apparently generic for ARMv7 and will be
reused for Tegra124 support.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
From: Ian Campbell i...@hellion.org.uk
I will need mc_security_cfg0/1 in a future patch and I added the rest while
debugging, so thought I might as well commit them.
Signed-off-by: Ian Campbell i...@hellion.org.uk
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
_sunxi_cpu_entry can be converted completely into a reusable
psci_cpu_entry. Tegra124 will use it as well.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/arm/cpu/armv7/psci.S | 19 +++
arch/arm/cpu/armv7/sunxi/psci.S | 21 ++---
2 files changed,
Changes in v3:
- use memory node adjustment for RAM carveout instead of reservation
- style fixes
Find patches also under
https://github.com/siemens/u-boot/tree/jetson-tk1-v3
Jan
CC: Ian Campbell i...@hellion.org.uk
Ian Campbell (3):
tegra124: Add more registers to struct mc_ctlr
On Wed, 18 Feb 2015 15:16:27 +0530
Akshay Saraswat aksha...@samsung.com wrote:
This patch adds workaround for ARM errata 798870 which says
If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B)
With driver model now we can enable both EHCI and XHCI on
Exynos5250.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
include/configs/exynos5-common.h|3 +++
include/configs/exynos5250-common.h |3 +++
include/configs/smdk5250.h |2 ++
3 files changed, 8
Add devices for XHCI-HCD and EHCI-HCD in exynos5 family.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
arch/arm/dts/exynos5.dtsi |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/dts/exynos5.dtsi b/arch/arm/dts/exynos5.dtsi
index 238acb8..5cdf406 100644
---
Hi Akshay,
This patch adds code to shutdown secondary cores.
When U-boot comes up, all secondary cores appear powered on,
which is undesirable and causes side effects while
initializing these cores in kernel.
Secondary core power down happens in following steps:
Step-1: After Exynos
On Mon, 2015-02-16 at 23:25 +0100, Hans de Goede wrote:
Add support for the 6 480x800 tl059wv5c0 panel used on e.g. Utoo P66 and
Aigo M60/M608/M606 tablets.
Signed-off-by: Hans de Goede hdego...@redhat.com
All 4 patches: Acked-by: Ian Campbell i...@hellion.org.uk
I a couple of small
This patch adds iRAM, CPU state and low power configs
which are the addresses acting as flag registers.
iROM code checks CONFIG_LOWPOWER_FLAG address. If it is equal
to CONFIG_LOWPOWER_EN then it jumps to the address (0x0202+CPUID*4).
This is a part of iROM logic. Rest other flags are being
Until yet usb_**_msg() APIs don't contain the string 'submit'.
Rename it to make things uniform. This is also helping while
adding a host translational layer wherein we are using
usb_submit_**_msg string to name APIs.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
common/usb.c
Add wrapper functions for usb layer operations for control, bulk,
interrupt transfers to accomodate support for driver model.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
common/usb.c | 99
common/usb_hub.c |2 +-
Adding a UCLASS driver for USB based on driver-model, to facilitate
binding mutiple host-controllers to their respective drivers, and
thereby enable using mutiple controllers simultaneously on a platform.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/host/Kconfig |
Adding support for driver model and necessary callbacks
in ohci/ehci/xhci.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/host/ehci-hcd.c | 36
drivers/usb/host/ohci-hcd.c | 35 ---
Hi Marek, Simon,
This patch-series comes as a update for an earlier posted series[1]
[PATCH RFC 0/2] usb: host: Add a wrapper layer for mutiple host support
which was posted long back.
We had discussion to introduce the driver model instead of the approach used
in [1]. The driver model seems
Hello,
On 02/18/2015 06:01 AM, Simon Glass wrote:
+Stephen who might have an opinion on this.
Hi Przemyslaw,
On 17 February 2015 at 06:09, Przemyslaw Marczak p.marc...@samsung.com wrote:
This commits extends:
- dm gpio ops by: 'set_pull' call
- dm gpio uclass by: dm_gpio_set_pull() function
This patch adds code to shutdown secondary cores.
When U-boot comes up, all secondary cores appear powered on,
which is undesirable and causes side effects while
initializing these cores in kernel.
Secondary core power down happens in following steps:
Step-1: After Exynos power-on, primary core
This patch series introduces changes for booting secondary CPUs
on Exynos5420 and Exynos5800.
Changes since v2:
- Patch 7 8 : Replaced #ifdef and #ifndef - if(proid_is_soc()).
- Patch 11 : Removed #ifdef from enum definition.
Changes since v1:
- Added Reviewed-by
This patch adds workaround for the ARM errata 799270 which says
If the L2 cache logic clock is stopped because of L2 inactivity,
setting or clearing the ACTLR.SMP bit might not be effective. The bit is
modified in the ACTLR, meaning a read of the register returns the
updated value. However the
iROM logic provides undesired jump address for CPU2.
This patch adds a programmable susbstitute for a part of
iROM logic which wakes up cores and provides jump addresses.
This patch creates a logic to make all secondary cores jump
to a particular address which evades the possibility of CPU2
This patch adds workaround for ARM errata 798870 which says
If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a
This commit adds implementation of driver model gpio pull
setting to s5p gpio driver.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Simon Glass s...@chromium.org
Cc: Minkyu Kang mk7.k...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
---
Changes v2:
- adjust code after
When compiled SPL for Thumb secondary cores failed to boot
at the kernel boot up. Only one core came up out of 4.
This was happening because the code relocated to the
address 0x02073000 by the primary core was an ARM asm
code which was executed by the secondary cores as if it
was a thumb code.
L2 Auxiliary Control Register provides configuration
and control options for the L2 memory system. Bit 3
of L2ACTLR stands for clean/evict push to external.
Setting bit 3 disables clean/evict which is what
this patch intends to do.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by:
From: Doug Anderson diand...@chromium.org
It was found that the L2 cache timings that we had before could cause
freezes and hangs. We should make things more robust with better
timings. Currently the production ChromeOS kernel applies these
timings, but it's nice to fixup firmware too (and
1. Renaming set_l2cache to configure_l2actlr in order to avoid
misleading comprehensions. Apparently this name suggests
that L2 cache is being set or initialized which is incorrect
as per the code in this function.
2. Cleaning missed mrc for L2 control register.
Signed-off-by: Akshay
This patch does 3 things:
1. Enables ECC by setting 21st bit of L2CTLR.
2. Restore data and tag RAM latencies to 3 cycles because iROM sets
0x3000400 L2CTLR value during switching.
3. Disable clean/evict push to external by setting 3rd bit of L2ACTLR.
We need to restore this here due to
On warm reset, all cores jump to the low_power_start function because iRAM
data is retained and because while executing iROM code all cores find
the jump flag 0x02020028 set. In low_power_start, cores check the reset
status and if true they clear the jump flag and jump back to 0x0.
The A7 cores
Hello Simon,
On 02/18/2015 06:02 AM, Simon Glass wrote:
Hi Przemyslaw,
On 17 February 2015 at 06:09, Przemyslaw Marczak p.marc...@samsung.com wrote:
Before this commit, the mmc devices were always registered
in the same order. So dwmmc channel 0 was registered as mmc 0,
channel 1 as mmc 1,
Before this commit, the mmc devices were always registered
in the same order. So dwmmc channel 0 was registered as mmc 0,
channel 1 as mmc 1, etc.
In case of possibility to boot from more then one device,
the CONFIG_SYS_MMC_ENV_DEV should always point to right mmc device.
This can be achieved by
This commits extends:
- dm gpio ops by: 'set_pull' call
- dm gpio uclass by: dm_gpio_set_pull() function
The pull modes are defined by proper enum and can be:
- UP
- DOWN
- NONE
- UNKNOWN
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
CC: Simon Glass s...@chromium.org
Reviewed-by: Simon
The dw mmc driver init priority was always the same: ch 0, ch 1, ch 2.
On some boards (e.g. Odroid XU3) the dwmmc driver is enabled for all
mmc channels. In this case, when boot device is switchable (SD/eMMC),
the default MMC device will be 0 or 1.
Change the init priority to boot device, always
Depending on the boot priority, the eMMC/SD cards,
can be initialized with the same numbers for each boot.
To be sure which mmc device is SD and which is eMMC,
this info is printed by 'mmc list' command, when
the init is done.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Pantelis
On Wed, 18 Feb 2015 15:16:28 +0530
Akshay Saraswat aksha...@samsung.com wrote:
This patch adds workaround for the ARM errata 799270 which says
If the L2 cache logic clock is stopped because of L2 inactivity,
setting or clearing the ACTLR.SMP bit might not be effective. The bit is
modified in
Hi,
Here's what I think happens:
When working with large TFTP packets (probably 4096 bytes, as set in
your board config file), U-Boot TFTP code sends wrong acknowledges for
the TFTP packets. If the TFTP server implementation is too strict (the
OpenBSD server is a good example), the transfer
Hi Andreas, for OMAP3 and AM35xx boards, it would have been ok omitting the
CONFIG_BCH check and simply use CONFIG_NAND_OMAP_ECCSCHEME.
Those boards use the ecc scheme config already. However I just wasn't 100%
sure if I could rely on this config for all TI OMAP/AM based boards. I know
OMAP3
and
I am trying to bring up xen suing u-boot that has this patch. Unfortunately as
soon as the code tries to call _nonsec_init through secure_ram_addr in
arm7_init_nonsec function in virt-v7.c I get an undefined instruction
exception. I suspect the CONFIG_ARMV7_SECURE_BASE needs to be defined to a
Hello Rob,
Sorry for delay.
On 01/26/2015 04:44 PM, Rob Herring wrote:
Currently, an environment variable must be used to store the randomly
generated UUID for each partition. This is not necessary, so make storing
the UUID optional. Now passing uuid_disk and uuid are optional when random
Hello Rob,
On 01/26/2015 04:43 PM, Rob Herring wrote:
The gpt command always reports success even if writing the partition table
failed. Propagate the return value of gpt_restore so we get proper status
reported.
Signed-off-by: Rob Herring r...@kernel.org
---
common/cmd_gpt.c | 4 ++--
1
On Tue, Feb 17, 2015 at 04:47:14PM -0800, Adam Lee wrote:
I have a Gumstix Overo (OMAP3) with a 512MiB NAND. I have been validating
BCH8 ecc scheme and one of the problems I ran into is this:
arm-linux-gnueabi-ld.bfd: u-boot-spl section `.rodata' will not fit in
region `.sram'
Had a conversation with Ash @ Gumstix and he pointed out relying on
CONFIG_NAND_OMAP_ECCSCHEME could be dangerous as it could be anything other
than the two SW ECC schemes available for OMAP3.
Also it looks like making a selection between OMAP_ECC_BCH8_CODE_HW and
This patch adds functionality to getvar command to get the userdata partition
size.
Signed-off-by: Dileep Katta dileep.ka...@linaro.org
---
common/fb_mmc.c | 38 ++
drivers/usb/gadget/f_fastboot.c | 2 ++
include/fb_mmc.h| 2
On Tue, Feb 17, 2015 at 08:22:17PM -0700, Simon Glass wrote:
+tom, and pruning the cc list a little
Hi,
On 26 January 2015 at 18:27, Simon Glass s...@chromium.org wrote:
This series adds debug UART infrastructure which can in principle be used on
any architecture. It works best with
Add a uclass for PCI controllers and a generic one for PCI devices. Adjust
the 'pci' command and the existing PCI support to work with this new uclass.
Keep most of the compatibility code in a separate file so that it can be
removed one day.
TODO: Add more header file comments to the new parts of
Since sandbox does not have real devices (unless it borrows those from the
host) it must use emulations. Provide a uclass which permits PCI operations
to be passed through to an emulation device.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/pci/Makefile | 1 +
Move coreboot-x86 over to driver model for PCI.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/cpu/coreboot/pci.c | 63 ++---
arch/x86/dts/chromebook_link.dts| 7 +
board/google/chromebook_link/link.c | 9 ++
This function returns -ENOENT when the property is missing (which the caller
might forgive) and also when the property is present but incorrectly
formatted (which many callers would like to report).
Update the error return value to allow these different situations to be
distinguished.
Both of these values are useful for understanding what is going on, so show
them both.
The requested number comes from a device tree alias. The allocated one is
set up when the device is activated, and is unique throughout the uclass.
Signed-off-by: Simon Glass s...@chromium.org
---
This function does not unmap what it maps. Correct it.
Signed-off-by: Simon Glass s...@chromium.org
---
common/cmd_mem.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/common/cmd_mem.c b/common/cmd_mem.c
index bcb3ee3..855aa57 100644
--- a/common/cmd_mem.c
+++
Add some basic tests to check that things work as expected with sandbox.
Signed-off-by: Simon Glass s...@chromium.org
---
test/dm/Makefile | 1 +
test/dm/pci.c| 59
test/dm/test.dts | 17
3 files changed, 77
On Wednesday, February 18, 2015 at 04:04:07 AM, Tom Rini wrote:
On Tue, Feb 17, 2015 at 09:11:01PM +0100, Marek Vasut wrote:
Hi Tom,
SoCFPGA stuff for current release.
The following changes since commit 7f641d53bbb3a426a3bfb132d8346153e86a9d08:
Merge branch 'master' of
Since device_unbind() is also defined in device-remove.c,
which is compiled in only in case CONFIG_DM_DEVICE_REMOVE
is defined, protect the device_unbind() prototype with the
same CONFIG_DM_DEVICE_REMOVE check.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Simon Glass s...@chromium.org
Cc: Stefan
Enable DM in case these two drivers are enabled, since these
two drivers depend on DM.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Simon Glass s...@chromium.org
Cc: Stefan Roese s...@denx.de
Cc: Tom Rini tr...@ti.com
---
include/configs/socfpga_common.h | 4
1 file changed, 4 insertions(+)
This series is a collection of changes in core DM, sandbox, x86 and PCI code
to implement a PCI uclass and associated operations. Some basic tests are
provided as well.
As is becoming common with DM conversions, the existing structure (here
struct pci_controller) becomes per-bus uclass data.
Add a driver which can access emulations of devices and make them available
in sandbox.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/pci/Kconfig | 10 ++
drivers/pci/Makefile | 1 +
drivers/pci/pci_sandbox.c | 79 +++
3
These functions currently use a generic name, but they are for x86 only.
This may introduce confusion and prevents U-Boot from using these names
more widely.
In fact it should be possible to remove these at some point and use
generic functions, but for now, rename them.
Signed-off-by: Simon
Add a convenience function to access the private data that a uclass stores
for each of its devices. Convert over most existing uses for consistency
and to provide an example for others.
Signed-off-by: Simon Glass s...@chromium.org
---
common/cmd_sf.c| 2 +-
common/cros_ec.c
Enable PCI options so that sandbox can be used for testing this bus with
driver model.
Signed-off-by: Simon Glass s...@chromium.org
---
configs/sandbox_defconfig | 3 +++
include/configs/sandbox.h | 4
2 files changed, 7 insertions(+)
diff --git a/configs/sandbox_defconfig
At present the device is not active when the probe() method is called. But
some probe() methods want to set up the device and this can involve
accessing it through normal methods. For example a PCI bus may wish to
set up its PCI parameters using calls to pci_hose_write_config_dword() and
similar.
Move chromebook_link over to driver model for PCI.
This involves:
- adding a uclass for platform controller hub
- removing most of the existing PCI driver
- adjusting how CPU init works to use driver model instead
- rename the lpc compatible string (it will be removed later)
This does not really
At present we do more in this function than we should. Create a new
x86_post_cpu_init() which can be called from the board file when needed
(e.g. in board_early_init_f(). This allows us to use driver model for
our x86_post_cpu_init() function.
It is likely that some future refactoring will
Add a simple x86 PCI driver which uses standard functions provided by the
architecture.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/cpu/pci.c | 40
arch/x86/include/asm/pci.h | 8
arch/x86/lib/Makefile | 2 ++
This device sits on the sandbox PCI bus and provides a case-swapping
service for sandbox. It illustrates the use of both PCI I/O and PCI
memory accesses.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/misc/Makefile| 1 +
drivers/misc/swap_case.c | 285
Some uclasses want to set up a device before it is probed. Add a method
for this.
An example is with PCI, where a PCI uclass wants to set up its private
data for later use. This allows the device's uclass() method to make calls
whcih use that data (for example, read PCI memory regions from device
From: Stephen Warren swar...@nvidia.com
This is needed to correctly apply the new Jetson TK1 pinmux config.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
v2:
* Use clrbits_le32() rather than open-code read/modify/write statements.
* Update pinmux_set_tristate_input_clamping to match.
---
From: Stephen Warren swar...@nvidia.com
Syseng has revamped the Jetson TK1 pinmux spreadsheet, basing the content
completely on correct configuration for the board/schematic, rather than
the previous version which was based on the bare minimum changes relative
to another reference board.
The new
Add the required header information, device tree nodes and I/O accessor
functions to support PCI on sandbox. All devices are emulated by drivers
which can be added as required for testing or development.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/sandbox/Kconfig
The 'nandecc sw' command selects a software-based error correction
algorithm. By default, this is OMAP_ECC_HAM1_CODE_SW but some
platforms use OMAP_ECC_BCH8_CODE_HW_DETECTION_SW as their
software-based correction algorithm. Allow a user to be specific e.g.
# nandecc sw hamming|bch8
where
This strdup() is missing a check. Add it.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/i2c/i2c-uclass.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c
index a6991bf..b890806 100644
--- a/drivers/i2c/i2c-uclass.c
+++
Driver model will share many functions with the existing PCI implementation.
Move these into their own file to avoid duplication and confusion.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/pci/Makefile | 2 +-
drivers/pci/pci.c| 281
These are missing a size value. Add one in each case.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/sandbox/dts/sandbox.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts
index 9ce31bf..1ccfdee 100644
This function is missing a prototype but is more widey useful. Add it.
Signed-off-by: Simon Glass s...@chromium.org
---
include/fdtdec.h | 11 +++
lib/fdtdec.c | 2 +-
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/include/fdtdec.h b/include/fdtdec.h
index
On Wed, Feb 18, 2015 at 12:20:25AM +0100, Andreas Bießmann wrote:
Hi Tom,
reworked pull request for avr32 generic board support.
The following changes since commit 5745f8c4fd5807becf7f246625e153388293aedc:
Merge git://git.denx.de/u-boot-marvell (2015-02-16 08:44:03 -0500)
are
On Wed, Feb 18, 2015 at 06:09:28AM -0700, Simon Glass wrote:
Hi Tom,
The following changes since commit 5745f8c4fd5807becf7f246625e153388293aedc:
Merge git://git.denx.de/u-boot-marvell (2015-02-16 08:44:03 -0500)
are available in the git repository at:
On 02/17/2015 01:22 PM, Tom Rini wrote:
On Tue, Feb 17, 2015 at 12:35:41PM -0700, Stephen Warren wrote:
On 02/16/2015 06:03 PM, Tom Rini wrote:
On Mon, Feb 16, 2015 at 12:16:15PM -0700, Stephen Warren
wrote:
USB doesn't seem to work yet; the controller detects the
on-board Hub/ Ethernet
Hello Simon,
Am 18.02.2015 22:10, schrieb Simon Glass:
This strdup() is missing a check. Add it.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/i2c/i2c-uclass.c | 2 ++
1 file changed, 2 insertions(+)
Good catch, Thanks!
Acked-by: Heiko Schocher h...@denx.de
bye,
Heiko
diff
Masahiro Yamada (4):
ARM: UniPhier: set CONFIG_SYS_MALLOC_F to the global default value
malloc_f: fix broken .config caused by CONFIG_SYS_MALLOC_F
kconfig: switch to single .config configuration
kconfig: remove unneeded dependency on !SPL_BUILD
Kconfig
Since commit b724bd7d6349 (dm: Kconfig: Move CONFIG_SYS_MALLOC_F_LEN
to Kconfig), the .config created by the configuration has been
wrong.
For example, the following is a snippet of the .config generated
by make beaver_defconfig:
---8-
It is true that malloc is necessary for Driver Model before
relocation, but there is no good reason to reserve the malloc
space more than enough. The default value 0x400 works well.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
Changes in v2: None
When Kconfig for U-boot was examined, one of the biggest issues was
how to support multiple images (Normal, SPL, TPL). There were
actually two options, single .config and multiple .config.
After some discussions and thought experiments, I chose the latter,
i.e. to create .config, spl/.config,
Since commit b724bd7d6349 (dm: Kconfig: Move CONFIG_SYS_MALLOC_F_LEN
to Kconfig), the .config created by the configuration has been
wrong.
For example, the following is a snippet of the .config generated
by make beaver_defconfig:
---8-
It is true that malloc is necessary for Driver Model before
relocation, but there is no good reason to reserve the malloc
space more than enough. The default value 0x400 works well.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
arch/arm/cpu/armv7/uniphier/Kconfig | 2 +-
1 file
Now CONFIG_SPL_BUILD is not defined in Kconfig, so
!depends on SPL_BUILD arn if !SPL_BUILD are redundant.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
Kconfig | 12 ++--
arch/arm/Kconfig| 7 +++
Hello,
I have a Samsung Exynos 5420 Arndale Octa Board and I am trying to run Xen
4.5 on it.
I have successfully managed to configure and patch XEN and the kernel for
the board.
The problem is that XEN doesn't match the correct CPU mode for its boot.
-XEN early debug-
Hello,
On 02/18/2015 05:32 AM, Simon Glass wrote:
Hi Przemyslaw,
On 16 February 2015 at 08:21, Przemyslaw Marczak p.marc...@samsung.com wrote:
Hello,
On 02/16/2015 04:13 PM, Przemyslaw Marczak wrote:
For ARM architecture, enable the CONFIG_USE_ARCH_MEMSET/MEMCPY,
will highly increase the
Hi Simon,
On 02/18/2015 05:32 AM, Simon Glass wrote:
Hi Przemyslaw,
On 16 February 2015 at 08:13, Przemyslaw Marczak p.marc...@samsung.com wrote:
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
---
Kconfig | 26 +++---
1 file changed, 19 insertions(+), 7
Hi Tom,
The following changes since commit 5745f8c4fd5807becf7f246625e153388293aedc:
Merge git://git.denx.de/u-boot-marvell (2015-02-16 08:44:03 -0500)
are available in the git repository at:
http://git.denx.de/u-boot-fdt.git
for you to fetch changes up to
Hello,
On 02/18/2015 05:23 AM, Simon Glass wrote:
On 16 February 2015 at 08:13, Przemyslaw Marczak p.marc...@samsung.com wrote:
This commit enables the following configs:
- CONFIG_USE_ARCH_MEMCPY
- CONFIG_USE_ARCH_MEMSET
This increases the performance of memcpy/memset
and also reduces the boot
Hello Stephen,
On 02/17/2015 11:39 PM, Stephen Warren wrote:
On 02/17/2015 02:43 PM, Stephen Warren wrote:
On 02/16/2015 08:13 AM, Przemyslaw Marczak wrote:
This patchset reduces the boot time for ARM architecture,
Exynos boards, and boards with DFU enabled.
I tested this series on NVIDIA's
Hi Simon,
On Wed, Feb 18, 2015 at 6:45 PM, Simon Glass s...@chromium.org wrote:
+mailing list
On 18 February 2015 at 06:14, Simon Glass s...@chromium.org wrote:
Hi Vivek,
On 18 February 2015 at 03:40, Vivek Gautam gautam.vi...@samsung.com wrote:
Hi Marek, Simon,
This patch-series comes
Hi Tom,
On Wed, 2015-02-18 at 15:35 +0300, Alexey Brodkin wrote:
Hi Tom,
Could you please pull those changes?
Just realized you already pulled my the changes.
Probably I missed your reply and was too lazy to check latest changes in
U-Boot at say http://git.denx.de/?p=u-boot.git;a=shortlog
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