On 01/29/2016 08:42 PM, Daniel Schwierzeck wrote:
>
> Am 28.01.2016 um 11:00 schrieb Purna Chandra Mandal:
>> This adds support for Microchip PIC32MZ[DA] StarterKit board
>> based on a PIC32MZ[DA] family of microcontroller.
>>
>> Signed-off-by: Purna Chandra Mandal
> Reviewed-by: Daniel Schwierze
Dear u-boot team,
Occasionally, I get corrupted rootfs if the system power goes away
while u-boot is attaching the root file system in order to fetch the
kernel.
I am using imx6 Solo and u-boot 2013-10.
Is there any way to stop uboot messing up the file system while making
attachment of UBI? Doe
change the get_medium_size() function from
- long (*get_medium_size)(struct dfu_entity *dfu);
+ int (*get_medium_size)(struct dfu_entity *dfu, long long *size);
so it can return bigger medium sizes than 2GiB, and the return
value is seperate from the size.
Signed-off-by: Heiko Schoche
With the new dfu_mtd layer, now dfu supports reading/writing
to mtd partitions, found on mtd devices. With this approach
it is also possible to read/write to concatenated mtd
devices.
Signed-off-by: Heiko Schocher
---
This patch is based on patch:
dfu: allow get_medium_size() to return bigger me
Hello Andy,
Am 01.02.2016 um 09:58 schrieb Andy Ng:
Dear u-boot team,
Occasionally, I get corrupted rootfs if the system power goes away
while u-boot is attaching the root file system in order to fetch the
kernel.
I am using imx6 Solo and u-boot 2013-10.
Is there any way to stop uboot messing
Unprotecting SPI flash is now handled in the SPI controller driver,
via a call to the PCH driver. Drop the ad-hoc version.
Signed-off-by: Bin Meng
---
arch/x86/cpu/queensbay/tnc.c | 16
include/configs/crownbay.h | 1 -
2 files changed, 17 deletions(-)
diff --git a/arch/x86
The ICH SPI controller supports two variants, one of which is ICH7
compatible and the other is ICH9 compatible. Change 'pch_version'
to 'ich_version' to better match its original name.
Signed-off-by: Bin Meng
---
drivers/spi/ich.c | 14 +++---
drivers/spi/ich.h | 7 ++-
2 files cha
At present ich spi driver gets the controller version information via
pch, but this can be simply retrieved via spi node's compatible string.
Signed-off-by: Bin Meng
---
arch/x86/dts/bayleybay.dts | 2 +-
arch/x86/dts/broadwell_som-6896.dts | 2 +-
arch/x86/dts/chromebook_link.dts
This cleans up the ich spi driver a little bit:
- Remove struct ich_spi_slave that is not referenced anywhere
- Remove ending period in some comments
- Move struct ich_spi_platdata and struct ich_spi_priv to ich.h
- Add #ifndef _ICH_H_ .. in ich.h
Signed-off-by: Bin Meng
---
drivers/spi/ich.c |
There are still some codes that use the legacy PCI APIs to access
the configuration space registers. This series converts those codes
to completely use DM PCI APIs.
This includes adding several new ops to the PCH uclass driver, and
some clean up to the SPI/GPIO/IRQ drivers.
Tested on QEMU and Cro
Unprotecting SPI flash is now handled in the SPI controller driver,
via a call to the PCH driver. Drop the ad-hoc version.
Signed-off-by: Bin Meng
---
arch/x86/cpu/quark/quark.c | 17 -
1 file changed, 17 deletions(-)
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark
Implement get_gpio_base op for bd82x6x, pch7 and pch9 drivers.
Signed-off-by: Bin Meng
---
arch/x86/cpu/ivybridge/bd82x6x.c | 33 +
drivers/pch/pch7.c | 33 +
drivers/pch/pch9.c | 33
On some newer chipset (eg: BayTrail), there is an IO base address
register on the PCH device which configures the base address of a
memory-mapped I/O controller.
Signed-off-by: Bin Meng
---
drivers/pch/pch-uclass.c | 11 +++
include/pch.h| 18 ++
2 files chan
pch_get_version op was only used by the ich spi controller driver,
and does not really provide a good identification of pch controller
so far, since we see plenty of Intel PCH chipsets and one differs
from another a lot, which is not simply either a PCHV_7 or PCHV_9.
Now that ich spi controller dri
x86 GPIO registers are accessed via I/O port whose base address is
configured in a PCI configuration register on the PCH device. Add
an op get_gpio_base to get the GPIO base address from PCH.
Signed-off-by: Bin Meng
---
drivers/pch/pch-uclass.c | 11 +++
include/pch.h| 18 ++
IO_BASE is only seen on PCH9 device, implement the get_io_base op.
Signed-off-by: Bin Meng
---
drivers/pch/pch9.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/pch/pch9.c b/drivers/pch/pch9.c
index 2a212ce..910eb61 100644
--- a/drivers/pch/pch9.c
+++ b/drivers/p
Spell out 'sbase' to 'spi_base' so that it looks clearer.
Signed-off-by: Bin Meng
---
arch/x86/cpu/ivybridge/bd82x6x.c | 4 ++--
drivers/pch/pch-uclass.c | 6 +++---
drivers/pch/pch7.c | 4 ++--
drivers/pch/pch9.c | 4 ++--
drivers/spi/ich.c|
So far disable_igd() does not have any return value, but we may need
that in the future.
Signed-off-by: Bin Meng
---
arch/x86/cpu/queensbay/tnc.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index f9fd
At present this GPIO driver still uses the legacy PCI API. Now that
we have proper PCH drivers we can use those to obtain the information
we need. While the device tree has nodes for the GPIO peripheral it is
not in the right place. It should be on the PCI bus as a sub-peripheral
of the PCH device.
asm/arch/gpio.h is not needed anymore as we get the GPIO base from
PCH driver.
Signed-off-by: Bin Meng
---
arch/x86/include/asm/arch-baytrail/gpio.h | 13 -
arch/x86/include/asm/arch-coreboot/gpio.h | 13 -
arch/x86/include/asm/arch-efi/gpio.h | 10 --
ar
At present irq_router is declared as a static struct irq_router in
arch/x86/cpu/irq.c. Since it's a driver control block, it makes sense
to move it to a per driver priv. Adjust existing APIs to accept an
additional parameter of irq_router's udevice.
Signed-off-by: Bin Meng
---
arch/x86/cpu/irq.
Once we get udevice of IGD and SDVO, we can use its udevice to
access PCI configuration space with dm_pci_write_config32().
Signed-off-by: Bin Meng
---
arch/x86/cpu/queensbay/tnc.c | 22 +++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/arch/x86/cpu/queensbay
Drop legacy PCI APIs usage in pci_assign_irqs() as well.
Signed-off-by: Bin Meng
---
arch/x86/cpu/pci.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c
index 7a31260..9cad57e 100644
--- a/arch/x86/cpu/pci.c
+++ b/arch/x86/cpu/pci
There is no need to parse PCH's property as we have already
a DM PCI API dm_pci_get_bdf() that can handle this.
Signed-off-by: Bin Meng
---
arch/x86/cpu/irq.c | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index 0b36ace..cc02
With recent DM PCI changes to vesa_fb driver, external graphics
card does not work any more. This is because: after setting the
function disable bit, IGD and SDVO devices will disappear in the
PCI configuration space. This however creates an inconsistent state
from a driver model PCI controller poi
IOBASE is now obtained from PCH driver, drop this property.
Signed-off-by: Bin Meng
---
arch/x86/dts/minnowmax.dts | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index b7e3ba4..60bd05a 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arc
Now that we have irq router's udevice passed as a parameter, it's
time to start using the DM PCI API instead of those legacy ones.
Signed-off-by: Bin Meng
---
arch/x86/cpu/irq.c | 6 +++---
arch/x86/cpu/queensbay/irq.c | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --g
Use pci_[read|write]_config intead of x86_pci_[read|write]_config.
Signed-off-by: Bin Meng
---
arch/x86/cpu/qemu/qemu.c | 34 +-
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index f8af566..7ad
Now that we have converted all x86 codes to use DM PCI APIs,
drop those legacy ones.
Signed-off-by: Bin Meng
---
arch/x86/cpu/pci.c | 53 --
arch/x86/include/asm/pci.h | 12 ---
2 files changed, 65 deletions(-)
diff --git a/arch/x86/
The DDR3-SDRAM initialization sequence is implemented in
accordance with the DDR3-SRAM/DDR3L-SDRAM initialization section
described in the SAMA5D2 datasheet.
Add registers and definitions of mpddrc controller, which is used
to support DDR3 devices.
Signed-off-by: Wenyou Yang
Reviewed-by: Andreas
This patch series is to add DDR3-SDRAM initialzation sequence
support. The DDR3-SDRAM initialization sequence is implemented in
accordance with the DDR3-SRAM/DDR3L-SDRAM initialization section
described in the SAMA5D2 datasheet.
Changes in v3:
- fix unchanged board files (at91sam9m10ek, at91sam9n
Add struct atmel_mpddrc_config to accommodate the mpddrc register
configurations, not using the mpddrc register map structure,
struct atmel_mpddrc, in order to increase readability and reduce
run-time memory use.
Signed-off-by: Wenyou Yang
Reviewed-by: Andreas Bießmann
---
Changes in v3:
- fix
To remove the unnecessary #ifdef-endif, use the mpddrc IP version
to check whether or not the interleaved decoding type is supported.
Signed-off-by: Wenyou Yang
Reviewed-by: Andreas Bießmann
---
Changes in v3:
- add "base" argument for ddr2_decodtype_is_seq() to avoid
specified base address
The sama5d2 Xplained SPL supports the boot medias: spi flash
and SD Card.
Signed-off-by: Wenyou Yang
---
This patch is base on [U-Boot] [PATCH v3 0/3] arm: at91/spl: add DDR3-SDRAM
initialization support
http://lists.denx.de/pipermail/u-boot/2016-February/244228.html
Changes in v2:
- a
Added missing parameter 'u-boot,dm-pre-reloc' for qspi and
flash0 in dts file arch/arm/dts/socfpga_cyclone5_socdk.dts
to make it support booting from QSPI flash.
Signed-off-by: shengjiangwu
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Dinh Nguyen
Cc: Pavel Machek
Cc: Marek Vasut
Cc: Stefan Roese
UBIFS is the preferred FS, and YAFFS isn't officially included in
Linux. Removing this feature reduces the code size.
Signed-off-by: Adam Ford
---
include/configs/omap3_logic.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
ind
Hi Simon,
On 31.1.2016 17:16, Simon Glass wrote:
> Hi Michal,
>
> I notice that the only user of this driver appears to be a board you
> maintain. Do you think you could convert this to driver model? Please
> see doc/driver-model/serial-howto.txt.
>
> I'm hoping you might have hardware to test w
Secure Boot ESBC has been enabled on FSL LS208x platforms.
This patchset is dependent on
http://patchwork.ozlabs.org/patch/571612/
Changes for v2:
- changed function fsl_secboot_validate to return address of image
- corrected Bootscript header for ls1043 and ls1021
Changes for v3:
In LS2080/LS2085, SFP is LE and Ver is 3.4
The base address is 0x01e80200
SFP will be used in Secure Boot to read fuses.
Signed-off-by: Aneesh Bansal
Signed-off-by: Saksham Jain
---
Changes for v2:
- No changes
Changes for v3:
- No changes
arch/arm/include/asm/arch-fsl-layerscap
For ls2080, Added configs for various IPs used during secure boot
Added address and endianness for SEC and Security Monitor.
SRK - Fuses in SFP (Fused for public keys hash)
These are stored in LE format.
Signed-off-by: Aneesh Bansal
Signed-off-by: Saksham Jain
---
Changes for v2:
- No c
During secure boot, Linux image along with other images are validated
using bootscript. This bootscript also needs to be validated before
it is executed. This requires a header for bootscript.
When secure boot is enabled, default bootcmd is changed to first validate
bootscript using the header and
Following changes have been made to enable secure boot:
1) Sec_init has been called in starting to initialize SEC Block (CAAM)
which will be used for Secure Boot validation later for both ls2080a qds
and rdb
2) 64Bit address in ESBC Header has been enabled as this SoC is based on
armv8
3) Secure Bo
For Secure Boot, a header is used to identify key table, signature
and image address. For LS-CH3, there is a new header structure being used.
The following changes are there in the new header:
1) Currently IE Table (Key extension) feature is not supported
2) Single Key feature is not supported. Ke
During Secure Boot, a bootscript is validated using its header.
This patch copies both these images to DDR from NOR and then validates and
executed them from DDR. (If NOR is the boot source for LS2080 and LS2085).
This copy step is done to make this step common across booting sources.
Because in c
"fdt_high" env variable has been changed to 0xa000 for ls2080a
and ls2085a during Secure Boot. This env_varible is used to specify
the upper limit to be used for copying flat device tree.
This address must be visible to kernel.
The "fdt_high" value has been set during Secure Boot to same value
The GUR (DCFG) registers in CCSR space are in LE format
for ls2080/ls2085. Defined a config CONFIG_SYS_FSL_CCSR_GUR_LE in
arch/arm/include/asm/arch-fsl-layerscape/config.h
Signed-off-by: Aneesh Bansal
Signed-off-by: Saksham Jain
---
Changes for v2:
- No changes
Changes for v3:
-
During secure boot, SMMU is enabled on POR by SP bootrom.
SMMU needs to be put in Bypass mode in uboot to
enable CAAM transcations to pass through.
During Nonsecure Boot, SP BootROM doesn't enable SMMU and
at reset SMMU is in bypass mode.
Signed-off-by: Aneesh Bansal
Signed-off-by: Saksham Jain
When MMU is disabled, 64bit Write must be at a memory aligned at
64bit Boundary. So, this commit splits the 64bit write into 2 -32bit
writes as the memory location is not guaranteed to be 64bit aligned.
The alignment exception only occurs when MMU is disabled.
Signed-off-by: Aneesh Bansal
Signed-
To solve CAAM coherency issue on ls2080a and ls2085a.
When Caches are enabled and CAAM's DMA's AXI transcations are not
made cacheable, Core reads/write data from/to Caches and CAAM does from
Main Memory. This forces data flushes to synchronize various data structures
But even if any data in proxim
For secure boot, currently we were using fixed bootargs for
all SoCs. This is not needed and we can use the bootargs
which are used in non-secure boot.
Incase bootargs are not defined for non-secure boot of any
platform, we use default bootargs.
Signed-off-by: Aneesh Bansal
Signed-off-by: Saksham
Currently, fsl_secboot_validate function used to set env variable "img_addr"
to contain address of image being validated.
The function has been changed to output image addr via argument
img_addr_ptr. The command esbc_validate sets the env variable
"img_addr".
This change helps when fsl_secboot_va
In case of fatal failure during secure boot execution (e.g. header not found)
it is needed that the execution stops.
Earlier, we were asserting reset request in case in case of failure. But if
the RESET_REQ is not tied off to HRESET, this allows the execution to continue.
This can either be taken
For validating images from uboot (Such as Kernel Image), either keys
from SoC fuses can be used or keys from a veriied table of public keys
can be used. The latter feature is called IE Key Extension Feature.
For earlier SoCs, BootROM used to verify IE Key Table and then write the
address of this t
From: Fabio Estevam
Since commit 59370f3fcd1350 ("net: phy: delay only if reset handler is
registered") Ethernet is no longer functional.
This commit does not have an issue in itself, but it revelead a problem
with the Ethernet initialization.
According to the LAN8720 datasheet tpurstd (time th
From: Fabio Estevam
According to the LAN8720 datasheet tpurstd (time that reset line should
stay asserted) is 25ms.
So do as suggested by the LAN8720 datasheet.
Signed-off-by: Fabio Estevam
---
board/tqc/tqma6/tqma6_wru4.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/bo
Hi!
I'm currently porting the Marvell mvpp2 driver for the Armada 375
to U-Boot. This controller is a bit different, as it exposes
multiple interfaces per controller. In this specific case its
2 interfaces. Here the current dts node:
/* Network controller */
ethernet@f {
Thank you for your reply.
by going to update u-boot, does it guaranty corruption free UBI if the
power goes away during the phase where u-boot fetches uImage from the
ubifs?
best regards,
Andy
On Mon, Feb 1, 2016 at 9:34 AM, Heiko Schocher wrote:
> Hello Andy,
>
> Am 01.02.2016 um 09:58 schrieb
Author: Vishwas Srivastava
Date: Mon Jan 25 21:28:17 2016 +0530
Wrong Initialization in davinci emac driver
emac module of the davinci platform supports only 8 tx and 8
rx channels (total 16). emac driver for davinci platform,
however, while doing initialization of the dma descriptor
head poin
On 01/31/2016 11:16 PM, Mingkai Hu wrote:
> From: Mingkai Hu
>
> Memory controller performance is not optimal with default internal
> target queue register value, write required value for optimal DDR
> performance.
>
> Signed-off-by: Mingkai Hu
> ---
> v2:
> - Add a check to make sure A009660
On 1 February 2016 at 02:40, Bin Meng wrote:
>
> This cleans up the ich spi driver a little bit:
> - Remove struct ich_spi_slave that is not referenced anywhere
> - Remove ending period in some comments
> - Move struct ich_spi_platdata and struct ich_spi_priv to ich.h
> - Add #ifndef _ICH_H_ .. in
Hi Bin,
On 1 February 2016 at 02:40, Bin Meng wrote:
> There are still some codes that use the legacy PCI APIs to access
> the configuration space registers. This series converts those codes
> to completely use DM PCI APIs.
>
> This includes adding several new ops to the PCH uclass driver, and
>
On 1 February 2016 at 02:40, Bin Meng wrote:
> Unprotecting SPI flash is now handled in the SPI controller driver,
> via a call to the PCH driver. Drop the ad-hoc version.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/cpu/queensbay/tnc.c | 16
> include/configs/crownbay.h |
On 1 February 2016 at 02:40, Bin Meng wrote:
> At present ich spi driver gets the controller version information via
> pch, but this can be simply retrieved via spi node's compatible string.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/dts/bayleybay.dts | 2 +-
> arch/x86/dts/broadwe
On 1 February 2016 at 02:40, Bin Meng wrote:
> The ICH SPI controller supports two variants, one of which is ICH7
> compatible and the other is ICH9 compatible. Change 'pch_version'
> to 'ich_version' to better match its original name.
>
> Signed-off-by: Bin Meng
> ---
>
> drivers/spi/ich.c | 14
On 1 February 2016 at 02:40, Bin Meng wrote:
> pch_get_version op was only used by the ich spi controller driver,
> and does not really provide a good identification of pch controller
> so far, since we see plenty of Intel PCH chipsets and one differs
> from another a lot, which is not simply eith
On 1 February 2016 at 02:40, Bin Meng wrote:
> Unprotecting SPI flash is now handled in the SPI controller driver,
> via a call to the PCH driver. Drop the ad-hoc version.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/cpu/quark/quark.c | 17 -
> 1 file changed, 17 deletions(-)
Hello Vishwas,
On Mon, 1 Feb 2016 20:51:58 +0530, Vishwas Srivastava
wrote:
> Author: Vishwas Srivastava
> Date: Mon Jan 25 21:28:17 2016 +0530
This is unneeded in the commit message, as the author and date are
already provided in the mail.
> Wrong Initialization in davinci emac driver
This
On 1 February 2016 at 02:40, Bin Meng wrote:
> x86 GPIO registers are accessed via I/O port whose base address is
> configured in a PCI configuration register on the PCH device. Add
> an op get_gpio_base to get the GPIO base address from PCH.
>
> Signed-off-by: Bin Meng
> ---
>
> drivers/pch/pch
On 1 February 2016 at 02:40, Bin Meng wrote:
> Spell out 'sbase' to 'spi_base' so that it looks clearer.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/cpu/ivybridge/bd82x6x.c | 4 ++--
> drivers/pch/pch-uclass.c | 6 +++---
> drivers/pch/pch7.c | 4 ++--
> drivers/pch/pch9
On 1 February 2016 at 02:40, Bin Meng wrote:
> On some newer chipset (eg: BayTrail), there is an IO base address
> register on the PCH device which configures the base address of a
> memory-mapped I/O controller.
>
> Signed-off-by: Bin Meng
> ---
>
> drivers/pch/pch-uclass.c | 11 +++
>
On 1 February 2016 at 02:40, Bin Meng wrote:
> asm/arch/gpio.h is not needed anymore as we get the GPIO base from
> PCH driver.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/include/asm/arch-baytrail/gpio.h | 13 -
> arch/x86/include/asm/arch-coreboot/gpio.h | 13 -
>
On 1 February 2016 at 02:40, Bin Meng wrote:
> IOBASE is now obtained from PCH driver, drop this property.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/dts/minnowmax.dts | 1 -
> 1 file changed, 1 deletion(-)
Reviewed-by: Simon Glass
Tested on Minnowmax:
Tested-by: Simon Glass
On 1 February 2016 at 02:40, Bin Meng wrote:
> At present irq_router is declared as a static struct irq_router in
> arch/x86/cpu/irq.c. Since it's a driver control block, it makes sense
> to move it to a per driver priv. Adjust existing APIs to accept an
> additional parameter of irq_router's udev
On 1 February 2016 at 02:40, Bin Meng wrote:
> So far disable_igd() does not have any return value, but we may need
> that in the future.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/cpu/queensbay/tnc.c | 10 +++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
Reviewed-by: Simon Glas
On 1 February 2016 at 02:40, Bin Meng wrote:
> There is no need to parse PCH's property as we have already
> a DM PCI API dm_pci_get_bdf() that can handle this.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/cpu/irq.c | 9 +
> 1 file changed, 1 insertion(+), 8 deletions(-)
Reviewed-by:
On 1 February 2016 at 02:40, Bin Meng wrote:
> Drop legacy PCI APIs usage in pci_assign_irqs() as well.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/cpu/pci.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Simon Glass
Tested on Minnowmax:
Tested-by: Simon Glass
_
Hi Bin,
On 1 February 2016 at 02:40, Bin Meng wrote:
> With recent DM PCI changes to vesa_fb driver, external graphics
> card does not work any more. This is because: after setting the
> function disable bit, IGD and SDVO devices will disappear in the
> PCI configuration space. This however creat
On 1 February 2016 at 02:40, Bin Meng wrote:
> Now that we have irq router's udevice passed as a parameter, it's
> time to start using the DM PCI API instead of those legacy ones.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/cpu/irq.c | 6 +++---
> arch/x86/cpu/queensbay/irq.c | 2 +-
On 1 February 2016 at 02:40, Bin Meng wrote:
> Now that we have converted all x86 codes to use DM PCI APIs,
> drop those legacy ones.
>
> Signed-off-by: Bin Meng
>
> ---
>
> arch/x86/cpu/pci.c | 53
> --
> arch/x86/include/asm/pci.h | 12 -
+Marek
Hi Stefan,
On 1 February 2016 at 06:27, Stefan Roese wrote:
> Hi!
>
> I'm currently porting the Marvell mvpp2 driver for the Armada 375
> to U-Boot. This controller is a bit different, as it exposes
> multiple interfaces per controller. In this specific case its
> 2 interfaces. Here the c
Hi Michal,
On 1 February 2016 at 05:37, Michal Simek wrote:
> Hi Simon,
>
> On 31.1.2016 17:16, Simon Glass wrote:
>> Hi Michal,
>>
>> I notice that the only user of this driver appears to be a board you
>> maintain. Do you think you could convert this to driver model? Please
>> see doc/driver-mo
From: Fabio Estevam
As mx6slevk has only one Ethernet port, we don't need
to declare CONFIG_ETHPRIME, so just remove it.
Signed-off-by: Fabio Estevam
---
include/configs/mx6slevk.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index
On 1 February 2016 at 02:40, Bin Meng wrote:
> At present this GPIO driver still uses the legacy PCI API. Now that
> we have proper PCH drivers we can use those to obtain the information
> we need. While the device tree has nodes for the GPIO peripheral it is
> not in the right place. It should be
On 1 February 2016 at 02:40, Bin Meng wrote:
> Once we get udevice of IGD and SDVO, we can use its udevice to
> access PCI configuration space with dm_pci_write_config32().
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/cpu/queensbay/tnc.c | 22 +++---
> 1 file changed, 19 insert
On 1 February 2016 at 02:40, Bin Meng wrote:
> Use pci_[read|write]_config intead of x86_pci_[read|write]_config.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/cpu/qemu/qemu.c | 34 +-
> 1 file changed, 17 insertions(+), 17 deletions(-)
Reviewed-by: Simon Glass
On 1 February 2016 at 02:40, Bin Meng wrote:
> IO_BASE is only seen on PCH9 device, implement the get_io_base op.
>
> Signed-off-by: Bin Meng
> ---
>
> drivers/pch/pch9.c | 17 +
> 1 file changed, 17 insertions(+)
Reviewed-by: Simon Glass
Tested on Minnowmax:
Tested-by: Simon G
On 1 February 2016 at 02:40, Bin Meng wrote:
> Implement get_gpio_base op for bd82x6x, pch7 and pch9 drivers.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/cpu/ivybridge/bd82x6x.c | 33 +
> drivers/pch/pch7.c | 33 +
>
On 01/14/2016 04:42 AM, Ashish Kumar wrote:
> * Increase default hugepage count to 256 from 16
> * Note: default env variables are stored at 0x58020/0x58420
> of size 0x2000
>
Ashish,
What does the default env location have anything to do with this patch?
York
> Signed-off-by:
Hi Simon,
On Sat, Jan 30, 2016 at 4:45 PM, Simon Glass wrote:
> This fixes the following error when building microblaze-generic:
>
> net/eth-uclass.c: In function 'eth_post_probe':
> net/eth-uclass.c:466:18: error: 'gd' undeclared (first use in this function)
> ops->start += gd->reloc_off;
>
On Sun, Jan 31, 2016 at 09:40:04PM +0100, Albert ARIBAUD wrote:
> Hello Tom,
>
> The following changes since commit 8cdae1dacde7dbe74d53a8ac1a05761a53c4f191:
>
> video: Correct 'tor' typo in comment (2016-01-30 10:58:47 +0100)
>
> are available in the git repository at:
>
> git://git.denx.
On Sat, Jan 30, 2016 at 03:45:17PM -0700, Simon Glass wrote:
> Close the file earlier to hopefully fix a Coverity error.
>
> Reported-by: Coverity (CID: 134901)
>
> Signed-off-by: Simon Glass
Reviewed-by: Tom Rini
--
Tom
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On Sat, Jan 30, 2016 at 03:45:15PM -0700, Simon Glass wrote:
> All paths should share the same return.
>
> Reported-by: Coverity (CID:134903)
>
> Signed-off-by: Simon Glass
Reviewed-by: Tom Rini
--
Tom
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On Sat, Jan 30, 2016 at 03:45:18PM -0700, Simon Glass wrote:
> Use __maybe_unused which should avoid the Coverity error.
>
> Reported-by: Coverity (CID: 134900)
>
> Signed-off-by: Simon Glass
Reviewed-by: Tom Rini
--
Tom
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On Sat, Jan 30, 2016 at 03:45:16PM -0700, Simon Glass wrote:
> Using short doesn't save anything and is confusing when the width and height
> variables are ulong.
>
> This may fix Coverity CID134902 but I doubt it.
It won't, that CID wants height to be sanity checked as it comes from an
external
On Sat, Jan 30, 2016 at 03:45:19PM -0700, Simon Glass wrote:
> The option was renamed to CONFIG_CONSOLE_ROTATION and Rockchip boards
> were not updated. However this option is is not needed by default for
> Rockchip since we don't need a rotated console for current boards. So just
> remove the old
+Alison to comment on my question at the end of this email
Aneesh,
A few comments to this patch.
First, please prefix the subject with a meaningful tag. In this case, it should
be armv7: ls1020a.
On 01/17/2016 10:16 PM, Aneesh Bansal wrote:
> To enable snooping on CAAM transactions following pr
On 01/25/2016 09:40 PM, Qianyu Gong wrote:
>
>> -Original Message-
>> From: Scott Wood [mailto:o...@buserror.net]
>> Sent: Tuesday, January 26, 2016 1:17 AM
>> To: Qianyu Gong ; u-boot@lists.denx.de
>> Cc: b07...@freescale.com; Shaohui Xie
>> Subject: Re: [U-Boot] [Patch V3 2/3] fm: fdt:
I agree with York. Keep the name as is-- ls2080a. We already went
through the name change from ls2085a to ls2080a last year in Linux and
in u-boot and there is no reason to go back. The fact that the RDB
boards have the wrong name printed on them is not enough reason to
revert what we already
On 01/31/2016 06:19 AM, Bin Meng wrote:
> Hi York,
>
> On Sun, Jan 31, 2016 at 6:03 AM, York Sun wrote:
>> This reverts commit 168dcc6cef7a0e13bc52fc8fa8de2866cf4033dc.
>> Align with changes since P2020DS was removed, including adding
>> these macros to defconfig
>>
>> CONFIG_SYS_NS16550
>> CONFI
On Saturday, January 16, 2016 at 07:13:47 PM, Wills Wang wrote:
> Signed-off-by: Wills Wang
> ---
[...]
> diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
> new file mode 100644
> index 000..df84876
> --- /dev/null
> +++ b/arch/mips/mach-ath79/Kconfig
> @@ -0,0 +1,10
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