On 03/15/2016 11:40 PM, Marek Vasut wrote:
> On 03/15/2016 01:44 PM, Purna Chandra Mandal wrote:
>> Moved definition of writes{bwlq} and reads{bwlq} into arch.
>> There is no need of having arch specific wrapper in driver.
> And so the patch does ... what exactly ? I cannot figure it out just by
>
Hi Bin,
On 16.03.2016 03:18, Bin Meng wrote:
On Wed, Mar 16, 2016 at 12:14 AM, Stefan Roese wrote:
This patch adds support for the congatec conga-QA3/E3845-4G eMMC8 SoM,
installed on the congatec Qseven 2.0 evaluation carrier board
(conga-QEVAL).
Its port is very similar to the MinnowboardMAX
The initial training for the DDRC may provide results that are not
optimized. The workaround provides better read timing margins.
Signed-off-by: Shengzhou Liu
---
arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
drivers/ddr/fsl/fsl_ddr_gen4.c| 7 +++
include/fsl_d
Per the latest erratum document, update step 4 and step 8, only
DEBUG_29[21] is changed, all other bits should not be changed.
Signed-off-by: Shengzhou Liu
---
drivers/ddr/fsl/fsl_ddr_gen4.c | 10 +++---
include/fsl_ddr_sdram.h| 3 +++
2 files changed, 10 insertions(+), 3 deletions(
Barrier transactions from CCI400 need to be disabled till
the DDR is configured, otherwise it may lead to system hang.
The patch adds workaround to fix the erratum.
Signed-off-by: Shengzhou Liu
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 18 ++
arch/arm/include/asm/ar
On Wednesday 16 March 2016 04:39 AM, Nishanth Menon wrote:
> Hi,
> The following series adds support for DRA72x SoC and enables support
> for TI DRA72-evm rev C.
>
> Rev C evm has a few changes w.r.t. rev A/B (SR1.0 based SoC),
> including newer DDR, newer ethernet PHY(2 ports enabled), very few
> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Tuesday, March 15, 2016 7:18 PM
> To: Qianyu Gong ; Huan Wang
> Cc: york sun ; Tom Rini ; Siva Durga
> Prasad Paladugu ; Michal Simek ;
> u-boot@lists.denx.de; Stefan Roese ; Mingkai Hu
>
> Subject: Re: [U-
On 14 March 2016 at 23:48, Peng Fan wrote:
> To i.MX controller, we use such as "<&gpio1 3 GPIO_ACTIVE_LOW>" for
> a device to refer a gpio pin in device tree. So need to implement
> xlate function, to correctly handle gpio flags and offset.
>
> Signed-off-by: Peng Fan
> Cc: Simon Glass
> Cc: St
On 15 March 2016 at 11:20, Tom Rini wrote:
> good enough.
> - Make include like other arches do
> - Enable many many more drivers in sandbox_defconfig so that we can get
> more build-time testing on this platform.
>
> Cc: Simon Glass
> Signed-off-by: Tom Rini
> ---
> arch/sandbox/include/
Hi Stefan,
On 15 March 2016 at 13:53, Marek Vasut wrote:
> On 03/15/2016 01:59 PM, Stefan Roese wrote:
>> My current x86 platform (Bay Trail, not in mainline yet) has a quite
>> complex USB infrastructure with many USB hubs. Here the USB scan takes
>> an incredible huge amount of time:
>>
>> star
Hi Tom,
2016-03-16 4:23 GMT+09:00 Tom Rini :
> On Mon, Feb 29, 2016 at 08:31:57PM +0900, Masahiro Yamada wrote:
>
>> The function spl_parse_image_header() falls back to a raw image
>> if the U-Boot header is missing and CONFIG_SPL_PANIC_ON_RAW_IMAGE
>> is undefined. While, the bad magic checking
The function spl_parse_image_header() falls back to a raw image
if the U-Boot header is missing and CONFIG_SPL_PANIC_ON_RAW_IMAGE
is undefined. While, mmc_load_image_raw_sector() only accepts a
U-Boot legacy image or an FIT image, preventing us from loading a
raw image.
Signed-off-by: Masahiro Ya
On 03/15/2016 01:59 PM, Stefan Roese wrote:
> My current x86 platform (Bay Trail, not in mainline yet) has a quite
> complex USB infrastructure with many USB hubs. Here the USB scan takes
> an incredible huge amount of time:
>
> starting USB...
> USB0: USB EHCI 1.00
> scanning bus 0 for devices.
On 03/13/2016 07:16 PM, Eric Anholt wrote:
For Raspberry Pi, we had the input clock rate to the pl011 fixed in
the rpi.c file, but it may be changed by firmware due to user changes
to config.txt. Since the firmware always sets up the uart (default
115200 output unless the user changes it), we ca
Hi Stefan,
On Tue, Mar 15, 2016 at 8:59 PM, Stefan Roese wrote:
>
> My current x86 platform (Bay Trail, not in mainline yet) has a quite
> complex USB infrastructure with many USB hubs. Here the USB scan takes
> an incredible huge amount of time:
>
> starting USB...
> USB0: USB EHCI 1.00
> scan
On Tue, Mar 15, 2016 at 8:59 PM, Stefan Roese wrote:
> Debugging has shown, that all USB hubs are being reset twice while
> USB scanning. This introduces additional delays and makes USB scanning
> even more slow. Testing has shown that this 2nd USB hub reset doesn't
> seem to be necessary.
>
> Thi
On Tue, Mar 15, 2016 at 8:59 PM, Stefan Roese wrote:
> This patch changes the USB port scanning procedure and timeout
> handling in the following ways:
>
> a)
> The power-on delay in usb_hub_power_on() is now reduced to a value of
> max(100ms, "hub->desc.bPwrOn2PwrGood * 2"). The code does not wai
On Tue, Mar 15, 2016 at 8:59 PM, Stefan Roese wrote:
> This patch removes 2 mdelay(200) calls from usb_hub_port_connect_change().
> These delays don't seem to be necessary. At least not in my tests. Here
> the number for a custom x86 Bay Trail board (not in mainline yet) with
> a quite large and c
On Tue, Mar 15, 2016 at 8:59 PM, Stefan Roese wrote:
> Start with a short USB hub reset delay of 20ms. This can be enough for
> some configurations.
>
> The 2nd delay at the end of the loop is completely removed. Since the
> delay hasn't been long enough, a longer delay time of 200ms is assigned
>
Hi Stefan,
On Wed, Mar 16, 2016 at 12:14 AM, Stefan Roese wrote:
> This patch adds support for the congatec conga-QA3/E3845-4G eMMC8 SoM,
> installed on the congatec Qseven 2.0 evaluation carrier board
> (conga-QEVAL).
>
> Its port is very similar to the MinnowboardMAX port and also uses
> the In
If vmmc-supply property is provided, then enable it.
If vmmc-supply is not provided, just ignore it.
For now, only fixed regulator is supported.
In device tree:
"
reg_sd1_vmmc: regulator@1 {
compatible = "regulator-fixed";
regulator-n
In device tree, there is vmmc-supply property for SD/MMC.
Introduce mmc_power_init function and pwrup hook function to let
the specific drivers handle vmmc-supply.
mmc_power_init will first invoke board_mmc_power_init to
avoid break boards which already implement board_mmc_power_init.
Then if pwr
Hi Fabio,
On Tue, Mar 15, 2016 at 09:53:15AM -0300, Fabio Estevam wrote:
>On Tue, Mar 15, 2016 at 2:48 AM, Peng Fan wrote:
>> When configured a gpio to output direction, directly reading PSR register
>> can not return the output value, since we did not set SION bit for gpio
>> iomux. So, we can u
On 9 March 2016 at 08:06, George Broz wrote:
> On 9 March 2016 at 02:55, Marek Vasut wrote:
>> On 03/09/2016 02:42 AM, Phil Reid wrote:
>>> G'day George,
>>>
>>> On 3/03/2016 10:57 PM, George Broz wrote:
On 2 March 2016 at 23:11, Phil Reid wrote:
> On 3/03/2016 2:49 PM, George Broz wrot
On 16.3.2016 02:05, Tom Rini wrote:
> Starting with 96e5b03 we use a linker list for partition table
> information. However since we use this in SPL we need to make sure that
> the SPL linker scripts include these as well. While doing this, it's
> best to simply include all linker lists to future
On Tue, Mar 15, 2016 at 09:05:55PM -0400, Tom Rini wrote:
> Starting with 96e5b03 we use a linker list for partition table
> information. However since we use this in SPL we need to make sure that
> the SPL linker scripts include these as well. While doing this, it's
> best to simply include all
Starting with 96e5b03 we use a linker list for partition table
information. However since we use this in SPL we need to make sure that
the SPL linker scripts include these as well. While doing this, it's
best to simply include all linker lists to future proof ourselves.
Cc: Andreas Bießmann
Cc:
On 16.3.2016 01:50, Tom Rini wrote:
> On Wed, Mar 16, 2016 at 01:25:14AM +0100, Michal Simek wrote:
>> On 15.3.2016 23:29, Tom Rini wrote:
>>> Starting with 96e5b03 we use a linker list for partition table
>>> information. However since we use this in SPL we need to make sure that
>>> the SPL link
On Wed, Mar 16, 2016 at 01:25:14AM +0100, Michal Simek wrote:
> On 15.3.2016 23:29, Tom Rini wrote:
> > Starting with 96e5b03 we use a linker list for partition table
> > information. However since we use this in SPL we need to make sure that
> > the SPL linker scripts include these as well.
> >
On 15.3.2016 23:29, Tom Rini wrote:
> Starting with 96e5b03 we use a linker list for partition table
> information. However since we use this in SPL we need to make sure that
> the SPL linker scripts include these as well.
>
> Cc: Michal Simek
> Reviewed-by: Simon Glass
> Reported-by: Nishanth
Hi,
The following series adds support for DRA72x SoC and enables support
for TI DRA72-evm rev C.
Rev C evm has a few changes w.r.t. rev A/B (SR1.0 based SoC),
including newer DDR, newer ethernet PHY(2 ports enabled), very few pin
mux changes, etc.
Ethernet support is a follow on series that shoul
Since many platforms may need different pad configuration required
depending on variation of the platform with minor deltas, it is
easier to maintain a sub step based approach to allow for pin mux
and iodelay configuration which may depend on the platform variations
and need to be done in IO isolat
Add the pinmux data for rev C evm. This is different from previous
revisions of the platform thanks to the deltas introduced both from
silicon side and from SoC side.
Based on J6EcoES2_EVM_Base_Config-20160309b and PCT-DRA72x-v1.3.0.7 for
SR2.0 silicon.
Signed-off-by: Nishanth Menon
---
board/t
Based on data from EMIF configuration tool 1.1.1.
Signed-off-by: Nishanth Menon
---
arch/arm/cpu/armv7/omap5/sdram.c | 44 +-
1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
in
do_set_iodelay can now be used from board files based on needs of the
platforms variation they have.
Signed-off-by: Nishanth Menon
---
arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c|4 ++--
arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h |2 ++
2 files changed, 4 insertions(+), 2 del
From: Ravi Babu
Add support for detection of SR2.0 version of DRA72x family of
processors.
Signed-off-by: Ravi Babu
Signed-off-by: Nishanth Menon
---
arch/arm/cpu/armv7/omap5/hw_data.c |2 ++
arch/arm/cpu/armv7/omap5/hwinit.c |3 +++
arch/arm/cpu/armv7/omap5/sdram.c |
From: Ravi Babu
DDR configuration has changes from SR1.1 based Rev-A/B version of evm
to the SR2.0 based Rev C of the EVM. Rev C evm now uses the higher
density MT41K512M8RH-125-AAT:E (IT) which is of size 2GB.
Update the DDR configuration based on data from EMIF configuration
tool 1.1.1. NOTE:
Based on data from EMIF configuration tool 1.1.1. Expected update for
CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT in the next revision of the tool has
been incorporated as well.
Signed-off-by: Nishanth Menon
---
arch/arm/cpu/armv7/omap5/hw_data.c | 16 +++-
1 file changed, 15 insertions(+), 1
Starting with 96e5b03 we use a linker list for partition table
information. However since we use this in SPL we need to make sure that
the SPL linker scripts include these as well.
Cc: Michal Simek
Reviewed-by: Simon Glass
Reported-by: Nishanth Menon
Tested-by: Nishanth Menon
Signed-off-by: T
On 15.3.2016 22:58, Tom Rini wrote:
> Starting with 96e5b03 we use a linker list for partition table
> information. However since we use this in SPL we need to make sure that
> the SPL linker scripts include these as well.
>
> Cc: Nishanth Menon
> Cc: Michal Simek
> Cc: Simon Glass
> Reported-
On 03/15/2016 04:58 PM, Tom Rini wrote:
> Starting with 96e5b03 we use a linker list for partition table
> information. However since we use this in SPL we need to make sure that
> the SPL linker scripts include these as well.
>
> Cc: Nishanth Menon
> Cc: Michal Simek
> Cc: Simon Glass
> Repor
On 15 March 2016 at 15:58, Tom Rini wrote:
>
> Starting with 96e5b03 we use a linker list for partition table
> information. However since we use this in SPL we need to make sure that
> the SPL linker scripts include these as well.
>
> Cc: Nishanth Menon
> Cc: Michal Simek
> Cc: Simon Glass
>
Starting with 96e5b03 we use a linker list for partition table
information. However since we use this in SPL we need to make sure that
the SPL linker scripts include these as well.
Cc: Nishanth Menon
Cc: Michal Simek
Cc: Simon Glass
Reported-by: Nishanth Menon
Signed-off-by: Tom Rini
---
ar
On Thu, Dec 10, 2015 at 10:46 PM, Tom Rini wrote:
> Based on the am335x_evm conversion, switch to config_distro_bootcmd for
> mmc and pxe. Tested with Fedora 23.
>
> Signed-off-by: Tom Rini
> ---
> include/configs/ti_omap4_common.h | 51
> -
> 1 file chang
Fixes the following warning with PART_DEBUG enabled:
disk/part.c: In function ‘get_partition_info’:
disk/part.c:372:3: warning: format ‘%s’ expects a matching ‘char *’ argument
[-Wformat]
Signed-off-by: Nishanth Menon
---
disk/part.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
d
On Tue, Mar 15, 2016 at 07:09:14PM +0100, Karsten Merker wrote:
> On Tue, Mar 15, 2016 at 06:41:39AM +0100, Michael Haas wrote:
>
> > This change is required to get GBIT Ethernet to work
> > reliably on my board. Without CONFIG_GMAC_TX_DELAY=4, the connection
> > suffers severe packet loss and SSH
On Tue, Mar 15, 2016 at 12:11:13PM -0700, Vagrant Cascadian wrote:
> Signed-off-by: Vagrant Cascadian
Reviewed-by: Tom Rini
--
Tom
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On Tue, Mar 15, 2016 at 12:11:12PM -0700, Vagrant Cascadian wrote:
> Signed-off-by: Vagrant Cascadian
Reviewed-by: Tom Rini
--
Tom
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On Tue, Mar 15, 2016 at 12:16:39PM -0700, Vagrant Cascadian wrote:
> Signed-off-by: Vagrant Cascadian
Reviewed-by: Tom Rini
--
Tom
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On 15 March 2016 at 13:11, Vagrant Cascadian wrote:
> Signed-off-by: Vagrant Cascadian
> ---
>
> board/hisilicon/hikey/hikey.c | 2 +-
> fs/fat/fat_write.c| 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Simon Glass
___
On 15 March 2016 at 13:19, Marek Vasut wrote:
>
> On 03/15/2016 08:16 PM, Vagrant Cascadian wrote:
> > Signed-off-by: Vagrant Cascadian
> > ---
>
> This patch increase the size of U-Boot binary by a few bytes on systems
> with floppy disk controllers ;-)
>
> Of course,
> Acked-by: Marek Vasut
R
On 03/15/2016 01:44 PM, Purna Chandra Mandal wrote:
> This driver adds support of PIC32 MUSB OTG controller as dual role device.
> It implements platform specific glue to reuse musb core.
>
> Signed-off-by: Cristian Birsan
> Signed-off-by: Purna Chandra Mandal
[...]
> diff --git a/drivers/usb/
On 03/15/2016 07:21 PM, Jagan Teki wrote:
> On Tuesday 15 March 2016 11:42 PM, Cyrille Pitchen wrote:
>> Hi all,
>>
>> This series of patches fixes and extend the support of QSPI memories
>> in the SPI flash framework. The updates are split into many parts to
>> make it easier to understand and rev
On 03/15/2016 01:44 PM, Purna Chandra Mandal wrote:
> Moved definition of writes{bwlq} and reads{bwlq} into arch.
> There is no need of having arch specific wrapper in driver.
And so the patch does ... what exactly ? I cannot figure it out just by
reading the commit message, sorry.
The patch itse
On 03/15/2016 08:16 PM, Vagrant Cascadian wrote:
> Signed-off-by: Vagrant Cascadian
> ---
This patch increase the size of U-Boot binary by a few bytes on systems
with floppy disk controllers ;-)
Of course,
Acked-by: Marek Vasut
--
Best regards,
Marek Vasut
On Mon, Feb 29, 2016 at 08:31:57PM +0900, Masahiro Yamada wrote:
> The function spl_parse_image_header() falls back to a raw image
> if the U-Boot header is missing and CONFIG_SPL_PANIC_ON_RAW_IMAGE
> is undefined. While, the bad magic checking here makes the
> spl_parse_image_header() unreachabl
Signed-off-by: Vagrant Cascadian
---
arch/powerpc/cpu/mpc8xx/spi.c| 2 +-
arch/sparc/cpu/leon3/usb_uhci.c | 8
board/mpl/common/usb_uhci.c | 8
cmd/fdc.c| 2 +-
common/usb.c | 2 +-
co
Signed-off-by: Vagrant Cascadian
---
board/hisilicon/hikey/hikey.c | 2 +-
fs/fat/fat_write.c| 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c
index c4ae40b..cf9c77d 100644
--- a/board/hisilicon/hikey/
Vagrant Cascadian (2):
Fix spelling of "comment".
Fix spelling of "supported/unsupported".
board/hisilicon/hikey/hikey.c | 2 +-
fs/fat/fat_write.c| 2 +-
tools/env/fw_env_main.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
--
2.1.4
Signed-off-by: Vagrant Cascadian
---
tools/env/fw_env_main.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/env/fw_env_main.c b/tools/env/fw_env_main.c
index 4bd4216..3bec5b9 100644
--- a/tools/env/fw_env_main.c
+++ b/tools/env/fw_env_main.c
@@ -93,7 +93,7 @@ void usag
On Tue, Mar 15, 2016 at 11:56:33PM +0530, Jagan Teki wrote:
> Global definition of priv seems no-sense to use it
> for non-dm case and pass the pointer to functions
> which are common to both dm and non-dm.
>
> So, fix this by removing omap3_spi_slave from non-dm
> and make visible to omap3_spi_p
On 15 March 2016 at 23:56, Jagan Teki wrote:
> Global definition of priv seems no-sense to use it
> for non-dm case and pass the pointer to functions
> which are common to both dm and non-dm.
>
> So, fix this by removing omap3_spi_slave from non-dm
> and make visible to omap3_spi_priv for both dm
Global definition of priv seems no-sense to use it
for non-dm case and pass the pointer to functions
which are common to both dm and non-dm.
So, fix this by removing omap3_spi_slave from non-dm
and make visible to omap3_spi_priv for both dm and non-dm.
Cc: Christophe Ricard
Reported-by: Tom Rini
Setup the LCD backlight brightness control pin to use PWM
Signed-off-by: Akshay Bhat
Cc: Stefano Babic
---
board/ge/bx50v3/bx50v3.c| 11 +++
include/configs/ge_bx50v3.h | 3 +++
2 files changed, 14 insertions(+)
diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
inde
On Tuesday 15 March 2016 11:42 PM, Cyrille Pitchen wrote:
Hi all,
This series of patches fixes and extend the support of QSPI memories
in the SPI flash framework. The updates are split into many parts to
make it easier to understand and review but they should be considered
as a whole.
This was
There is no need to claim/release the SPI bus for each command sent to the
memory when performing read, write or erase operations. Now we claim the
SPI bus once for all at the very beginning of these operations then we
release it just before exiting.
Signed-off-by: Cyrille Pitchen
---
drivers/mt
This patch makes the support of SST flashes available to all
UCLASS_SPI_FLASH drivers, not only the sf_probe.c one.
Signed-off-by: Cyrille Pitchen
---
drivers/mtd/spi/sf_internal.h | 8 ++---
drivers/mtd/spi/sf_probe.c| 9 -
drivers/mtd/spi/spi_flash.c | 76 +++---
This patch splits the generic algorithm to read data from the
actual implementation which is specific to each UCLASS_SPI_FLASH driver.
For now, the sf_probe.c driver is the only instance of this driver class
using this generic algorithm but other driver instances are to come.
This patch will ease
Since spi_claim_bus() and spi_release_bus() are now called outside
spi_flash_read_common(), this latest function is just a useless alias for
spi_flash_cmd_read(). So we remove it.
Signed-off-by: Cyrille Pitchen
---
drivers/mtd/spi/sf_internal.h | 6 --
drivers/mtd/spi/spi_flash.c | 30 +++
It looks odd to compute a logical AND between the e_rd_cmd field of
struct spi_flash_params and the mode_rx field of struct spi_slave.
Indeed, these two fields don't use the same range of values.
mode_rx is limited to SPI_RX_{SLOW, FAST, DUAL, QUAD}. Even completed
with the SPI_TX_{DUAL, QUAD} fla
This reverts commit c56ae7519f141523ba1248b22b5b5169b21772fe.
Once the 'Quad Enable' bit is cleared in their Enhanced Volatile
Configuration Register (EVCR), Micron memories expect ALL commands to use
the SPI 4-4-4 protocol. Commands using SPI 1-y-z protocols are no longer
accepted.
Within the re
This patch prepares the split of memory versus internal registers SPI
commands.
Signed-off-by: Cyrille Pitchen
---
drivers/mtd/spi/sf_internal.h | 8 +++---
drivers/mtd/spi/spi_flash.c | 62 ++-
2 files changed, 42 insertions(+), 28 deletions(-)
diff -
This patch exports a new function so future drivers can use it.
Signed-off-by: Cyrille Pitchen
---
drivers/mtd/spi/sf_internal.h | 3 +++
drivers/mtd/spi/spi_flash.c | 7 ++-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_in
This patch splits the generic algorithm to write data from the
actual implementation which is specific to each UCLASS_SPI_FLASH driver.
For now, the sf_probe.c driver is the only instance of this driver class
using this generic algorithm but other driver instances are to come.
This patch will ease
Hi all,
This series of patches fixes and extend the support of QSPI memories
in the SPI flash framework. The updates are split into many parts to
make it easier to understand and review but they should be considered
as a whole.
This was tested on a Atmel sama5d2 xplained board with a Micron n25q1
This patch splits the generic algorithm to erase pages/sectors from the
actual implementation which is specific to each UCLASS_SPI_FLASH driver.
For now, the sf_probe.c driver is the only instance of this driver class
using this generic algorithm but other driver instances are to come.
This patch
This patch provides support of Micron QSPI memories.
Signed-off-by: Cyrille Pitchen
---
drivers/mtd/spi/Makefile | 1 +
drivers/mtd/spi/sf_internal.h | 24 +
drivers/mtd/spi/sf_micron.c | 222 ++
drivers/mtd/spi/spi_flash.c | 13 +--
4 fil
This is just a transitional patch to add manufacturer dedicated support
for QSPI memories.
Indeed, using Quad SPI protocols is slighty more complicated than simply
enabling the Quad I/O or QPI mode. We should also take care about the
number of dummy cycles. For instance, some Spansion QSPI memorie
This patch adds a helper function to ease the conversion between a number
of dummy clock cycles and number of bytes.
Actually this number of bytes depends on both the number of dummy clock
cycles and SPI protocol used by (Fast) Read commands.
This new function is exported so it can be used by oth
This patch provides an alternative to support memory >16MiB (>128Mib).
Indeed using the Base Address Register changes the internal state of
the SPI flash memory. However some early boot loaders expect to access
the first memory bank of the SPI flash. Then when another bank has been
selected, those
The quad (or dual) mode of a SPI flash memory may be enabled at boot time
by non-volatile bits in some setting register. Also such a mode may have
already been enabled at early stage by some boot loader.
Hence, we should not guess the SPI flash memory is always configured for
the regular SPI 1-1-1
This patch finalizes the split of internal register and memory data SPI
commands. Indeed some (Q)SPI controllers such as the Atmel QSPI controller
need to make the difference between register read/write SPI commands and
data read/write/erase SPI commands.
It follows an interface close to the one u
This patch adds support of the Atmel QSPI controller.
Signed-off-by: Cyrille Pitchen
---
drivers/mtd/spi/Makefile | 1 +
drivers/mtd/spi/atmel_qspi_flash.c | 432 +
drivers/spi/Kconfig| 9 +
drivers/spi/Makefile |
From: Marcus Cooper
Add dts and defconfig for the multi board device based on the
Allwinner A20 SoC. It contains the A20 Itead Core module and a
base board for the external interfaces.
The core module comes with 4GB NAND and 1GB DDR RAM. As this is
a generic design which has also been used on a
Add the new get_qpsi_clk_rate() function which will be needed by the
future Atmel QSPI controller driver.
Signed-off-by: Cyrille Pitchen
---
arch/arm/mach-at91/include/mach/clk.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-at91/include/mach/clk.h
b/arch/arm/mach-at91/
On 15 March 2016 at 18:34, wrote:
> From: Marcus Cooper
>
> This patch delivers the uboot changes required for the Itead Ibox A20. As
> there
> are a few Itead variants out there based on their A10/A20 core module; I have
> created a common dtsi for all of them.
>
> I've also converted the A10
From: Marcus Cooper
This patch delivers the uboot changes required for the Itead Ibox A20. As there
are a few Itead variants out there based on their A10/A20 core module; I have
created a common dtsi for all of them.
I've also converted the A10 Itead Iteaduino dts to use this common file.
BR,
CK
From: Marcus Cooper
The delivery of the Itead Ibox A20 contained a common include
dtsi file for the core module which this Itead Iteadunio Plus
uses.
This patch modifies the dts to use this include dtsi.
Signed-off-by: Marcus Cooper
---
arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts | 86 +---
Implements the below changes:
- Disable LVDS1 on B450v3/B650v3 boards since the final boards no longer
have connectors for the same. Only LVDS0 hardware connectors are present.
- Implement imx6 EB821 or ERR009219 errata for LVDS clock switch.
This patch was ported from Freescale 3.10.17_1.0.0_ga ke
On 15 March 2016 at 22:05, Stefan Roese wrote:
> This enables this driver for the Marvell Armada 375 SoC.
>
> Signed-off-by: Stefan Roese
> Cc: Luka Perkov
> Cc: Jagan Teki
Reviewed-by: Jagan Teki
--
Jagan.
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On 15 March 2016 at 20:34, Tom Rini wrote:
> On Tue, Mar 15, 2016 at 08:01:14AM -0400, Tom Rini wrote:
>> On Tue, Mar 15, 2016 at 12:41:20PM +0530, Jagan Teki wrote:
>>
>> > Hi Tom,
>> >
>> > Please pull this PR.
>> >
>> > thanks!
>> > Jagan.
>> >
>> > The following changes since commit
>> > df61
The EFI standard defines a simple boot protocol that an EFI payload can use
to access video output.
This patch adds support to expose exactly that one (and the mode already in
use) as possible graphical configuration to an EFI payload.
With this, I can successfully run grub2 with graphical output
From: Marcus Cooper
The delivery of the Itead Ibox A20 contained a common include
dtsi file for the core module which this Itead Iteadunio Plus
uses.
This patch modifies the dts to use this include dtsi.
Signed-off-by: Marcus Cooper
---
arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts | 86 +---
From: Marcus Cooper
This patch delivers the uboot changes required for the Itead Ibox A20. As there
are a few Itead variants out there based on their A10/A20 core module; I have
created a common dtsi for all of them.
I've also converted the A10 Itead Iteaduino dts to use this common file.
BR,
CK
From: Marcus Cooper
Add dts and defconfig for the multi board device based on the
Allwinner A20 SoC. It contains the A20 Itead Core module and a
base board for the external interfaces.
The core module comes with 4GB NAND and 1GB DDR RAM. As this is
a generic design which has also been used on a
This patch adds support for the mvpp2 ethernet controller which is integrated
in the Marvell Armada 375 SoC. This port is based on the Linux driver (v4.4),
which has been stripped of the in U-Boot unused portions.
Tested on the Marvell Armada 375 eval board db-88f6720.
Signed-off-by: Stefan Roese
On Tue, Mar 15, 2016 at 06:21:45PM +0100, Alexander Graf wrote:
> Signed-off-by: Alexander Graf
> ---
> arch/arm/include/asm/system.h | 99
> ---
> arch/arm/lib/cache-cp15.c | 66 ++---
> 2 files changed, 153 insertions(+), 12
Hey all,
As some of you know, I run coverity scan builds for U-Boot periodically
and then pass errors along to folks when new changes introduce problems.
With DM work, one thing that's now possible is to build and link code
that's not going to run on a particular platform. For example, I just
po
Signed-off-by: Alexander Graf
---
arch/arm/include/asm/system.h | 99 ---
arch/arm/lib/cache-cp15.c | 66 ++---
2 files changed, 153 insertions(+), 12 deletions(-)
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/as
When compiling the code for 64bit, the lcd code emits warnings because it
tries to cast pointers to 32bit values. Fix it by casting them to longs
instead, actually properly aligning with the function prototype.
Signed-off-by: Alexander Graf
---
common/lcd.c | 4 ++--
1 file changed, 2 insertions
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