From: Siva Durga Prasad Paladugu
Correct type of varibale base to unsigned long as
keeping it as int causes usb failures if MSB of
the base address is set.
Signed-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek
---
include/dwc3-uboot.h | 2 +-
1 file changed, 1 insertion(+), 1
Am 12.05.2016 um 07:49 schrieb Prabhakar Kushwaha :
>> -Original Message-
>> From: Alexander Graf [mailto:ag...@suse.de]
>> Sent: Thursday, May 12, 2016 3:37 AM
>> To: york sun; Prabhakar Kushwaha; u-boot@lists.denx.de
>> Cc: Pratiyush Srivastava; Abhimanyu Saini
>> Subject: Re: [U-Boot]
> -Original Message-
> From: Alexander Graf [mailto:ag...@suse.de]
> Sent: Thursday, May 12, 2016 3:37 AM
> To: york sun; Prabhakar Kushwaha; u-boot@lists.denx.de
> Cc: Pratiyush Srivastava; Abhimanyu Saini
> Subject: Re: [U-Boot] [PATCH 8/9][v2] armv8: ls1012a: Add support of
> ls1012aqds
Hi Tom,
On Wednesday 11 May 2016 09:53 PM, Tom Rini wrote:
> On Tue, May 10, 2016 at 01:18:16PM +0530, Lokesh Vutla wrote:
>
>> This series adds support for FIT and various AM335x based platforms
>>
>> BBB: http://pastebin.ubuntu.com/16340189/
>> BBW: http://pastebin.ubuntu.com/16340238/
>> AM3
On Tuesday 10 May 2016 06:09 PM, Marek Vasut wrote:
> On 05/10/2016 01:48 PM, Mugunthan V N wrote:
>> Add a TI MUSB peripheral driver with driver model support and the
>> driver will be bound by the MUSB wrapper driver based on the
>> dr_mode device tree entry.
>>
>> Signed-off-by: Mugunthan V N
>
On Tuesday 10 May 2016 05:57 PM, Marek Vasut wrote:
> On 05/10/2016 01:44 PM, Mugunthan V N wrote:
>> Adopt usb ether gadget and rndis driver to adopt driver model
>>
>> Signed-off-by: Mugunthan V N
>> ---
>> drivers/usb/gadget/ether.c | 153
>> ++---
>> d
On Tuesday 10 May 2016 05:54 PM, Marek Vasut wrote:
> On 05/10/2016 01:44 PM, Mugunthan V N wrote:
>> prepare driver for driver model migration
>>
>> Signed-off-by: Mugunthan V N
>> ---
>> drivers/usb/gadget/ether.c | 72
>> --
>> 1 file changed, 51 in
Hello Kevin,
Am 11.05.2016 um 17:54 schrieb Kevin Smith:
Hi Joe and Heiko,
I tried disabling the fastmap options, and it appears to be related to
these. With fastmap off, I am able two write without corrupting the
other volume. It looks like it may specifically be the autoupdate
feature, but
Hi Marek,
2016-05-11 20:22 GMT+09:00 Marek Vasut :
>>> Because you want to have definition of every symbol you use in your
>>> headers when you include that header. I am not a big fan of huge stack
>>> of #include statements in a driver.
>>
>> Agree. That's why this patch is here.
>>
>> See thi
In a system where the initial u-boot location is genuinely NOR flash (as
opposed to RAM or a cache-line setup by a pre-bootloader) writes to the
data section are problematic. At best these writes have no effect at
worse they put the flash memory into a status mode which changes the
executable code
We have a board using Marvell's MV78100 SoC (note despite the name this
is quite different to the armada MV782x0/MV784x0 SoCs).
The SoC support isn't upstream but since it's quite similar to the
Orion/Kirkwood we've managed to keep reasonably up to date. One
difference with our system is that it b
On Wed, May 11, 2016 at 09:20:20PM +0200, Marek Vasut wrote:
> On 05/11/2016 06:23 PM, Tom Rini wrote:
> > On Sat, May 07, 2016 at 03:42:15AM +0200, Marek Vasut wrote:
> >
> >> The following changes since commit
> >> bbca7108db79076d3a9a9c112792d7c4608a665c:
> >>
> >>
> >>
> >> ARM: tegra: impo
On 11.05.16 17:59, York Sun wrote:
> On 05/11/2016 12:30 AM, Prabhakar Kushwaha wrote:
>> QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
>> development platform, with a complete debugging environment.
>> The LS1012AQDS board supports the QorIQ LS1012A processor and is
>> opti
From: Stephen Warren
This will allow a driver's bind function to use the driver data. One
example is the Tegra186 GPIO driver, which instantiates child devices
for each of its GPIO ports, yet supports two different HW instances each
with a different set of ports, and identified by the udevice_id
From: Stephen Warren
Now that the DM core sets driver_data before calling bind(), this driver
can make use of driver_data to determine the set of child devices to
create, rather than manually re-implementing the matching logic in code.
Cc: Hans de Goede
Signed-off-by: Stephen Warren
---
v2: Ne
On 05/11/2016 06:23 PM, Tom Rini wrote:
> On Sat, May 07, 2016 at 03:42:15AM +0200, Marek Vasut wrote:
>
>> The following changes since commit
>> bbca7108db79076d3a9a9c112792d7c4608a665c:
>>
>>
>>
>> ARM: tegra: import latest Jetson TK1 spreadsheet (2016-05-04 13:31:04
>> -0700)
>>
>>
>> are ava
Hi Stephen,
On 11 May 2016 at 12:45, Stephen Warren wrote:
> Simon,
>
> For Tegra186 support, I'd like to introduce a reset subsystem into U-Boot,
> to support the reset DT bindings[1]. It'd be equivalent to the existing
> reset subsystem in Linux. This binding/subsystem does/would control reset
Hi Stephen,
On 11 May 2016 at 10:52, Stephen Warren wrote:
> On 05/10/2016 08:25 PM, Simon Glass wrote:
>>
>> Hi Stephen,
>>
>> On 4 May 2016 at 12:42, Stephen Warren wrote:
>>>
>>> On 05/01/2016 01:27 PM, Simon Glass wrote:
Hi Stephen,
On 28 April 2016 at 17:08, Stephen
Simon,
For Tegra186 support, I'd like to introduce a reset subsystem into
U-Boot, to support the reset DT bindings[1]. It'd be equivalent to the
existing reset subsystem in Linux. This binding/subsystem does/would
control reset of e.g. individual HW blocks in an SoC, or individual
chips on th
> Am 11.05.2016 um 19:09 schrieb York Sun :
>
>> On 05/11/2016 10:04 AM, Alexander Graf wrote:
>>
>>
Am 11.05.2016 um 18:33 schrieb York Sun :
On 05/11/2016 09:25 AM, Alexander Graf wrote:
While testing our shiny new EFI support, I stumbled across systems that
have di
On 05/11/2016 10:04 AM, Alexander Graf wrote:
>
>
>> Am 11.05.2016 um 18:33 schrieb York Sun :
>>
>>> On 05/11/2016 09:25 AM, Alexander Graf wrote:
>>> While testing our shiny new EFI support, I stumbled across systems that
>>> have disk I/O hardware that can only access the lower 32bits of our
>
> Am 11.05.2016 um 18:33 schrieb York Sun :
>
>> On 05/11/2016 09:25 AM, Alexander Graf wrote:
>> While testing our shiny new EFI support, I stumbled across systems that
>> have disk I/O hardware that can only access the lower 32bits of our
>> physical address space.
>>
>> This is not a problem
On 05/10/2016 08:25 PM, Simon Glass wrote:
Hi Stephen,
On 4 May 2016 at 12:42, Stephen Warren wrote:
On 05/01/2016 01:27 PM, Simon Glass wrote:
Hi Stephen,
On 28 April 2016 at 17:08, Stephen Warren wrote:
From: Stephen Warren
This will allow a driver's bind function to use the driver d
On 05/11/2016 09:25 AM, Alexander Graf wrote:
> While testing our shiny new EFI support, I stumbled across systems that
> have disk I/O hardware that can only access the lower 32bits of our
> physical address space.
>
> This is not a problem when running with the normal U-Boot flow, since we
> def
We know for certain that we have 32bit DMA hardware, but 64bit addresses
on LS2085A and ZynqMP, so let's enable EFI bounce buffers for all defconfigs
on these SoCs.
Signed-off-by: Alexander Graf
---
configs/ls2080a_emu_defconfig| 1 +
configs/ls2080a_simu_defconfig
Some hardware that is supported by U-Boot can not handle DMA above 32bits.
For these systems, we need to come up with a way to expose the disk interface
in a safe way.
This patch implements EFI specific bounce buffers. For non-EFI cases, this
apparently was no issue so far, since we can just defin
While testing our shiny new EFI support, I stumbled across systems that
have disk I/O hardware that can only access the lower 32bits of our
physical address space.
This is not a problem when running with the normal U-Boot flow, since we
define all "pointers" that get in use in our environment, so
On Tue, May 10, 2016 at 02:33:47PM +0530, Lokesh Vutla wrote:
> TI's Industrial Communication Engine EVM is a low cost hardware mainly
> developed for industrial communication type applications using serial
> or Ethernet based interfaces. This platform features TI's AM3359 with
> 800MHz single cor
On Tue, May 10, 2016 at 01:18:16PM +0530, Lokesh Vutla wrote:
> This series adds support for FIT and various AM335x based platforms
>
> BBB: http://pastebin.ubuntu.com/16340189/
> BBW: http://pastebin.ubuntu.com/16340238/
> AM335x-evm: http://pastebin.ubuntu.com/16340157/
> AM335x-evmsk: http:
On Sat, May 07, 2016 at 03:42:15AM +0200, Marek Vasut wrote:
> The following changes since commit
> bbca7108db79076d3a9a9c112792d7c4608a665c:
>
>
>
> ARM: tegra: import latest Jetson TK1 spreadsheet (2016-05-04 13:31:04
> -0700)
>
>
> are available in the git repository at:
>
>
>
> git
On Sat, May 07, 2016 at 03:41:11AM +0200, Marek Vasut wrote:
> The following changes since commit bbca7108db79076d3a9a9c112792d7c4608a665c:
>
> ARM: tegra: import latest Jetson TK1 spreadsheet (2016-05-04 13:31:04
> -0700)
>
> are available in the git repository at:
>
> git://git.denx.de/u-
On 05/11/2016 12:30 AM, Prabhakar Kushwaha wrote:
> QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
> development platform, with a complete debugging environment.
> The LS1012AQDS board supports the QorIQ LS1012A processor and is
> optimized to support the high-bandwidth DDR3L m
I'm adding support [1] for another zynq-based board (MYIR Zturn [2]).
This board has one peculiarity that I have to deal with: it has a shared reset
signal that hits both the USB PHY and the Ethernet PHY, and this is routed to
a GPIO that must be shaken down and up before using those two pheripher
On 05/11/2016 12:30 AM, Prabhakar Kushwaha wrote:
> QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
> development platform, with a complete debugging environment.
> The LS1012ARDB board supports the QorIQ LS1012A processor and is
> optimized to support the high-bandwidth DD
Hi Joe and Heiko,
I tried disabling the fastmap options, and it appears to be related to
these. With fastmap off, I am able two write without corrupting the
other volume. It looks like it may specifically be the autoupdate
feature, but I am still testing to be sure this is the case. I will l
IASL compiler does not provide a command line option to turn off
its non-warning message. To quieten the output when 'make -s',
redirect its output to /dev/null.
Signed-off-by: Bin Meng
---
Changes in v2: None
scripts/Makefile.lib | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --g
Windows might cache system information and only detect ACPI changes
if you modify the ACPI table versions.
Signed-off-by: Bin Meng
---
Changes in v2: None
doc/README.x86 | 6 ++
1 file changed, 6 insertions(+)
diff --git a/doc/README.x86 b/doc/README.x86
index 75762de..4d50feb 100644
---
Per ACPI spec, during ACPI OS initialization, OSPM can determine
that the ACPI hardware registers are owned by SMI (by way of the
SCI_EN bit in the PM1_CNT register), in which case the ACPI OS
issues the ACPI_ENABLE command to the SMI_CMD port. The SCI_EN bit
effectively tracks the ownership of the
Now that we already reserved high memory for configuration tables,
call high_table_malloc() to allocate tables from the region.
Signed-off-by: Bin Meng
---
Changes in v2: None
arch/x86/lib/tables.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/x86/lib/tables.c b/a
SeaBIOS can be loaded by U-Boot to aid the installation of Ubuntu
and Windows to a SATA drive and boot from there. Enable it on all
BayTrail boards.
Signed-off-by: Bin Meng
---
Changes in v2:
- New patch to enable SeaBIOS on all boards
configs/bayleybay_defconfig | 1 +
configs/
Currently when CONFIG_SEABIOS is on, U-Boot allocates configuration
tables via normal malloc(). To simplify, use a dedicated memory
region which is reserved on the stack before relocation for this
purpose. Add functions for reserve and malloc.
Signed-off-by: Bin Meng
---
Changes in v2: None
ar
Instead of asking each platform to provide reserve_arch(),
supply it in arch/x86/cpu/cpu.c in a unified way.
Signed-off-by: Bin Meng
---
Changes in v2: None
arch/x86/cpu/baytrail/valleyview.c | 8
arch/x86/cpu/broadwell/sdram.c | 5 -
arch/x86/cpu/cpu.c | 12
Since BayTrail, Intel starts to use new GPIO IPs in their chipset.
This adds the GPIO ASL, so that OS can load corresponding drivers
for it. On Linux, this is BayTrail pinctrl driver.
Signed-off-by: Bin Meng
---
Changes in v2:
- New patch to add GPIO ASL description
arch/x86/include/asm/arch-
As of now, U-Boot can support installing and booting Ubuntu/Windows
with the help of SeaBIOS. Update the documentation.
Signed-off-by: Bin Meng
---
Changes in v2: None
doc/README.x86 | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/doc/README.x86 b/doc/README.x8
Document how to make SeaBIOS load and run the VGA ROM of Intel
IGD device when loaded by U-Boot.
Signed-off-by: Bin Meng
---
Changes in v2: None
doc/README.x86 | 24
1 file changed, 24 insertions(+)
diff --git a/doc/README.x86 b/doc/README.x86
index 25cb218..250d5a3 1
BayTrail integrates an internal ns15550 compatible UART (PNP0501).
Its IRQ is hardwired to IRQ3 in old revision chipset, but in newer
revision one IRQ4 is being used for ISA compatibility. Handle this
correctly in the ASL file.
Linux does not need this ASL, but Windows need this to correctly
disco
When SeaBIOS is on, reserve configuration tables in reserve_arch().
Signed-off-by: Bin Meng
---
Changes in v2: None
arch/x86/cpu/cpu.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 2e27d78..e522ff3 100644
--- a/arc
coreboot_table.c only needs to be built when SeaBIOS is used.
Signed-off-by: Bin Meng
---
Changes in v2: None
arch/x86/lib/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index dc90df2..73e3e52 100644
--- a/arch/x86/lib
Before moving 'current' pointer during ACPI table writing, we always
check the table length to see if it is larger than the table header.
Since our purpose is to generate valid tables, the check logic is
always true, which can be avoided.
Signed-off-by: Bin Meng
---
Changes in v2:
- New patch t
The generated AmlCode[] from IASL already has the calculated DSDT
table checksum in place. No need for us to calculate it again.
Signed-off-by: Bin Meng
---
Changes in v2:
- New patch to remove the unnecessary checksum calculation of DSDT
arch/x86/lib/acpi_table.c | 6 --
1 file changed,
Currently U-Boot environment address is at offset 0x7fe00 of a 8MB
SPI flash. When creating a partial u-boot.rom image without flash
descriptor and ME firmware, U-Boot actually occupies the last 1MB
of the flash, and reprograming U-Boot causes previous environment
settings get lost which is not con
SeaBIOS can be loaded by U-Boot to aid the installation of Ubuntu
and Windows to a SATA drive and boot from there. But till now this
is broken. The installation either hangs forever or just crashes.
This series fixed a bunch of issues that affect the installation
of Ubuntu and Windows, and booting
At present board_final_cleanup() is called before booting a Linux
kernel. This actually needs to be done before booting anything,
like SeaBIOS, VxWorks or Windows.
Move the call to last_stage_init() instead.
Signed-off-by: Bin Meng
---
Changes in v2: None
arch/x86/cpu/coreboot/coreboot.c | 20
PIRQ routing table checksum is fixed up in copy_pirq_routing_table(),
which is fine if we only write the configuration table once. But with
the SeaBIOS case, when we write the table for the second time, the
checksum will be fixed up to zero per the checksum algorithm, which
is caused by the checksu
On Wed, 2016-05-11 at 11:54 +0200, Mario Six wrote:
> On Tue, May 10, 2016 at 1:22 AM, Hamish Martin <
> hamish.mar...@alliedtelesis.co.nz> wrote:
>
> >
> > Hi,
> >
> > I'm looking for uboot driver support for the Freescale QorIQ T2080 CPU.
> > This has 4 blocks of GPIOs similar to the single bl
On Tue, 2016-05-10 at 23:30 +0200, Marek Vasut wrote:
> On 05/10/2016 10:13 PM, dingu...@opensource.altera.com wrote:
> > From: Dinh Nguyen
> >
> > Update the pinmux and pll configuration for the Cyclone5 RevE or
> > later devkit.
> >
> > Signed-off-by: Dinh Nguyen
> > ---
> > Hi Marek,
>
> Hi
On 05/11/2016 12:28 PM, Masahiro Yamada wrote:
> UniPhier platform switched to DWC3 core with UniPhier specific
> glue layer to support USB3. This pre-DM driver is no longer
> needed.
>
> Signed-off-by: Masahiro Yamada
Reviewed-by: Marek Vasut
Best regards,
Marek Vasut
___
On 05/11/2016 12:28 PM, Masahiro Yamada wrote:
Please, do write commit messages.
> Signed-off-by: Masahiro Yamada
> ---
>
> arch/arm/Kconfig | 1 +
> include/configs/uniphier.h | 4
> 2 files changed, 5 insertions(+)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index
On 05/11/2016 12:28 PM, Masahiro Yamada wrote:
> Synopsys DWC3 IP generally works with an SoC-specific glue layer.
> DT binding for that is like this:
>
> usb3_glue {
> compatible = "foo,dwc3";
> ...
>
> usb3: usb3 {
> compatible = "snps,dwc3";
>
On 05/11/2016 12:28 PM, Masahiro Yamada wrote:
> Add UniPhier platform specific glue layer to support USB3 Host mode
> on Synopsys DWC3 IP.
>
> Signed-off-by: Masahiro Yamada
Reviewed-by: Marek Vasut
> ---
>
> drivers/usb/host/Kconfig | 7 +++
> drivers/usb/host/Makefile|
On 05/11/2016 01:03 PM, Masahiro Yamada wrote:
> Hi Marek,
Hi!
> 2016-05-07 1:40 GMT+09:00 Marek Vasut :
>> On 05/06/2016 01:31 PM, Masahiro Yamada wrote:
>>> Hi Marek,
>>
>> Hi!
>>
>>> 2016-05-06 19:50 GMT+09:00 Marek Vasut :
On 05/06/2016 12:36 PM, Masahiro Yamada wrote:
> This should
2016-05-11 19:28 GMT+09:00 Masahiro Yamada :
>
>
>
> Masahiro Yamada (10):
> usb: xhci: add struct devrequest declaration to xhci.h
> usb: dwc3: make DWC3 core support code into a driver
> usb: dwc3: add UniPhier specific glue layer
> ARM: uniphier: switch over to USB DM
> ARM: uniphier:
On 05/11/2016 12:28 PM, Masahiro Yamada wrote:
> If xhci.h is included without include/usb.h, the compiler
> complains like follows:
> warning: 'struct devrequest' declared inside parameter list
>
> Teach the compiler that devrequest is a structure.
> I found no reason include include/usb.h from x
Hi Marek,
2016-05-07 1:40 GMT+09:00 Marek Vasut :
> On 05/06/2016 01:31 PM, Masahiro Yamada wrote:
>> Hi Marek,
>
> Hi!
>
>> 2016-05-06 19:50 GMT+09:00 Marek Vasut :
>>> On 05/06/2016 12:36 PM, Masahiro Yamada wrote:
This should be declared for xhci_ctrl_tx() to avoid build error.
>>>
>>> Ca
UniPhier platform switched to DWC3 core with UniPhier specific
glue layer to support USB3. This pre-DM driver is no longer
needed.
Signed-off-by: Masahiro Yamada
---
drivers/usb/host/Kconfig | 7
drivers/usb/host/Makefile| 1 -
drivers/usb/host/xhci-uniphier.c | 85 -
Adjust xHCI nodes to use the DWC3 core and the SoC-specific glue
layer for former SoCs.
Signed-off-by: Masahiro Yamada
---
arch/arm/dts/uniphier-ph1-ld20.dtsi| 17 +
arch/arm/dts/uniphier-ph1-pro4-ref.dts | 4
arch/arm/dts/uniphier-ph1-pro4.dtsi| 32 +++
Add UniPhier platform specific glue layer to support USB3 Host mode
on Synopsys DWC3 IP.
Signed-off-by: Masahiro Yamada
---
drivers/usb/host/Kconfig | 7 +++
drivers/usb/host/Makefile| 1 +
drivers/usb/host/dwc3-uniphier.c | 110 +++
3 fil
Synopsys DWC3 IP generally works with an SoC-specific glue layer.
DT binding for that is like this:
usb3_glue {
compatible = "foo,dwc3";
...
usb3: usb3 {
compatible = "snps,dwc3";
...
};
};
The glue layer initializes
Masahiro Yamada (10):
usb: xhci: add struct devrequest declaration to xhci.h
usb: dwc3: make DWC3 core support code into a driver
usb: dwc3: add UniPhier specific glue layer
ARM: uniphier: switch over to USB DM
ARM: uniphier: enable DWC3 xHCI driver
usb: uniphier: remove UniPhier xHC
On Driver Model USB, EHCI and xHCI can be enabled at the same time.
PH1-Pro4 SoC has two EHCI cores and two xHCI cores, so enable the
Generic EHCI driver.
Signed-off-by: Masahiro Yamada
---
configs/uniphier_pro4_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/uniphier_pr
Signed-off-by: Masahiro Yamada
---
configs/uniphier_ld20_defconfig | 1 +
configs/uniphier_pro4_defconfig | 1 +
configs/uniphier_pxs2_ld6b_defconfig | 1 +
3 files changed, 3 insertions(+)
diff --git a/configs/uniphier_ld20_defconfig b/configs/uniphier_ld20_defconfig
index cbc65dd..f
Now USB 3.0 feature is enabled/disabled by CONFIG_USB_DWC3_UNIPHIER.
Signed-off-by: Masahiro Yamada
---
arch/arm/mach-uniphier/clk/clk-pro4.c | 6 +++---
arch/arm/mach-uniphier/clk/clk-pro5.c | 6 +++---
arch/arm/mach-uniphier/clk/clk-pxs2.c | 6 +++---
3 files changed, 9 insertions(+), 9 delet
If xhci.h is included without include/usb.h, the compiler
complains like follows:
warning: 'struct devrequest' declared inside parameter list
Teach the compiler that devrequest is a structure.
I found no reason include include/usb.h from xhci.h.
Signed-off-by: Masahiro Yamada
---
drivers/usb/h
Now UniPhier platform switched over to the DM-based xHCI driver.
The pin-muxing for that is automatically cared by the pinctrl
driver. These ad-hoc pin-muxing code is no longer needed.
Signed-off-by: Masahiro Yamada
---
arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c | 12
arch/arm/
Signed-off-by: Masahiro Yamada
---
arch/arm/Kconfig | 1 +
include/configs/uniphier.h | 4
2 files changed, 5 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6b65d8e..59410cb 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -723,6 +723,7 @@ config ARCH
Hi Tom, Marek,
For the time being I do not wish to make additional refactoring to the
code as I think it is better to wait until an alternative to the bus
number is found. My changes follow the current implementation of the
eeprom command, so if there are no additional comments, can this be
appli
On Tue, May 10, 2016 at 1:22 AM, Hamish Martin <
hamish.mar...@alliedtelesis.co.nz> wrote:
> Hi,
>
> I'm looking for uboot driver support for the Freescale QorIQ T2080 CPU.
> This has 4 blocks of GPIOs similar to the single block defined in
> arch/powerpc/include/asm/mpc85xx_gpio.h.
>
> If someone
On Wed, May 11, 2016 at 5:01 PM, Miao Yan wrote:
> 2016-05-11 10:11 GMT+08:00 Bin Meng :
>> Hi Miao,
>>
>> On Tue, May 10, 2016 at 10:10 AM, Miao Yan wrote:
>
> +config CMD_QEMU_FW_CFG
> + bool "qfw"
> + depends on X86
> + help
> + This provides a
2016-05-11 10:11 GMT+08:00 Bin Meng :
> Hi Miao,
>
> On Tue, May 10, 2016 at 10:10 AM, Miao Yan wrote:
+config CMD_QEMU_FW_CFG
+ bool "qfw"
+ depends on X86
+ help
+ This provides access to the QEMU firmware interface. The main
+
Hi,
I'm looking for uboot driver support for the Freescale QorIQ T2080 CPU.
This has 4 blocks of GPIOs similar to the single block defined in
arch/powerpc/include/asm/mpc85xx_gpio.h.
If someone is working on a driver for that CPU or similar, let me know.
Ideally this would fit the new driver m
Hi,
We are using P4080DS demo board. It has two 2GB Ram. We want to
optimize/reduce both bootloader time. For bootloader we use u-boot. While we
are working on u-boot, DDR is the one that takes more time. When we have
checked u-boot DDR initialization code timeout is stated 400 milliseconds
for e
Hi Kevin,
Am 09.05.2016 um 23:16 schrieb Kevin Smith:
> Hello,
>
> I would appreciate some UBI help/advice if you are able to provide it.
> I am trying to use UBI to store my u-boot environment, but when I try
> to 'saveenv', it is corrupting another volume of my UBI. I can image
> the rootfs v
Hi Tom,
>
> Well, this patch was a first pass at trying to separate out the logic.
> My end goal is to be able to use -kernel / -initrd / -dtb to pass in
> files "directly" to say vexpress_ca9x4 rather than have to fiddle with
> fake networking. So we need to keep that in mind when splitting the
Hi Bin,
On 11.05.2016 10:15, Bin Meng wrote:
On Wed, May 11, 2016 at 3:23 PM, Stefan Roese wrote:
Hi Bin,
On 09.05.2016 11:34, Bin Meng wrote:
This series fixed a bunch of issues that affect the installation
of Ubuntu and Windows, and booting Windows.
Testing was performed on MinnowMax by:
Hi Stefan,
On Wed, May 11, 2016 at 3:23 PM, Stefan Roese wrote:
> Hi Bin,
>
> On 09.05.2016 11:34, Bin Meng wrote:
>>
>> This series fixed a bunch of issues that affect the installation
>> of Ubuntu and Windows, and booting Windows.
>>
>> Testing was performed on MinnowMax by:
>> - Install Ubuntu
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c: In function
‘get_sys_info’:
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c:29:6: warning:
unused variable ‘rcw_tmp’ [-Wunused-variable]
u32 rcw_tmp;
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2: Sending as it is
arch/arm/cpu/ar
QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
development platform, with a complete debugging environment.
The LS1012AQDS board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
S
From: Abhimanyu Saini
Check if qixis supports memory-mapped read/write
before compiling IFC based qixis read/write functions.
Signed-off-by: Calvin Johnson
Signed-off-by: Abhimanyu Saini
Signed-off-by: Prabhakar Kushwaha
---
Chages for v2: New patch in this patch-set
board/freescale/common/
It is not mandatory for Layerscape SoCs to have SMMU. SoCs like
LS1012A are layerscape SoC without SMMU IP.
So put SMMU configuration code under SMMU_BASE.
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2: Sending as it is
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 ++
1 file changed
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes port
From: Abhimanyu Saini
Add QIXIS_LBMAP_BRDCFG_REG to the save offset of LBMAP
configuration register instead of hardcoding it in
set_lbmap() function.
Signed-off-by: Calvin Johnson
Signed-off-by: Abhimanyu Saini
Signed-off-by: Prabhakar Kushwaha
---
Chages for v2: New patch in this patch-set
The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.
This patch add support of LS1012A SoC along with
- Update platform & DD
Serial number, vendor id and page size are added for QSPI flash
common on both LS1012AQDS and LS1012ARDB i.e. S25FS512SDSMFI011.
Signed-off-by: Pratiyush Mohan Srivastava
Signed-off-by: Calvin Johnson
Signed-off-by: Mingkai Hu
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2: Sending as it
The QorIQ LS1012A processor is a new Freescale' SoC optimized for
battery-backed or USB-powered, integrates a single ARM Cortex-A53
core with a hardware packet forwarding engine and high-speed
interfaces to deliver line-rate networking performance.
LS1012AQDS, LS1012ARDB are a high-performance d
Other than LS1043A, LS1012A also Chassis Gen2 Architecture compliant.
So Avoid LS1043A specific defines in arch/arm
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2: Sending as it is
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +-
arch/arm/include/asm/arch-fsl-layerscape/fsl_
Hi Bin,
On 09.05.2016 11:34, Bin Meng wrote:
This series fixed a bunch of issues that affect the installation
of Ubuntu and Windows, and booting Windows.
Testing was performed on MinnowMax by:
- Install Ubuntu 14.04 and boot
- Install Windows 8.1 and boot
- Install Windows 10 and boot
This ser
On 09.05.2016 11:34, Bin Meng wrote:
Currently U-Boot environment address is at offset 0x7fe00 of a 8MB
SPI flash. When creating a partial u-boot.rom image without flash
descriptor and ME firmware, U-Boot actually occupies the last 1MB
of the flash, and reprograming U-Boot causes previous environ
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