Hi Kever,
On 07/29/2016 11:35 AM, Kever Yang wrote:
> This patch add driver for:
> - clock driver including set_rate for cpu, mmc, vop, I2C.
> - sysreset driver
> - grf syscon driver
>
> Signed-off-by: Kever Yang
I don't have a knowledge for rockchip..So i don't add the comments relevant to
ro
Hi Kever,
On 07/29/2016 03:42 PM, Kever Yang wrote:
> Init clock for eMMC controller.
Sorry for too often requesting something.
If you add the commit msg in more detail, then it's more great.:)
"Initialize the maximum clock with CMU, before setting the rockchip sdhci host
controller."
And when
On 28/07/16 13:06, Marek Vasut wrote:
+++ b/board/imgtec/boston/boston-regs.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef __BOARD_BOSTON_REGS_H__
+#define __BOARD_BOSTON_REGS_H__
+
+#define BOSTON_PLAT_BASE
On Thursday 28 July 2016 05:27 PM, Vignesh R wrote:
> AM437x SK and AM437x IDK EVMs have 64MB flash, therefore enable
> CONFIG_SPI_FLASH_BAR to access flash regions above 16MB.
>
> Signed-off-by: Vignesh R
Reviewed-by: Mugunthan V N
Regards
Mugunthan V N
__
On Monday 25 July 2016 03:45 PM, Vignesh R wrote:
> According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update
> the driver to use the same.
>
> Signed-off-by: Vignesh R
Reviewed-by: Mugunthan V N
Regards
Mugunthan V N
___
U-Boot mailing
On Monday 25 July 2016 03:45 PM, Vignesh R wrote:
> From: Lokesh Vutla
>
> According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, hence
> update QSPI input clock divider value (DPLL_PER_HS13) to provide 76.8MHz
> clock, so that driver can use the same.
>
> Signed-off-by: Vignesh R
> --
On Monday 25 July 2016 03:45 PM, Vignesh R wrote:
> Now that QSPI driver can support 76.8MHz, update the
> CONFIG_SF_DEFAULT_SPEED to the same value.
>
> Signed-off-by: Vignesh R
Reviewed-by: Mugunthan V N
Regards
Mugunthan V N
___
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On Monday 25 July 2016 03:45 PM, Vignesh R wrote:
> According to AM572x DM SPRS953A, QSPI max bus speed is 76.8MHz.
> Therefore update the spi-max-frequency value of QSPI node for DRA74 and
> DRA72 evm. This increase flash read speed by ~2MB/s.
>
> Signed-off-by: Vignesh R
> ---
Reviewed-by: Mug
This series adds support for QSPI for am571x-idk and am572x-idk. The
flash is same as the one present on DRA74 EVM.
Tested on am572x-idk and am571x-idk.
Vignesh R (2):
ARM: am57xx_evm: Enable QSPI support
ARM: dts: am57xx-idk-common: Enable support for QSPI
arch/arm/dts/am57xx-idk-common.d
AM571x and AM572x IDK have a spansion s25fl256s QSPI flash on the board
connected to TI QSPI over CS0. Hence, add QSPI and flash slave
DT nodes.
Signed-off-by: Vignesh R
---
v2: No changes
arch/arm/dts/am57xx-idk-common.dtsi | 49 +
1 file changed, 49 insert
AM571x IDK and AM572x IDK EVMs have spansion s25fl256s QSPI flash on the
board connected to TI QSPI IP over CS0. Therefore enable QSPI support.
Signed-off-by: Vignesh R
---
v2: Add entries for am57xx_hs_evm_defconfig and am57xx_evm_nodt_defconfig
configs/am57xx_evm_defconfig | 5 +
On Friday 29 July 2016 12:03 PM, Vignesh R wrote:
> AM571x IDK and AM572x IDK EVMs have spansion s25fl256s QSPI flash on the
> board connected to TI QSPI IP over CS0. Therefore enable QSPI support.
>
> Signed-off-by: Vignesh R
> ---
> configs/am57xx_evm_defconfig | 5 +
> include/configs/am
On Friday 29 July 2016 02:24 PM, Mugunthan V N wrote:
> On Friday 29 July 2016 12:03 PM, Vignesh R wrote:
>> AM571x IDK and AM572x IDK EVMs have spansion s25fl256s QSPI flash on the
>> board connected to TI QSPI IP over CS0. Therefore enable QSPI support.
>>
>> Signed-off-by: Vignesh R
>> ---
>>
On Friday 29 July 2016 02:27 PM, Vignesh R wrote:
>
>
> On Friday 29 July 2016 02:24 PM, Mugunthan V N wrote:
>> On Friday 29 July 2016 12:03 PM, Vignesh R wrote:
>>> AM571x IDK and AM572x IDK EVMs have spansion s25fl256s QSPI flash on the
>>> board connected to TI QSPI IP over CS0. Therefore ena
On Friday 29 July 2016 02:22 PM, Vignesh R wrote:
> AM571x IDK and AM572x IDK EVMs have spansion s25fl256s QSPI flash on the
> board connected to TI QSPI IP over CS0. Therefore enable QSPI support.
>
> Signed-off-by: Vignesh R
Reviewed-by: Mugunthan V N
Regards
Mugunthan V N
On Friday 29 July 2016 02:22 PM, Vignesh R wrote:
> AM571x and AM572x IDK have a spansion s25fl256s QSPI flash on the board
> connected to TI QSPI over CS0. Hence, add QSPI and flash slave
> DT nodes.
>
> Signed-off-by: Vignesh R
Reviewed-by: Mugunthan V N
Regards
Mugunthan V N
___
This patch enables NFSv3 support.
If NFSv2 is available use it as usual.
If NFSv2 is not available, but NFSv3 is available, use NFSv3.
If NFSv2 and NFSv3 are not available, print an error message since NFSv4 is not
supported.
Tested on iMX6 sabrelite with 4 Linux NFS servers:
* NFSv2 + NFSv3 +
On 27/07/16 13:02, Daniel Schwierzeck wrote:
Am 27.07.2016 um 12:51 schrieb Zubair Lutfullah Kakakhel:
Mostly the same as the Kernel upstream device tree file except for
- alias for the serial console node
- ethernet node as the ethernet stuff isn't upstream on kernel.org yet
- uart clock-f
Hi,
On 27-07-16 21:14, Siarhei Siamashka wrote:
Hello Hans,
I just realized I forgot to reply to this bit:
Also changing the MAC address generation algorithm is an invasive
change, which is affecting the end users.
Agreed, which is why I'm only changing it for the H3 and why I'm
changing
Hi,
On 27/07/16 13:13, Daniel Schwierzeck wrote:
Am 27.07.2016 um 12:51 schrieb Zubair Lutfullah Kakakhel:
MIPSfpga is an FPGA based dev platform.
In a nutshell, its a microAptiv cpu core with lots of Xilinx IP blocks
The FPGA dev board used is the Nexys4DDR board by Digilent.
For more inf
From: Soren Brinkmann
This partly reverts commit:
"ARM64: zynqmp: Add SPL support support"
(sha1: e6a9ed04e78cf87ec97e306fa4e7a1669ef98df6)
Stack can rewrite ATF code.
Signed-off-by: Soren Brinkmann
Signed-off-by: Michal Simek
---
include/configs/xilinx_zynqmp.h | 3 ++-
1 file changed, 2 i
It seems that bytes 13-14 of the SID / bytes 1-2 from word 3 of the SID
are always 0 on H3 making it a poor candidate to use as source for the
serialnr / mac-address, and the other non constant words (1 and 2) also
have quite a few bits which are the same for some boards,
This commits switches to
This fixes the following CACHE warnings when using sun8i_emac:
=> dhcp
BOOTP broadcast 1
BOOTP broadcast 2
CACHE: Misaligned operation at range [7bf594a8, 7bf59628]
BOOTP broadcast 3
CACHE: Misaligned operation at range [7bf59c90, 7bf59e10]
CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8]
Remove unnecessary board specific config file for DC4
board.
Signed-off-by: Siva Durga Prasad Paladugu
---
configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 1 -
include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h | 15 ---
2 files changed, 16 deletions(-)
delete mode 100644 include/
Move the config IDENT_STRING to Kconfig for ZynqMP.
Signed-off-by: Siva Durga Prasad Paladugu
---
common/Kconfig | 5 +
1 file changed, 5 insertions(+)
diff --git a/common/Kconfig b/common/Kconfig
index 46e7173..011f9b3 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -198,6 +198,11 @@ c
Move config IDENT_STRING to defconfig for all
zynqmp boards.
Signed-off-by: Siva Durga Prasad Paladugu
---
configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 +
configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 +
configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 1 +
configs/xilinx_zynqmp
On Fri, 2016-07-29 at 11:49 +0200, Hans de Goede wrote:
> It seems that bytes 13-14 of the SID / bytes 1-2 from word 3 of the
> SID
> are always 0 on H3 making it a poor candidate to use as source for
> the
> serialnr / mac-address, and the other non constant words (1 and 2)
> also
> have quite a f
On Fri, 2016-07-29 at 12:01 +0200, Hans de Goede wrote:
> This fixes the following CACHE warnings when using sun8i_emac:
>
> => dhcp
> BOOTP broadcast 1
> BOOTP broadcast 2
> CACHE: Misaligned operation at range [7bf594a8, 7bf59628]
> BOOTP broadcast 3
> CACHE: Misaligned operation at range [7bf59
On 29 July 2016 at 15:31, Siva Durga Prasad Paladugu
wrote:
> Move config IDENT_STRING to defconfig for all
> zynqmp boards.
>
> Signed-off-by: Siva Durga Prasad Paladugu
> ---
> configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 +
> configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 +
> c
On 29 July 2016 at 15:31, Siva Durga Prasad Paladugu
wrote:
> Move the config IDENT_STRING to Kconfig for ZynqMP.
Didn't understand, from where IDENT_STRING kconfig option is moved
from to common/Kconfig or added new kconfig entry help for
IDENT_STRING.?
>
> Signed-off-by: Siva Durga Prasad Pala
From: Hou Zhiqiang
Signed-off-by: Hou Zhiqiang
---
arch/arm/lib/psci-dt.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/lib/psci-dt.c b/arch/arm/lib/psci-dt.c
index af49c24..baf6d70 100644
--- a/arch/arm/lib/psci-dt.c
+++ b/arch/arm/lib/psci-dt.c
@@ -65,6 +65,8 @@ int fdt_psci(
From: Hou Zhiqiang
Appended the compatible strings of old version PSCI to the latest version
supported. And there are some psci functions' property must be added to DT
only for psci version 0.1, such as 'cpu_on' 'cpu_off' etc.
Note:
The PSCI version 0.1 isn't supported by ARMv8 Secure Firmware F
On 29 July 2016 at 15:31, Siva Durga Prasad Paladugu
wrote:
> Remove unnecessary board specific config file for DC4
> board.
>
> Signed-off-by: Siva Durga Prasad Paladugu
Acked-by: Jagan Teki
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Hi Jagan,
Thanks. I'll fix it in the next version.
Regards,
Qianyu
> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Thursday, July 28, 2016 9:36 PM
> To: Qianyu Gong
> Cc: york sun ; u-boot@lists.denx.de; Prabhakar Kushwaha
> ; Zhiqiang Hou ;
> Wenbin So
From: Hou Zhiqiang
Identify the PSCI node only by its name, so removed the code finding
it by compatible string.
Signed-off-by: Hou Zhiqiang
---
arch/arm/lib/psci-dt.c | 17 -
1 file changed, 17 deletions(-)
diff --git a/arch/arm/lib/psci-dt.c b/arch/arm/lib/psci-dt.c
index 8d
Hi,
On Thu, 28 Jul 2016 20:35:21 +0200
Hans de Goede wrote:
> Hi,
>
> On 28-07-16 05:13, Chen-Yu Tsai wrote:
> > Hi,
> >
> > On Thu, Jul 28, 2016 at 3:14 AM, Siarhei Siamashka
> > wrote:
> >> Hello Hans,
> >>
> >> On Wed, 27 Jul 2016 18:10:34 +0200
> >> Hans de Goede wrote:
> >>
> >>> It
Hi Jagan,
> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Friday, July 29, 2016 4:14 PM
> To: Siva Durga Prasad Paladugu
> Cc: u-boot@lists.denx.de; Michal Simek ; Siva Durga
> Prasad Paladugu
> Subject: Re: [U-Boot] [PATCH 2/3] zynqmp: Move config IDENT
On Fri, 29 Jul 2016 11:49:45 +0200
Hans de Goede wrote:
> It seems that bytes 13-14 of the SID / bytes 1-2 from word 3 of the SID
> are always 0 on H3 making it a poor candidate to use as source for the
> serialnr / mac-address, and the other non constant words (1 and 2) also
> have quite a few b
Hi Jagan,
> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Friday, July 29, 2016 4:21 PM
> To: Siva Durga Prasad Paladugu
> Cc: u-boot@lists.denx.de; Michal Simek ; Siva Durga
> Prasad Paladugu
> Subject: Re: [U-Boot] [PATCH 1/3] Kconfig: zynqmp: Move con
This series adds support for TI's PCF8575 I2C GPIO expander[1] based on
Linux Kernel driver for the same. Also adds support for ethernet to use
new PCF8575 driver to select appropriate cpsw slaves on dra72.
Depends on I2C DM support [2]
Tested on DRA72 EVM.
[1]http://www.ti.com/lit/ds/symlink/p
On DRA72 EVM, cpsw slaves may be muxed with other modules. This
selection is controlled by a pcf gpio line. Add support for cpsw driver
to acquire mode-gpios and select the appropriate slave using gpio APIs.
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
---
v2: Drop extra blank line
drivers/
TI's PCF8575 is a 16-bit I2C GPIO expander.The device features a
16-bit quasi-bidirectional I/O ports. Each quasi-bidirectional I/O can
be used as an input or output without the use of a data-direction
control signal. The I/Os should be high before being used as inputs.
Read the device documentatio
On DRA7, pcf chip present at address 0x21 on i2c1, is used to
switch between cpsw slave0 and slave1. Hence, enable PCF
driver for the same.
Signed-off-by: Vignesh R
---
v2: No change
include/configs/dra7xx_evm.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/configs/dra7xx_ev
On DRA72 EVM, cpsw slave1 is muxed with VIN2A, hence switch to cpsw
slave0 for ethernet. This is controlled by pcf gpio line. Add
appropriate mode-gpios DT entry so that driver can select the required
slave.
Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
---
v2: no change
arch/arm/dts/dra72-e
On 29.7.2016 13:14, Siva Durga Prasad Paladugu wrote:
> Hi Jagan,
>
>> -Original Message-
>> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
>> Sent: Friday, July 29, 2016 4:14 PM
>> To: Siva Durga Prasad Paladugu
>> Cc: u-boot@lists.denx.de; Michal Simek ; Siva Durga
>> Prasad Paladug
On 29 July 2016 at 16:48, Siva Durga Prasad Paladugu
wrote:
> Hi Jagan,
>
>> -Original Message-
>> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
>> Sent: Friday, July 29, 2016 4:21 PM
>> To: Siva Durga Prasad Paladugu
>> Cc: u-boot@lists.denx.de; Michal Simek ; Siva Durga
>> Prasad P
Hi Simon,
2016-07-17 22:59 GMT+02:00 Simon Glass :
> On 5 July 2016 at 17:10, Simon Glass wrote:
> > This new function is more convenient for callers, and handles
> pre-relocation
> > situations automatically.
> >
> > Signed-off-by: Simon Glass
> > ---
> >
> > Changes in v2:
> > - Add new patch
Serial driver is getting clk information via DT that's why
also clk node needs to have this flag.
Different behavior was introduced by:
"dm: Use dm_scan_fdt_dev() directly where possible"
(sha1: 911954859d6dece49c3e4835faea004cfe392506)
where simple-bus driver starts to call dm_scan_fdt_dev() whic
From: Hou Zhiqiang
The PPA binary may be stored on QSPI flash instead of NOR.
So, deprecated CONFIG_SYS_LS_PPA_FW_IN_NOR in favour of
CONFIG_SYS_LS_PPA_FW_IN_XIP to prevent fragmentation of code
by addition of a new QSPI specific flag.
Signed-off-by: Hou Zhiqiang
Signed-off-by: Abhimanyu Saini
On Friday 29 July 2016 11:59 AM, Keerthy wrote:
On SoCs like DRA7, OMAP5 one cannot enable hypervisor mode directly from the
u-boot because the ROM code puts the chip to supervisor mode after it
jumps to boot loader.
Patch 1: Introduces a weak function which can be overridden specific to
SoCs
With the number of Rockchip clock drivers increasing, don't clutter up
the core drivers/clk directory with them and instead move them out of
the way into a separate subdirectory.
Suggested-by: Simon Glass
Signed-off-by: Heiko Stuebner
---
drivers/clk/Makefile| 3 +--
drivers
Hi Vikas,
2016-07-21 6:59 GMT+09:00 Vikas MANOCHA :
> Hi Tom,
>
> > -Original Message-
> > From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Tom Rini
> > Sent: Saturday, July 16, 2016 6:51 AM
> > To: tnishinaga@gmail.com
> > Cc: u-boot@lists.denx.de; gre...@linuxfoundati
On Thu, Jul 28, 2016 at 01:56:16PM +0200, Stefano Babic wrote:
> Hi Tom,
>
> please pull from u-boot-imx (master), thanks!
>
>
> The following changes since commit 19ce924ff914f315dc2fdf79f357825c513aed6e:
>
> Prepare v2016.07 (2016-07-11 15:01:01 -0400)
>
> are available in the git reposit
On Thu, Jul 28, 2016 at 05:27:57PM +0530, Vignesh R wrote:
> AM437x SK and AM437x IDK EVMs have 64MB flash, therefore enable
> CONFIG_SPI_FLASH_BAR to access flash regions above 16MB.
>
> Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
--
Tom
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On Thu, Jul 28, 2016 at 03:57:20AM +0300, Max Filippov wrote:
> print_bi_dram outputs start address and size for each DRAM bank.
>
> Signed-off-by: Max Filippov
Reviewed-by: Tom Rini
--
Tom
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On Thu, Jul 28, 2016 at 03:57:21AM +0300, Max Filippov wrote:
> print_bi_flash outputs flashstart, flashsize and flashoffset lines.
>
> Signed-off-by: Max Filippov
Reviewed-by: Tom Rini
--
Tom
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On Wed, Jul 27, 2016 at 12:12:39PM -0500, Andreas Dannenberg wrote:
> This commit allows injecting a board/platform/device-specific post-
> processing function into the FIT image data loading process, which can
> include modifying the size and altering the starting source address of
> an image dat
On Thu, Jul 28, 2016 at 03:57:24AM +0300, Max Filippov wrote:
> print_std_bdinfo outputs typical set of board information entries:
> boot params location, memory and flash addresses and sizes, network
> interfaces information and configured serial baud rate.
>
> Signed-off-by: Max Filippov
Revi
On Thu, Jul 28, 2016 at 03:57:23AM +0300, Max Filippov wrote:
> print_baudrate outputs serial baud rate.
>
> Signed-off-by: Max Filippov
Reviewed-by: Tom Rini
--
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On Thu, Jul 28, 2016 at 03:57:19AM +0300, Max Filippov wrote:
> print_bi_mem outputs memstart and memsize lines.
>
> Signed-off-by: Max Filippov
Reviewed-by: Tom Rini
--
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On Thu, Jul 28, 2016 at 03:57:18AM +0300, Max Filippov wrote:
> print_bi_boot_params outputs boot parameters structure location.
>
> Signed-off-by: Max Filippov
Reviewed-by: Tom Rini
--
Tom
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On Thu, Jul 28, 2016 at 04:40:29AM -0700, kubiznak.petr wrote:
> Hello,
>
> I wonder whether it is possible to dynamically enable/disable a command.
> Since u-boot does not provide any secure authentication method, it is
> dangerous to keep some commands available to a potential hacker. E.g.
>
On Thu, Jul 28, 2016 at 03:57:22AM +0300, Max Filippov wrote:
> print_eth_ip_addr outputs eth configurations for up to 6 interfaces and
> configured IP address.
>
> Signed-off-by: Max Filippov
Reviewed-by: Tom Rini
--
Tom
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On 29 July 2016 at 06:47, Heiko Stuebner wrote:
>
> With the number of Rockchip clock drivers increasing, don't clutter up
> the core drivers/clk directory with them and instead move them out of
> the way into a separate subdirectory.
>
> Suggested-by: Simon Glass
> Signed-off-by: Heiko Stuebner
On Thu, Jul 28, 2016 at 9:53 PM, Tapani wrote:
> On Thu, 28 Jul 2016 17:50:56 +
> york sun wrote:
>
>> On 07/28/2016 10:42 AM, Tim Harvey wrote:
>> > Greetings,
>> >
>> > I don't see U-Boot support for the TechNexion designed/built
>> > LS1021A-IoT. I've got one on my desk and am still muddli
On Fri, Jul 29, 2016 at 02:22:30PM +0530, Vignesh R wrote:
> AM571x IDK and AM572x IDK EVMs have spansion s25fl256s QSPI flash on the
> board connected to TI QSPI IP over CS0. Therefore enable QSPI support.
>
> Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
--
Tom
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On 27 July 2016 at 11:12, Andreas Dannenberg wrote:
> This commit allows injecting a board/platform/device-specific post-
> processing function into the FIT image data loading process, which can
> include modifying the size and altering the starting source address of
> an image data artifact. This
On Fri, Jul 29, 2016 at 04:50:23PM +0530, Vignesh R wrote:
> On DRA7, pcf chip present at address 0x21 on i2c1, is used to
> switch between cpsw slave0 and slave1. Hence, enable PCF
> driver for the same.
>
> Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
--
Tom
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Description:
On Fri, Jul 29, 2016 at 02:22:31PM +0530, Vignesh R wrote:
> AM571x and AM572x IDK have a spansion s25fl256s QSPI flash on the board
> connected to TI QSPI over CS0. Hence, add QSPI and flash slave
> DT nodes.
>
> Signed-off-by: Vignesh R
Reviewed-by: Tom Rini
--
Tom
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Descript
On Fri, Jul 29, 2016 at 4:31 AM, Guillaume GARDET
wrote:
> This patch enables NFSv3 support.
> If NFSv2 is available use it as usual.
> If NFSv2 is not available, but NFSv3 is available, use NFSv3.
> If NFSv2 and NFSv3 are not available, print an error message since NFSv4 is
> not supported.
>
>
On Wed, Jul 27, 2016 at 9:26 AM, Paul Burton wrote:
> Reading the PCI BAR & converting the result to a physical address is not
> safe across all architectures. For example on MIPS the virtual:physical
> mapping is not 1:1, so we cannot directly make use of the physical
> address.
>
> Use the more
On Wed, Jul 27, 2016 at 9:26 AM, Paul Burton wrote:
> The pch_gbe driver previously casted pointers to & from unsigned 32 bit
> integers in many locations. This breaks the driver on 64 bit systems,
> producing streams of compiler warnings about mismatched pointer &
> integer sizes and then failing
Mostly the same as the Kernel upstream device tree file except for
- alias for the serial console node
- ethernet node as the ethernet stuff isn't upstream on kernel.org yet
- uart clock-frequency passed directly in the node
Signed-off-by: Zubair Lutfullah Kakakhel
Reviewed-by: Paul Burton
Revi
MIPSfpga is an FPGA based dev platform by Imagination Technologies Ltd.
DDR is already initialized before u-boot.
And the peripherals supported in the u-boot port are an n16550 uart and
a xilinx ethernet IP (axi_emaclite) which already have drivers in u-boot.
Hence the port is mostly DT + config
On Wed, Jul 27, 2016 at 6:25 AM, Zubair Lutfullah Kakakhel
wrote:
> Virtual to physical mapping isn't necessarily 1:1 for all architectures
>
> Using ioremap_nocache allows for the arch code to translate the
> physical address to a virtual address.
>
> Signed-off-by: Zubair Lutfullah Kakakhel
> R
On Wed, Jul 27, 2016 at 6:25 AM, Zubair Lutfullah Kakakhel
wrote:
> out_be32 and in_be32 are actually #defined to little endian
> writel/readl in arch/microblaze.
>
> Just use __raw_writel/readl instead. That is also what is used
> in the Linux kernel driver for this IP block
>
> Tested on MIPSfpg
On Wed, Jul 27, 2016 at 6:25 AM, Zubair Lutfullah Kakakhel
wrote:
> Signed-off-by: Zubair Lutfullah Kakakhel
> Reviewed-by: Paul Burton
Acked-by: Joe Hershberger
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On Fri, Jul 29, 2016 at 6:20 AM, Vignesh R wrote:
> On DRA72 EVM, cpsw slaves may be muxed with other modules. This
> selection is controlled by a pcf gpio line. Add support for cpsw driver
> to acquire mode-gpios and select the appropriate slave using gpio APIs.
>
> Signed-off-by: Vignesh R
> Re
MIPSfpga is an FPGA based dev platform.
In a nutshell, its a microAptiv cpu core with lots of Xilinx IP blocks
The FPGA dev board used is the Nexys4DDR board by Digilent.
For more information, check the Readme file in board/imgtec/xilfpga
Signed-off-by: Zubair Lutfullah Kakakhel
Reviewed-by: P
On Fri, Jul 29, 2016 at 07:51:53AM -0600, Simon Glass wrote:
> On 27 July 2016 at 11:12, Andreas Dannenberg wrote:
> > This commit allows injecting a board/platform/device-specific post-
> > processing function into the FIT image data loading process, which can
> > include modifying the size and a
On Fri, Jul 29, 2016 at 04:37:31PM +0200, Petr Kubizňák wrote:
> Hi Tom, thanks for your reply.
>
> Such way is of course possible, but you surely know I'm rather
> interested in more clever solutions. Besides the understandable fact
> that I don't want to maintain two u-boot variants and flash i
Hi Tom, thanks for your reply.
Such way is of course possible, but you surely know I'm rather
interested in more clever solutions. Besides the understandable fact
that I don't want to maintain two u-boot variants and flash it twice, I
also believe it can be useful to lock "almost everything" a
On 07/28/2016 07:53 AM, Stefano Babic wrote:
Hi Akshay,
On 28/07/2016 12:12, Stefano Babic wrote:
Hi Akshay,
this looks good to me. I apply it, and I let you think about an upgrade
to SPL for this board.
The patch breaks most of i.MX6 boards because it redefines IMX_CONFIG.
In fact:
T
On 29/07/2016 17:07, Akshay Bhat wrote:
>
>
> On 07/28/2016 07:53 AM, Stefano Babic wrote:
>> Hi Akshay,
>>
>>
>> On 28/07/2016 12:12, Stefano Babic wrote:
>>> Hi Akshay,
>>>
>>> this looks good to me. I apply it, and I let you think about an upgrade
>>> to SPL for this board.
>>>
>>
>> The patch
Hi York,
with commit 5605dc6135f6f26560ef3b0c6ebc5141c531179a you fix wr_lat bits of
timing_cfg_2 register for FSL ddr driver. Unfortunately this fix is wrong as
(wr_lat & 0x10) is already 5 bits. To make things clearer maybe it is better to
set wr_lat this way
diff --git a/drivers/ddr/fsl/ctr
Hey U-Boot list,
I have some trouble with building U-BOOT for my Tinkerforge RED-Brick.
Its an Allwinner A10s powered little development SoC.
http://www.tinkerforge.com/de/doc/Hardware/Bricks/RED_Brick.html thats
all german.
I just made myself a Configuration, you will find it in the attachm
On 07/29/2016 03:37 AM, Zhiqiang Hou wrote:
> From: Hou Zhiqiang
>
> Appended the compatible strings of old version PSCI to the latest version
> supported. And there are some psci functions' property must be added to DT
> only for psci version 0.1, such as 'cpu_on' 'cpu_off' etc.
>
> Note:
> The P
Add support for Advantech DMS-BA16 board. The board is based on Advantech
BA16 module which has a i.MX6D processor. The board supports:
- FEC Ethernet
- USB Ports
- SDHC and MMC boot
- SPI NOR
- LVDS and HDMI display
Basic information about the module:
- Module manufacturer: Advantech
- CPU
On 07/28/2016 11:50 PM, Alexander Graf wrote:
> We create 2 sets of page tables: One for normal operation, one for
> emergency (used while modifying the former).
>
> Because the page tables grow dynamically, we have code that checks
> for overflow. Unfortunately we didn't adjust the available space
On 07/29/2016 08:19 AM, Thomas Schaefer wrote:
> Hi York,
>
> with commit 5605dc6135f6f26560ef3b0c6ebc5141c531179a you fix wr_lat bits of
> timing_cfg_2 register for FSL ddr driver. Unfortunately this fix is wrong as
> (wr_lat & 0x10) is already 5 bits. To make things clearer maybe it is better
Commit 5605dc6 tried to fix wr_lat bit in timing_cfg_2, but the
change was wrong. wr_lat has 5 bits with MSB at [13] and lower
4 bits at [9:12], in big-endian convention.
Signed-off-by: York Sun
Reported-by: Thomas Schaefer
---
drivers/ddr/fsl/ctrl_regs.c | 2 +-
1 file changed, 1 insertion(+)
On 07/28/2016 01:28 PM, Benjamin Tietz wrote:
Hello Vikas, hello Simon,
the new clk-API leaves me with a problem. Previously there was a
seperate way to access the clock-device itself (using clk_[gs]et_rate) and
the peripherals connected (clk_[gs]et_periph_rate). The former case now isn't
availa
Ok, I get it, then I'll have to deal with two defconfigs and reflashing
for now.
Anyway, at least a user feedback / feature request... I believe it would
be useful for many users to have a manufacturing mode, which they would
escape permanently by e.g. executing some command. In normal mode, s
On 07/29/2016 06:47 AM, Tim Harvey wrote:
> On Thu, Jul 28, 2016 at 9:53 PM, Tapani wrote:
>> On Thu, 28 Jul 2016 17:50:56 +
>> york sun wrote:
>>
>>> On 07/28/2016 10:42 AM, Tim Harvey wrote:
Greetings,
I don't see U-Boot support for the TechNexion designed/built
LS1021A-
Update maintainers for secure boot targets.
Signed-off-by: York Sun
---
board/freescale/b4860qds/MAINTAINERS | 2 +-
board/freescale/bsc9132qds/MAINTAINERS | 2 +-
board/freescale/corenet_ds/MAINTAINERS | 2 +-
board/freescale/ls1021atwr/MAINTAINERS | 4
board/freescale/ls1043ardb/MAINTA
Hello Stephen,
On Fri, Jul 29, 2016 at 10:04:56AM -0600, Stephen Warren wrote:
> On 07/28/2016 01:28 PM, Benjamin Tietz wrote:
> >Hello Vikas, hello Simon,
> >
> >the new clk-API leaves me with a problem. Previously there was a
> >seperate way to access the clock-device itself (using clk_[gs]et_ra
Update maintainers for secure boot targets.
Signed-off-by: York Sun
---
This is second resend. Somehow original mails weren't received by
mailing list.
board/freescale/b4860qds/MAINTAINERS | 2 +-
board/freescale/bsc9132qds/MAINTAINERS | 2 +-
board/freescale/corenet_ds/MAINTAINERS | 2
On 07/29/2016 07:58 AM, york@nxp.com wrote:
> On 07/29/2016 06:47 AM, Tim Harvey wrote:
>> On Thu, Jul 28, 2016 at 9:53 PM, Tapani wrote:
>>> On Thu, 28 Jul 2016 17:50:56 +
>>> york sun wrote:
>>>
On 07/28/2016 10:42 AM, Tim Harvey wrote:
> Greetings,
>
> I don't see U-Bo
On 07/29/2016 11:26 AM, Benjamin Tietz wrote:
Hello Stephen,
On Fri, Jul 29, 2016 at 10:04:56AM -0600, Stephen Warren wrote:
On 07/28/2016 01:28 PM, Benjamin Tietz wrote:
Hello Vikas, hello Simon,
the new clk-API leaves me with a problem. Previously there was a
seperate way to access the cloc
On 29 July 2016 at 14:12, Mugunthan V N wrote:
> On Monday 25 July 2016 03:45 PM, Vignesh R wrote:
>> From: Lokesh Vutla
>>
>> According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, hence
>> update QSPI input clock divider value (DPLL_PER_HS13) to provide 76.8MHz
>> clock, so that driver
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