On Mon, Sep 25, 2017 at 4:10 PM, Lukasz Majewski wrote:
> The content of Bank Address Register (BAR) is volatile. It is cleared
> after power cycle or reset command (RESET F0h).
>
> Some memories (like e.g. s25fl256s) use it to access memory larger than
> 0x100 (16 MiB).
>
> The problem shows
Hi Chris,
On 26.09.2017 00:29, Chris Packham wrote:
For the internet historians,
On Thu, Sep 21, 2017 at 4:25 PM, Chris Packham wrote:
On Wed, Sep 20, 2017 at 5:31 PM, Stefan Roese wrote:
Hi Chris,
On 19.09.2017 20:58, Chris Packham wrote:
When you did the port from Marvell's source did
On Isn, 2017-09-25 at 11:21 +0200, Marek Vasut wrote:
> On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Add support to memory allocation in SPL for preparation to enable
> > FAT
> > in SPL. Memory allocation is needed by FAT to work properly.
> >
> >
On Isn, 2017-09-25 at 11:20 +0200, Marek Vasut wrote:
> On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > This patch is for enabling the DDR support on Arria 10.
> >
> > Signed-off-by: Tien Fong Chee
> > ---
> > drivers/ddr/altera/Makefile | 1 +
> >
On Tue, Sep 26, 2017 at 9:07 AM, Liam Beguin wrote:
>
> Resending with proper CC since the email came back.
>
> On 24/09/17 09:36 PM, Liam Beguin wrote:
>> Hi,
>>
>> I'm testing a new Xilinx zynqmp dev board and was not able to probe the
>> qspi with the latest mainline U-Boot. I see that there is
Hi Chris,
On 26.09.2017 00:21, Chris Packham wrote:
On Tue, Sep 5, 2017 at 5:03 PM, Chris Packham wrote:
The Armada-38x has 1.8GHz and 2.0GHz variants. Add entries for these
variants to the sar_freq_tab.
Signed-off-by: Chris Packham
---
arch/arm/mach-mvebu/cpu.c | 16 +---
1
On Isn, 2017-09-25 at 11:23 +0200, Marek Vasut wrote:
> On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Enhance preloader header with both additional program length and
> > program
> > entry offset attributes, which offset is relative to the start of
On Isn, 2017-09-25 at 11:23 +0200, Marek Vasut wrote:
> On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Clock frequency info is required in U-boot.
> >
> > Signed-off-by: Tien Fong Chee
> I want a TB on Gen 5
>
What is TB?
> >
> > ---
> > arch/ar
On Isn, 2017-09-25 at 11:24 +0200, Marek Vasut wrote:
> On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Enable SPL loading U-boot from SDMMC to DDR and booting U-boot.
> This patch seems to be doing more than just one thing ...
>
I can split into two
Copied from Linux 4.13.
Commit log of 3e9b3112ec74 of Linux explains well why this header
is useful.
Signed-off-by: Masahiro Yamada
---
In order to use this header,
http://patchwork.ozlabs.org/patch/814471/
must be applied.
is highly dependent on
include/linux/bitfield.h | 106 +++
Hi Simon,
2017-09-25 11:15 GMT+09:00 Simon Glass :
> On 15 September 2017 at 23:10, Masahiro Yamada
> wrote:
>> Many drivers use dev_err, dev_info, etc. for logging. Currently,
>> we are relying on , but I guess the best home is
>> , taking into account that Linux defines them in
>> .
>>
>> For
Many drivers had started to use dev_err, dev_info, etc. for log
functions. Currently, we are relying on , but I
guess the best home is , taking into account that
Linux defines them in .
For now, I am leaving the ones in because lots of
Linux-originated code uses dev_*(), but the first argument i
Hi Stefano,
> -Original Message-
> From: Stefano Babic [mailto:sba...@denx.de]
> Sent: Monday, September 25, 2017 10:12 PM
> To: Peng Fan ; sba...@denx.de
> Cc: van.free...@gmail.com; u-boot@lists.denx.de; Fabio Estevam
>
> Subject: Re: [PATCH V4 11/12] imx: mx6sabresd: enable dm drivers
On Tue, Sep 26, 2017 at 07:10:21AM +0800, Bin Meng wrote:
> Hi Marek,
>
> On Tue, Sep 26, 2017 at 12:41 AM, Marek Vasut wrote:
> > The following changes since commit 1f6049e2501b5c35c61435dbc05ba96743202674:
> >
> > tools/mkimage: Make the path to the dtc binary that mkimage calls
> > configura
Hi Marek,
On Tue, Sep 26, 2017 at 12:41 AM, Marek Vasut wrote:
> The following changes since commit 1f6049e2501b5c35c61435dbc05ba96743202674:
>
> tools/mkimage: Make the path to the dtc binary that mkimage calls
> configurable (2017-09-24 07:33:03 -0400)
>
> are available in the git repository
For the internet historians,
On Thu, Sep 21, 2017 at 4:25 PM, Chris Packham wrote:
> On Wed, Sep 20, 2017 at 5:31 PM, Stefan Roese wrote:
>> Hi Chris,
>>
>> On 19.09.2017 20:58, Chris Packham wrote:
>>>
>>> When you did the port from Marvell's source did you script any of the
>>> tidy-up that yo
On Tue, Sep 5, 2017 at 5:03 PM, Chris Packham wrote:
> The Armada-38x has 1.8GHz and 2.0GHz variants. Add entries for these
> variants to the sar_freq_tab.
>
> Signed-off-by: Chris Packham
> ---
>
> arch/arm/mach-mvebu/cpu.c | 16 +---
> 1 file changed, 9 insertions(+), 7 deletions(-
Enable pinconf since it's now implemented and used in the DTs.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
configs/r8a7795_salvator-x_defconfig | 1 +
configs/r8a7795_ulcb_defconfig | 1 +
configs/r8a7796_salvator-x_defconfig | 1 +
configs/r8a7796_ulcb_defconfig | 1 +
4 f
Add pinconf support to the PFC driver, so that it can handle DT
props bias-disable, bias-pull-up, bias-pull-down, drive-strength
and power-source.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
drivers/pinctrl/renesas/pfc.c | 176 ++
1 file changed,
Signed-off-by: Rob Clark
---
Not sure if there is a way to inject a -l arg when test.py runs
sanbox somehow, to visually confirm the results? It is not really
possible to do manually since 'echo' command doesn't handle escape
sequences properly. At any rate, efi_console uses all the same
escape
I'll need some more of this, let's not just copy-pasta the
vidconsole_put_char() loop.
Named to match vidconsole_put_char() in case that is ever useful
outside of the tests.
Signed-off-by: Rob Clark
---
test/dm/video.c | 24
1 file changed, 12 insertions(+), 12 deletion
Hi Uri,
On Sun, Sep 24, 2017 at 3:00 AM, Uri Mashiach
wrote:
> This patch series adds support for CompuLab CL-SOM-iMX7, SBC-iMX7,
> SBC-IOT-iMX7
> and IOT-GATE-iMX7.
>
> CL-SOM-iMX7 is a miniature System-on-Module (SoM) based on
> NXP i.MX7 processor family.
>
> SBC-iMX7 is a single board comput
If we end up back in the root directory via a '..' directory entry, set
itr->is_root accordingly. Failing to do that gives spews like
"Invalid FAT entry" and being unable to access directory entries located
past the first cluster of the root directory.
Fixes: 8eafae209c35 ("fat/fs: convert to dire
The previous commit fixed a problem in FAT code where going back to the
root directory using '..' wouldn't work correctly on FAT12 or FAT16.
Add a test to exercise this case (which was once fixed in commit
18a10d46f26 "fat: handle paths that include ../" but reintroduced due to
the directory iterat
Currently we can only test FAT32 which is the default FAT version that
mkfs.vfat creates by default. Instead make it explicitly create either a
FAT16 or a FAT32 volume. This allows us to exercise more code, for
instance the root directory handling is done differently in FAT32 than
the older FATs.
The current code doesn't compute the group descriptor checksum correctly
for the filesystems that e2fsprogs 1.43.4 creates (they have
'Group descriptor size: 64' as reported by tune2fs). Extend the checksum
calculation to be done as ext4_group_desc_csum() does in Linux.
This fixes these errors in
Hi Peter,
On Mon, Sep 25, 2017 at 3:54 PM, Peter Robinson wrote:
> Hi Fabio,
>
> I'm seeing some issues with some of the i.MX6 devices with the latest
> stable release. It loads the SPL and then just seems to loop:
>
> U-Boot SPL 2017.09 (Sep 25 2017 - 18:42:10)
> Trying to boot from MMC1
>
> U-B
Hi Fabio,
I'm seeing some issues with some of the i.MX6 devices with the latest
stable release. It loads the SPL and then just seems to loop:
U-Boot SPL 2017.09 (Sep 25 2017 - 18:42:10)
Trying to boot from MMC1
U-Boot SPL 2017.09 (Sep 25 2017 - 18:42:10)
Trying to boot from MMC1
U-Boot SPL 2017
From: Fabio Estevam
CONFIG_SPL_PAD_TO is already defined inside "imx6_spl.h", so there
is no need to redefine it in the board config files.
Signed-off-by: Fabio Estevam
---
include/configs/apalis_imx6.h | 1 -
include/configs/colibri_imx6.h | 1 -
2 files changed, 2 deletions(-)
diff --git a
Hi Simon,
On 24 September 2017 at 19:14, Simon Glass wrote:
> Hi Sam,
>
> On 21 September 2017 at 16:51, Sam Protsenko
> wrote:
>> There is already existing function part_get_info_by_name().
>> But sometimes user is particularly interested in looking for only
>> specific partition type. This pa
On 09/18/2017 12:16 AM, Yangbo Lu wrote:
> PPA loading during SPL stage is not required for nornal
> SD boot scenario.
>
> Signed-off-by: Yangbo Lu
> ---
Applied to fsl-qoriq mater. Thanks.
York
___
U-Boot mailing list
U-Boot@lists.denx.de
https://li
On 09/14/2017 07:09 PM, Yangbo Lu wrote:
> Current u-boot disables IFC support for SD boot on all ls1043a
> boards. Actually IFC only conflicts with QSPI on ls1043a hardware.
> Only when QSPI is used, IFC should be disabled. Otherwise,
> the u-boot with ls1043aqds_sdcard_ifc_defconfig would not wor
On 09/18/2017 12:16 AM, Yangbo Lu wrote:
> PPA loading during SPL stage is not required for nornal
> SD boot scenario.
>
> Signed-off-by: Yangbo Lu
> ---
Applied to fsl-qoriq mater. Thanks.
York
___
U-Boot mailing list
U-Boot@lists.denx.de
https://li
On 09/14/2017 09:49 PM, Priyanka Jain wrote:
> As per current implementation, default value of board env is
> based on board filename i.e ls2080ardb.
>
> With distro support changes, this env is used to decide upon
> kernel dtb which is different for other SoCs (ls2088a, ls2081a)
> combination sup
On 08/29/2017 02:50 AM, Priyanka Jain wrote:
> For most of ls2080ardb use-cases, mc private DRAM block is required
> to be of 1.75GB.
> Henc set mcmemsize=0x7000 in default env
>
> Signed-off-by: Priyanka Jain
> ---
Applied to fsl-qoriq mater. Thanks.
York
On 09/04/2017 03:15 AM, Sriram Dash wrote:
> I2C code is put under CONFIG_SYS_I2C
>
> Signed-off-by: Sriram Dash
> ---
Applied to fsl-qoriq mater. Thanks.
York
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
On 09/04/2017 03:14 AM, Sriram Dash wrote:
> IFC code is put under CONFIG_FSL_IFC
>
> Signed-off-by: Sriram Dash
> ---
Applied to fsl-qoriq mater. Thanks.
York
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
On 08/31/2017 12:59 AM, Bharat Bhushan wrote:
> "pci: layerscape: Fixup device tree node for ls2088a" added
> support for LS208xA devices but fixing iommu-map property
> is missing. This patch adds support for fixing iommu-map.
>
> Signed-off-by: Bharat Bhushan
> Signed-off-by: Ioana Ciornei
> -
On 08/18/2017 02:47 AM, Santan Kumar wrote:
> As per updated board design, different QSPI flash
> is connected on boards, hence change QSPI flash type
> from Micron n25q512a device to spansion s25fs512s
> device in dts and config.
>
> Signed-off-by: Santan Kumar
> Signed-off-by: Yogesh Ga
On 08/18/2017 02:47 AM, Santan Kumar wrote:
> CONFIG_DISPLAY_BOARDINFO_LATE config is used to delay
> the prints of boardinfo late in cycle during uboot boot.
> This feature is not required in case of QSPI_BOOT.
>
> Signed-off-by: Santan Kumar
> Signed-off-by: Priyanka Jain
> ---
Applied to fsl
On 08/17/2017 10:24 PM, Ashish Kumar wrote:
> It is not necessary for every SoC to have 2 SATA controller.
> So put SATA1, SATA2 code under respective defines.
>
> Signed-off-by: Prabhakar Kushwaha
> Signed-off-by: Ashish Kumar
> ---
Applied to fsl-qoriq mater. Thanks.
York
___
On 09/14/2017 12:53 PM, York Sun wrote:
> Commit a8ecb39e accidentally reverted config macro CONFIG_ARCH_LS1021A
> to CONFIG_LS102XA.
>
> Signed-off-by: York Sun
> ---
Applied to fsl-qoriq mater.
York
___
U-Boot mailing list
U-Boot@lists.denx.de
https
On 09/25/2017 10:40 AM, Marek Vasut wrote:
On 09/25/2017 06:13 PM, Stephen Warren wrote:
Marek,
+CC Bin
I will drop the xhci patchset and hope to get a fixed one from him.
The latest branch content (0184c6fb34b4 "usb: dwc2: Align size of
invalidating dcache before starting DMA") passes the
On 09/25/2017 07:17 AM, Łukasz Majewski wrote:
> Hi York,
>
> If you don't mind, I would like to ask you for some help and
> clarification regarding your work.
>
>> Add jump_to_image_linux() for arm64. Add "noreturn" flag to
>> armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon
>
On 09/25/2017 06:13 PM, Stephen Warren wrote:
> Marek,
+CC Bin
I will drop the xhci patchset and hope to get a fixed one from him.
> The latest u-boot-usb master branch breaks the following unit tests for
> the sandbox target (as run by test/py):
>
> 8 failed
> ... test_ut[ut_dm_blk_usb]
> ...
On 09/15/2017 09:10 PM, Marek Vasut wrote:
> Add initial support for setting the vqmmc regulator. Since we do not
> support 1V8 modes, set the regulator to 3V3 and enable it.
>
> Signed-off-by: Marek Vasut
> Cc: Masahiro Yamada
> Cc: Jaehoon Chung
Anything ?! I don't see this in the PR ...
>
The following changes since commit 1f6049e2501b5c35c61435dbc05ba96743202674:
tools/mkimage: Make the path to the dtc binary that mkimage calls
configurable (2017-09-24 07:33:03 -0400)
are available in the git repository at:
git://git.denx.de/u-boot-usb.git master
for you to fetch changes up
Marek,
The latest u-boot-usb master branch breaks the following unit tests for
the sandbox target (as run by test/py):
8 failed
... test_ut[ut_dm_blk_usb]
... test_ut[ut_dm_usb_flash]
... test_ut[ut_dm_usb_keyb]
... test_ut[ut_dm_usb_multi]
... test_ut[ut_dm_usb_remove]
... test_ut[ut_dm_usb_t
On Fri, Sep 22, 2017 at 7:00 AM, David Müller (ELSOFT AG)
wrote:
> Hello
>
> Does the code below really work?
Hi Dave,
This patch does work to resolve the issue stated in the commit log
which was to fix failing to boot on a 4.11+ kernel which stems from
the fact that we have no reliable way to r
On 09/25/2017 04:17 PM, Łukasz Majewski wrote:
Nit -- Eanble in subject .
^^ Enable
Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Hi York,
If you don't mind, I would like to ask you for some help and
clarification regarding your work.
Add jump_to_image_linux() for arm64. Add "noreturn" flag to
armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon
boot.
I'm trying to do the same on imx6q board (armv7).
Hi Peng,
On 30/08/2017 08:14, Peng Fan wrote:
> Enable DM MMC/I2C/PMIC/GPIO/REGULATOR.
>
> Signed-off-by: Peng Fan
> Cc: Fabio Estevam
> Cc: Stefano Babic
> ---
>
> V2->V4: none
>
> board/freescale/mx6sabresd/mx6sabresd.c | 326
> +---
> configs/mx6sabresd_defco
On 30/08/2017 08:14, Peng Fan wrote:
> Typo fix: CONIFG->CONFIG
>
> Signed-off-by: Peng Fan
> Cc: Tom Rini
> ---
>
> V2: new
> V3: none
> V4: none
>
> scripts/Makefile.uncmd_spl | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/scripts/Makefile.uncmd_spl b/scripts/Make
On 24/09/2017 13:27, Max Krummenacher wrote:
> Hi
>
>
> I propose to drop my patches in favor of Fabio's solution.
>
>
Agree, I will merge them.
Regards,
Stefano
> Reviewed-by: Max Krummenacher
>
>
> Max
>
>
> *Von
Hi Fabio,
On 23/09/2017 17:11, Fabio Estevam wrote:
> On Sat, Sep 23, 2017 at 10:01 AM, Fabio Estevam wrote:
>> Hi Stefano,
>>
>> On Sat, Sep 23, 2017 at 5:43 AM, Stefano Babic wrote:
>>
>>> Max has already fixed apalis / colibri, see for example
>>> http://patchwork.ozlabs.org/patch/817053/. I
On Sep 25, 2017 3:11 AM, "Jagan Teki" wrote:
On Mon, Sep 18, 2017 at 7:13 AM, Adam Ford wrote:
> A few small additional items are needed to support DM_SPI and
> DM_SERIAL, so those were added to da850-evm-u-boot.dtsi
>
> Signed-off-by: Adam Ford
> ---
> V4: Re-sync with latest master
> V3: New
Am Montag, 25. September 2017, 19:49:01 CEST schrieb Andy Yan:
> Hi Heiko:
>
> On 2017年09月25日 18:29, Heiko Stübner wrote:
> > Hi Andy,
> >
> > Am Montag, 25. September 2017, 17:45:03 CEST schrieb Andy Yan:
> >> On 2017年09月22日 13:56, Heiko Stuebner wrote:
> >>> Am Freitag, 22. September 2017, 08:5
Hi Heiko:
On 2017年09月25日 18:29, Heiko Stübner wrote:
Hi Andy,
Am Montag, 25. September 2017, 17:45:03 CEST schrieb Andy Yan:
On 2017年09月22日 13:56, Heiko Stuebner wrote:
Am Freitag, 22. September 2017, 08:50:49 CEST schrieb Andy Yan:
Hi Heiko:
On 2017年09月22日 08:24, Andy Yan wrote:
Hi Heiko
On Sat, Sep 23, 2017 at 05:59:15PM +, Antony Antony wrote:
> Add initial DT for NanoPi NEO Plus2 by FriendlyARM
> - Allwinner quad core H5 Cortex A53 with an ARM Mali-450MP GPU
> - 1 GB DDR3 RAM
> - 8GB eMMC flash (Samsung KLM8G1WEPD-B031)
> - micro SD card slot
> - Gigabit Ethernet (external R
On Friday 18 August 2017 01:00 PM, Jaehoon Chung wrote:
> On 08/04/2017 06:34 PM, Suniel Mahesh wrote:
>> On Monday 17 July 2017 04:38 PM, Jaehoon Chung wrote:
>>> On 06/20/2017 01:53 AM, suni...@techveda.org wrote:
From: Suniel Mahesh
priv pointer should be freed before returning w
The content of Bank Address Register (BAR) is volatile. It is cleared
after power cycle or reset command (RESET F0h).
Some memories (like e.g. s25fl256s) use it to access memory larger than
0x100 (16 MiB).
The problem shows up when one:
1. Reads/writes/erases memory > 16 MiB
2. Calls "reset"
Hi Andy,
Am Montag, 25. September 2017, 17:45:03 CEST schrieb Andy Yan:
> On 2017年09月22日 13:56, Heiko Stuebner wrote:
> > Am Freitag, 22. September 2017, 08:50:49 CEST schrieb Andy Yan:
> >> Hi Heiko:
> >>
> >> On 2017年09月22日 08:24, Andy Yan wrote:
> >>> Hi Heiko:
> >>>
> >>> On 2017年09月21日 22:5
Hi Jagan,
On Wed, Sep 13, 2017 at 3:09 PM, Lukasz Majewski wrote:
The content of Bank Address Register (BAR) is volatile. It is cleared
after power cycle or reset command (RESET F0h).
Some memories (like e.g. s25fl256s) use it to access memory larger than
0x100 (16 MiB).
The problem show
On Mon, Jun 5, 2017 at 2:37 PM, Suresh Gupta wrote:
> In some of the QSPI controller version, there must be atleast
> 128bit data available in TX FIFO for any pop operation otherwise
> error bit will be set. The code will not make any behavior change
> for previous controller as the transfer data
On Fri, Sep 22, 2017 at 09:57:22PM +, Andre Przywara wrote:
> The sunxi-specific SPI load routine only knows how to load a legacy
> U-Boot image.
> Teach it how to handle FIT images as well, simply by providing the
> existing SPL FIT loader with the right loader routine to access the SPI
> NOR
On Mon, Sep 18, 2017 at 7:13 AM, Adam Ford wrote:
> A few small additional items are needed to support DM_SPI and
> DM_SERIAL, so those were added to da850-evm-u-boot.dtsi
>
> Signed-off-by: Adam Ford
> ---
> V4: Re-sync with latest master
> V3: New to series. I forgot to generate this before. T
On Wed, Sep 13, 2017 at 3:09 PM, Lukasz Majewski wrote:
> The content of Bank Address Register (BAR) is volatile. It is cleared
> after power cycle or reset command (RESET F0h).
>
> Some memories (like e.g. s25fl256s) use it to access memory larger than
> 0x100 (16 MiB).
>
> The problem shows
On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Add support to memory allocation in SPL for preparation to enable FAT
> in SPL. Memory allocation is needed by FAT to work properly.
>
> Signed-off-by: Tien Fong Chee
Gen 5 does have malloc support in SPL, so wh
On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Clock frequency info is required in U-boot.
>
> Signed-off-by: Tien Fong Chee
I want a TB on Gen 5
> ---
> arch/arm/mach-socfpga/board.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm
On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Enable SPL loading U-boot from SDMMC to DDR and booting U-boot.
This patch seems to be doing more than just one thing ...
> Signed-off-by: Tien Fong Chee
> ---
> arch/arm/mach-socfpga/spl.c | 55 +
On 09/25/2017 11:05 AM, David Müller (ELSOFT AG) wrote:
> Marek Vasut wrote:
>
>> On 09/22/2017 04:00 PM, David Müller (ELSOFT AG) wrote:
>>> On my custom MX6Q board, the code hangs on the read of the
>>> "PCIE_PL_PFLR". Please note that this code sequence is not entered
>>> the first time after
On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Enable generic filesystem interface drivers(fs.c and fat/) build
> for SPL. This would allow generic filesystem being used in SPL.
>
> Signed-off-by: Tien Fong Chee
+CC Simon, I'd like a RB on this one.
> ---
>
On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> This patch is for enabling the DDR support on Arria 10.
>
> Signed-off-by: Tien Fong Chee
> ---
> drivers/ddr/altera/Makefile | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/ddr/altera/Makefile
On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Enhance preloader header with both additional program length and program
> entry offset attributes, which offset is relative to the start of program
> header.
>
> Signed-off-by: Tien Fong Chee
> ---
> arch/arm/m
On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Existing FPGA program write is always assume RBF data >= 32 bytes, so
> any rbf data less than 32 bytes writing to FPGA would be failed.
> This patch enhances the FPGA program write to support rbf data with
> size
On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Add DDR driver suppport for Arria 10.
>
> Signed-off-by: Tien Fong Chee
> ---
> arch/arm/mach-socfpga/include/mach/sdram.h | 2 +
> arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 103 ++-
> drive
On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Add function for both multiple DRAM bank and single DRAM bank size
> initialization. This common functionality could be used by every single
> SOCFPGA board.
>
> Signed-off-by: Tien Fong Chee
I'd like TB on Gen5
On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> These drivers handle FPGA program operation from flash loading
> RBF to memory and then to program FPGA.
>
> Signed-off-by: Tien Fong Chee
Did you run checkpatch on this before submitting ? I presume no ...
> -
On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Current sdram driver is only applied to gen5 device, hence it is better
> to rename sdram driver to more specific name which is related to gen5
> device.
>
> Signed-off-by: Tien Fong Chee
> ---
> arch/arm/mach-s
On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Add compatible strings for Intel Arria 10 SoCFPGA device.
>
> Signed-off-by: Tien Fong Chee
Applied, thanks
> ---
> include/fdtdec.h | 2 ++
> lib/fdtdec.c | 2 ++
> 2 files changed, 4 insertions(+)
>
> d
On 09/25/2017 10:39 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> This patch adds description on properties about location of FPGA RBFs are
> stored, type and functionality of RBF used to configure FPGA.
>
> Signed-off-by: Tien Fong Chee
> ---
> doc/device-tree-bindings/fpga/a
On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Add code necessary into the FPGA driver framework in U-Boot
> so it can be used via the 'fpga' command for programing Arria 10
> SoCFPGA.
>
> Signed-off-by: Tien Fong Chee
> ---
[...]
> +#if defined(CONFIG_CMD_
On 09/25/2017 10:39 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> This patch adds description on properties about location of FPGA RBFs are
> stored, type and functionality of RBF used to configure FPGA.
>
> Signed-off-by: Tien Fong Chee
Why does this patch have different tags
On 09/25/2017 10:39 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> This DT binding doc is porting from Linux DT binding doc.
> commit 1adcbea4201a6852362aa5ece573f1f169b28113
>
> Add a device tree bindings document for the SoCFPGA Arria10
> FPGA Manager driver.
>
> Signed-off-by
Hi Heiko:
On 2017年09月22日 13:56, Heiko Stuebner wrote:
Am Freitag, 22. September 2017, 08:50:49 CEST schrieb Andy Yan:
Hi Heiko:
On 2017年09月22日 08:24, Andy Yan wrote:
Hi Heiko:
On 2017年09月21日 22:55, Heiko Stübner wrote:
Hi Andy,
Am Donnerstag, 21. September 2017, 22:03:32 CEST schrieb An
From: Tien Fong Chee
This DT binding doc is porting from Linux DT binding doc.
commit 1adcbea4201a6852362aa5ece573f1f169b28113
Add a device tree bindings document for the SoCFPGA Arria10
FPGA Manager driver.
Signed-off-by: Alan Tull
Acked-by: Rob Herring
Acked-By: Moritz Fischer
Signed-off-b
Marek Vasut wrote:
> On 09/22/2017 04:00 PM, David Müller (ELSOFT AG) wrote:
>> On my custom MX6Q board, the code hangs on the read of the
>> "PCIE_PL_PFLR". Please note that this code sequence is not entered
>> the first time after a power up; I have to execute a U-Boot reset
>> to actually trig
The intent of this patch is to create the initial files necessary to
support the nyan-kitty device by copying nyan-big files and renaming all
the nyan-big references and tags to be nyan-kitty.
This will make a u-boot that will act exactly like the nyan-big build,
except will say "nyan-kitty" where
Andy,
Excellent news.
Looks like Heiko and I figured out what breaks the series last week (i.e. the
SPL corrupts
the TPL’s stack—so my chaining will break things).
I’ll resubmit without the chained returns later and then we can have a final
test tomorrow.
Regards,
Philipp.
> On 25 Sep 2017, a
On Mon, Sep 25, 2017 at 2:11 PM, Łukasz Majewski wrote:
> Hi Jagan,
>
>> Hi Tom,
>>
>> Please pull this PR.
>
>
> Would you find some time and look into following patch:
>
> http://patchwork.ozlabs.org/patch/813266/
Of-course, will comment on respective patch itself.
thanks!
--
Jagan Teki
Free
From: Tien Fong Chee
Enable SPL loading U-boot from SDMMC to DDR and booting U-boot.
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/spl.c | 55 +
common/spl/spl_mmc.c | 2 +-
configs/socfpga_arria10_defconfig | 57 +++
From: Tien Fong Chee
SoC FPGA info is required in both SPL and U-boot.
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/board.c| 3 +++
arch/arm/mach-socfpga/misc_arria10.c | 5 -
arch/arm/mach-socfpga/spl.c | 6 ++
3 files changed, 9 insertions(+), 5 deletions(
From: Tien Fong Chee
Enhance preloader header with both additional program length and program
entry offset attributes, which offset is relative to the start of program
header.
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/include/mach/boot0.h | 11 +--
1 file changed, 9 inser
Hi Jagan,
Hi Tom,
Please pull this PR.
Would you find some time and look into following patch:
http://patchwork.ozlabs.org/patch/813266/
Thanks in advance,
Łukasz
thanks!
Jagan.
The following changes since commit 1f6049e2501b5c35c61435dbc05ba96743202674:
tools/mkimage: Make the path
From: Tien Fong Chee
This patch enables DDR Kconfig support for Arria 10.
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/Kconfig | 1 +
drivers/ddr/altera/Kconfig| 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-soc
From: Tien Fong Chee
Enable generic filesystem interface drivers(fs.c and fat/) build
for SPL. This would allow generic filesystem being used in SPL.
Signed-off-by: Tien Fong Chee
---
common/spl/Kconfig | 8
doc/README.SPL | 1 +
fs/Makefile| 1 +
3 files changed, 10 inser
From: Tien Fong Chee
fpga-mgr node is required in SPL, because SPL needs information
from the node to configure FPGA in Arria 10.
Signed-off-by: Tien Fong Chee
---
arch/arm/dts/socfpga_arria10.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/socfpga_arria10.dtsi
b/arch/ar
From: Tien Fong Chee
Clock frequency info is required in U-boot.
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/board.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 965f9dc..a00f63b 100644
--- a/arch/arm/
Hi Philipp, Heiko:
I finally got the upstream u-boot run on a rk3188 board which can be
attached by DS5 debugger,
if you have some registers info want to check, please let me know.
On 2017年09月21日 18:44, Heiko Stübner wrote:
Am Donnerstag, 21. September 2017, 12:25:17 CEST schrieb Dr. Phili
From: Tien Fong Chee
These drivers handle FPGA program operation from flash loading
RBF to memory and then to program FPGA.
Signed-off-by: Tien Fong Chee
---
.../include/mach/fpga_manager_arria10.h| 27 ++
drivers/fpga/socfpga_arria10.c | 391 ++
1 - 100 of 131 matches
Mail list logo
