The Allwinner H6 SoC has a register to set the PIO banks' voltage. When
it mismatches the real voltage supplied to the VCC to the PIO supply,
the PIO will work improperly.
The PIO controller also has a register that contains the status of each
VCC rail of the PIO supplies, and it has the same
When using fdt_fixup_mtdparts() offset and length cell sizes
are limited to 4 bytes (1 cell). However if the mtd device is
bigger then 4GiB, then #address-cells and #size-cells are
8 bytes (2 cells) [1].
This patch read #size-cells and uses either fdt32_t or
fdt64_t cell size. The default is
Ley Foon Tan schrieb am Mi., 24. Apr. 2019, 07:21:
> A mailbox command contains 1-u32 header + arguments. The "len" variable
> only contains the length of the arguments, but not the 1-u32 header.
> Include the length of header when checking the ring buffer space to
> prevent off-by-one error.
>
A mailbox command contains 1-u32 header + arguments. The "len" variable
only contains the length of the arguments, but not the 1-u32 header.
Include the length of header when checking the ring buffer space to
prevent off-by-one error.
Signed-off-by: Ley Foon Tan
Signed-off-by: Chee Hong Ang
---
> Subject: [PATCH v3 7/9] pico-imx7d: Add device tree for pico-imx7d
>
> Copy device tree files from Linux directly.
Please describe which specific commit from Linux kernel upstream
Regards,
Peng.
>
> Signed-off-by: Jun Nie
> ---
> arch/arm/dts/Makefile | 1 +
>
> Subject: [PATCH v3 5/9] pico-imx7d: Reserve region of memory to OPTEE
>
> Subtracts CONFIG_OPTEE_TZDRAM_SIZE from the available DRAM size so
> that the OPTEE memory is not override during u-boot relocation.
>
> Note the OPTEE boot process will itself subtract the DRAM region it lives in
>
> Subject: [PATCH v3 4/9] pico-imx7d: Correct uart clock root
>
> Correct uart clock root ID. Incorrect ID may result the clock is gated because
> rate value 0 is returned in
> imx_get_uartclk()
Yes. hardcoding to UART1_ROOT_CLK in imx_get_uartclk is not good.
But actually init_clk_uart
Hi Jun
> Subject: [PATCH v3 3/9] imx: mx7: Add empty arch_cpu_init if skipped
>
> Add empty arch_cpu_init if low level init is skipped. So that it does not
> break
> spl compile though spl is not needed in the skipped case actually.
>
> Signed-off-by: Jun Nie
> ---
>
Add Documentation of BL33 usage case. U-boot is in
non-secure world in this case.
Signed-off-by: Jun Nie
---
board/technexion/pico-imx7d/README.pico-imx7d_BL33 | 44 ++
1 file changed, 44 insertions(+)
create mode 100644 board/technexion/pico-imx7d/README.pico-imx7d_BL33
Add default configuration to run u-boot as BL33 in the boot flow case
of ATF(ARM Trusted Firmware) -> OPTEE -> U-boot.
Signed-off-by: Jun Nie
---
configs/pico-imx7d_bl33_defconfig | 63 +++
1 file changed, 63 insertions(+)
create mode 100644
Correct uart clock root ID. Incorrect ID may result the
clock is gated because rate value 0 is returned in
imx_get_uartclk()
Signed-off-by: Jun Nie
---
arch/arm/include/asm/arch-mx7/clock.h | 18 ++
arch/arm/mach-imx/Kconfig | 7 +++
Add boot option to boot from fitimage to support verified boot.
The boot script plain text file should be packed into fit blob as
image with name of bootscr.
Signed-off-by: Jun Nie
---
include/configs/pico-imx7d.h | 38 +++---
1 file changed, 35 insertions(+), 3
For U-Boot we allow a GPIO to be specified to enable the codec. Add this
to the relevant binding files.
Signed-off-by: Simon Glass
---
doc/device-tree-bindings/sound/intel-hda.txt | 1 +
doc/device-tree-bindings/sound/nvidia,tegra-audio-max98090.txt | 1 +
Add empty arch_cpu_init if low level init is skipped. So that
it does not break spl compile though spl is not needed in the
skipped case actually.
Signed-off-by: Jun Nie
---
arch/arm/mach-imx/mx7/soc.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-imx/mx7/soc.c
This file was missed when adding the sound driver to U-Boot. Bring it in
from Linux 5.0.
Signed-off-by: Simon Glass
---
.../sound/nvidia,tegra-audio-max98090.txt | 53 +++
1 file changed, 53 insertions(+)
create mode 100644
Subtracts CONFIG_OPTEE_TZDRAM_SIZE from the available DRAM size so that
the OPTEE memory is not override during u-boot relocation.
Note the OPTEE boot process will itself subtract the DRAM region it lives
in from the memory map passed to Linux.
Signed-off-by: Jun Nie
---
Add configuration to boot U-boot as BL33 case. The boot flow
is ATF -> OPTEE -> U-boot.
Changes vs V2:
- Revise fix to UART clock ID.
- Add documentation of build and test for BL33 usage case.
- Add device tree to store public key for FIT image verfication usage.
- Add revert patch to LCD
Copy device tree files from Linux directly.
Signed-off-by: Jun Nie
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/imx7d-pico-pi.dts | 93 +++
arch/arm/dts/imx7d-pico.dtsi | 585 +
3 files changed, 679 insertions(+)
create mode 100644
This file was missed when adding the sound driver to U-Boot. Bring it in
from Linux 5.0.
Signed-off-by: Simon Glass
---
doc/device-tree-bindings/sound/snow.txt | 31 +
1 file changed, 31 insertions(+)
create mode 100644 doc/device-tree-bindings/sound/snow.txt
diff
Share configs in mx7 to skip low level init if we are in the case where
OPTEE is loaded already (maybe by ARM Trusted Firmware) and that most of
the low level initialization is already done and that we may/should skip
it doing them here.
Fix the definition detection with size detection to decide
On Wed, 3 Apr 2019 at 06:25, Urja Rannikko wrote:
>
> There were 3 copies of the same sequence, make it into a function.
>
> Signed-off-by: Urja Rannikko
> ---
> disk/part_efi.c | 73 +++--
> 1 file changed, 34 insertions(+), 39 deletions(-)
>
On Wed, 3 Apr 2019 at 21:52, David Wu wrote:
>
> Some files have the redundant spaces, remove them.
>
> Signed-off-by: David Wu
> ---
>
> drivers/pinctrl/rockchip/pinctrl-rk3036.c | 12 ++--
> drivers/pinctrl/rockchip/pinctrl-rk3188.c | 12 ++--
>
This reverts commit 9e3c0174da842dd88f5feaffbf843ba332233897.
---
board/technexion/pico-imx7d/pico-imx7d.c | 55
configs/pico-hobbit-imx7d_defconfig | 1 -
configs/pico-imx7d_defconfig | 1 -
configs/pico-pi-imx7d_defconfig | 1 -
Hi,
On Wed, 3 Apr 2019 at 06:21, Urja Rannikko wrote:
>
> Based on snooping around the linux kernel rk8xx driver, and
> tested to work on the ASUS C201.
>
> Signed-off-by: Urja Rannikko
> ---
> This is really handy to be able to poweroff (without pressing power button
> for a long time) the
Hi Jon,
On Wed, 3 Apr 2019 at 03:05, Jon Hunter wrote:
>
>
> On 01/04/2019 21:38, Simon Glass wrote:
> > Add a driver for the audio hub. This is modelled as a misc device which
> > supports writing audio data from I2S.
> >
> > Signed-off-by: Simon Glass
> > ---
> >
> > Changes in v2:
> > - Fix
Hi Jon,
On Wed, 3 Apr 2019 at 03:15, Jon Hunter wrote:
>
>
> On 01/04/2019 21:38, Simon Glass wrote:
> > Add a sound driver for tegra devices. This connects the audio hub, I2S
> > controller and audio codec to allow sound output.
> >
> > Signed-off-by: Simon Glass
> > ---
> >
> > Changes in v2:
On Mon, 1 Apr 2019 at 21:39, Marek Vasut wrote:
>
> The current 4-minute data transfer timeout is misleading and broken.
> Instead of such a long wait, calculate the timeout duration based on
> the length of the data transfer. The current formula is the transfer
> length in bits, divided by a
Hi Urja,
On Wed, 3 Apr 2019 at 06:25, Urja Rannikko wrote:
>
> Some ChromeOS devices (atleast veyron speedy) have the first 8MiB of
> the eMMC write protected and equipped with a dummy 'IGNOREME' GPT
> header - instead of spewing error messages about it, just silently
> try the backup GPT.
>
>
On Wed, 3 Apr 2019 at 03:34, Urja Rannikko wrote:
>
> Updates jerry, mickey, minnie and speedy defconfigs to:
> - fit the SPL in 32k
> - boot from SPI (only)
> - remove gadget support (these have no OTG port)
>
> Signed-off-by: Urja Rannikko
> ---
> configs/chromebit_mickey_defconfig | 26
On Sun, 7 Apr 2019 at 09:58, Heinrich Schuchardt wrote:
>
> If CONFIG_UNIT_TEST is enabled we should enable the individual tests by
> default to ensure good test coverage.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> Tests ok on Travis CI:
>
On Wed, 3 Apr 2019 at 03:34, Urja Rannikko wrote:
>
> Affects rk3288 veyrons and rk3036, this was mostly done by
> moveconfig.py.
>
> Signed-off-by: Urja Rannikko
> ---
> configs/chromebit_mickey_defconfig | 1 +
> configs/chromebook_jerry_defconfig | 1 +
>
Hi Matti,
On Wed, 27 Mar 2019 at 06:40, Matti Vaittinen
wrote:
>
> Add regulator driver for ROHM BD71837 PMIC. BD71837 contains
> 8 bucks and 7 LDOS. Voltages for bucks 1-4 can be adjusted
> when regulators are enabled. For other bucks and LDOs we may
> have over- or undershooting if voltage is
Hi Matti,
On Mon, 8 Apr 2019 at 04:28, Matti Vaittinen
wrote:
>
> https://source.codeaurora.org/external/imx/uboot-imx
>
> cherry picked, styled and merged commits:
> - MLK-18387 pmic: Add pmic driver for BD71837: e9a3bec2e95a
> - MLK-18590 pmic: bd71837: Change to use new fdt API: acdc5c297a96
On Mon, 1 Apr 2019 at 14:01, Simon Goldschmidt
wrote:
>
> If the malloc range passed to mem_malloc_init() is at the end of address
> range and 'start + size' overflows to 0, following allocations fail as
> mem_malloc_end is zero (which looks like uninitialized).
>
> Fix this by subtracting 1 of
On Mon, 1 Apr 2019 at 17:05, Trent Piepho wrote:
>
> This is a configuration option specific to the tegra controller.
>
> Doing it this way makes it show up directly under the tegra controller
> option, indented one level, as "Disable external clock loopback".
>
> The way it is now, it shows up
On Mon, 1 Apr 2019 at 14:01, Simon Goldschmidt
wrote:
>
> Convert debug output from '%#lx' to '0x%lx' to be compatible with tiny
> printf used in SPL.
>
> Signed-off-by: Simon Goldschmidt
> ---
>
> Changes in v4:
> - dumped clearing BSS before SPL board_init_f, only real bugfixes remain
>
>
Hi Fabio
> -Original Message-
> From: Fabio Estevam [mailto:feste...@gmail.com]
> Sent: 2019年4月24日 10:01
> To: Peng Fan ; Abel Vesa
> Cc: Stefano Babic ; Lukasz Majewski ;
> Michael Trimarchi ; dl-uboot-imx
> ; Jagan Teki ; Marcel
> Ziswiler ; U-Boot-Denx
> ; Adam Ford ; Ye Li
> ; Otavio
Hi Bin
Bin Meng 於 2019年4月23日 週二 下午8:19寫道：
>
> On Tue, Apr 23, 2019 at 8:14 PM Bin Meng wrote:
> >
> > Hi Rick,
> >
> > On Tue, Apr 23, 2019 at 1:47 PM Andes wrote:
> > >
> > > From: Rick Chen
> > >
> >
> > typo in the commit title: seletable -> selectable
OK
> >
> > > In smp flow this two
Hi Peng and Abel,
On Mon, Apr 22, 2019 at 11:00 PM Peng Fan wrote:
> Honestly I am not familiar with imx_usb, we use mfgtool previously and not
> uuu tool.
Is the UUU tool capable of loading SPL + u-boot-dtb.img generated from
mainline U-Boot for mx6sabresd?
Thanks
Hi Bin
Bin Meng 於 2019年4月23日 週二 下午8:14寫道：
>
> Hi Rick,
>
> On Tue, Apr 23, 2019 at 1:47 PM Andes wrote:
> >
> > From: Rick Chen
> >
>
> nits in the commit title: boot->booting
OK
>
> > When AE350 was booting from ram, use OF_PRIOR_STAGE instead
> > of OF_PRIOR_STAGE.
>
> This should be
Hi Bin
Bin Meng 於 2019年4月23日 週二 下午8:14寫道：
>
> Hi Rick,
>
> On Tue, Apr 23, 2019 at 1:47 PM Andes wrote:
> >
> > From: Rick Chen
> >
>
> commit title should read: prior_stage_fdt_address should only be used
> when OF_PRIOR_STAGE is enabled
OK
>
> > This patch will fix prior_stage_fdt_address
Hi Bin
Bin Meng 於 2019年4月23日 週二 下午8:14寫道：
>
> Hi Rick,
>
> On Tue, Apr 23, 2019 at 1:47 PM Andes wrote:
> >
> > From: Rick Chen
>
> nits in the commit title: boot->booting
OK
>
> >
> > Add two defconfig to support AE350 SMP boot from flash
>
> boot->bootings
OK
>
> > by disable
> -Original Message-
> From: Lukasz Majewski [mailto:lu...@denx.de]
> Sent: 2019年4月23日 22:45
> To: Stefano Babic ; u-boot@lists.denx.de; Fabio Estevam
> ; Fabio Estevam ;
> dl-uboot-imx ; Jagan Teki
> ; Adam Ford
> Cc: Lukasz Majewski ; Bin Meng ;
> Simon Glass
> Subject: [PATCH v2]
Hi Lukas
Auer, Lukas 於 2019年4月24日 週三 上午3:58寫道：
>
> Hi Rick,
>
> On Tue, 2019-04-23 at 13:42 +0800, Andes wrote:
> > From: Rick Chen
> >
> > In current RISC-V SMP flow, AE350 will encounter the the write
> > failure problem since hart_lottery and available_harts_lock was
> > not in ram address
Hello Francois, Jan, Christian, and all
Sorry for the late reply, I was waiting for the administrator of the Boot
Architecture mailing list to accept my subscription request, but it seems it
will take a bit more time. I will send this reply and hope it will not be
blocked. I have also added
When booting in BL33 mode i.e. with u-boot loaded by OP-TEE we get the
following print-out.
Board: WARP7 in secure mode OPTEE DRAM 0xa000-0xa000
This is incorrect the right range is 0x9e00-0xa000. This patch
fixes the defines on the warp7_bl33_defconfig file to tidy up the
Commit c7b3a7ee5351 ("optee: adjust dependencies and default values for
dram") wants to skip low-level init of i.MX7 hardware in the case where
OP-TEE has already run and u-boot is being run as BL33 in normal world.
Currently we check for both #ifdef CONFIG_OPTEE_TZDRAM_SIZE and #ifndef
Commit 32ce6179fb99 ("optee: Add lib entries for sharing OPTEE code across
ports") adds code into lib/optee but neglects to update MAINTAINERS to make
me buggable for questions and maintenance.
Signed-off-by: Bryan O'Donoghue
Suggested-by: Jens Wiklander
---
MAINTAINERS | 5 +
1 file
Rober P Day rightly pointed out that some odd OP-TEE specific defines were
appearing in his defconfig, despite not having CONFIG_OPTEE=y set in his
defconfig.
Looking into this with a small bit of restructure we can fix this corner
case.
- Make sure OP-TEE CONFIG options only appear when you are
Commit c7b3a7ee5351 ("optee: adjust dependencies and default values for
dram") makes the TZDRAM defines for OPTEE show up for all configs as a
side-effect. While not harmful its not what we really want.
This patch makes the following defines contingent on CONFIG_OPTEE=y
CONFIG_OPTEE_TZDRAM_BASE
On 4/24/19 1:36 AM, Atish Patra wrote:
> This patch adds booti support for RISC-V Linux kernel. The existing
> bootm method will also continue to work as it is.
>
> It depends on the following kernel patch which adds the header to the
> flat Image.
>
>
This patch adds booti support for RISC-V Linux kernel. The existing
bootm method will also continue to work as it is.
It depends on the following kernel patch which adds the header to the
flat Image.
https://patchwork.kernel.org/patch/10913869/
Tested on HiFive Unleashed and QEMU.
Currently,
On Tue, Apr 23, 2019 at 04:55:00PM -0500, Dinh Nguyen wrote:
> Hi,
>
> This is V4 of the series to add a UCLASS_CACHE dm driver to handling
> the configuration of cache settings. Place this new driver under
> /drivers/cache. In this initial revision, the driver is only configuring
> what I think
Add a PL310 cache controller driver that is usually found on
ARMv7(32-bit) devices. The driver configures the cache settings that can
be found in the device tree files.
This initial revision only configures basic settings(data & instruction
prefetch, shared-override, data & tag latency). I
Select the PL310 UCLASS_CACHE driver for SoCFPGA.
Reviewed-by: Marek Vasut
Reviewed-by: Simon Glass
Signed-off-by: Dinh Nguyen
---
arch/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f58f8fb235..f5132d8174 100644
---
The cache UCLASS will be used for configure settings that can be found
in a CPU's L2 cache controller.
Add a uclass and a test for cache.
Reviewed-by: Simon Glass
Signed-off-by: Dinh Nguyen
---
v5: fix compile error for sandbox_cache.c
v4: re-order includes and add Reviewed-by:
v3: Add
Find the UCLASS_CACHE driver to configure the cache controller's
settings.
Reviewed-by: Marek Vasut
Reviewed-by: Simon Glass
Signed-off-by: Dinh Nguyen
---
arch/arm/mach-socfpga/misc.c | 16 +++-
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git
Add the PL310 macros for latency control setup, read and write bits.
Reviewed-by: Marek Vasut
Reviewed-by: Simon Glass
Signed-off-by: Dinh Nguyen
---
arch/arm/include/asm/pl310.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h
Linux commit 8ecd7f5970c5 ("ARM: 8483/1: Documentation: l2c: Rename
l2cc to l2c2x0")
Linux docs:
Documentation/devicetree/bindings/arm/l2c2x0.txt
Copied from Linux kernel v5.0.
"The documentation in the l2cc.txt is specific to the L2 cache
controllers L2C210/L2C220/L2C310 (also known as
Hi,
This is V4 of the series to add a UCLASS_CACHE dm driver to handling
the configuration of cache settings. Place this new driver under
/drivers/cache. In this initial revision, the driver is only configuring
what I think are essential cache settings. The more comprehensive cache
settings can
On 4/23/19 10:51 PM, Simon Goldschmidt wrote:
>
>
> Marek Vasut mailto:ma...@denx.de>> schrieb am Di., 23.
> Apr. 2019, 22:43:
>
> On 4/23/19 9:36 PM, Simon Goldschmidt wrote:
> > This series cleans up the include/configs/socfpga_common.h file a bit.
> >
> > It removes some
On 4/22/19 12:48 PM, Tom Rini wrote:
> On Mon, Apr 01, 2019 at 05:32:17PM -0500, Dinh Nguyen wrote:
>
>> The cache UCLASS will be used for configure settings that can be found
>> in a CPU's L2 cache controller.
>>
>> Add a uclass and a test for cache.
>>
>> Reviewed-by: Simon Glass
>>
Marek Vasut schrieb am Di., 23. Apr. 2019, 22:43:
> On 4/23/19 9:36 PM, Simon Goldschmidt wrote:
> > This series cleans up the include/configs/socfpga_common.h file a bit.
> >
> > It removes some defines that are used nowhere and cleans up some
> > leftovers after various subsystems have been
On 4/23/19 9:36 PM, Simon Goldschmidt wrote:
> This series cleans up the include/configs/socfpga_common.h file a bit.
>
> It removes some defines that are used nowhere and cleans up some
> leftovers after various subsystems have been converted to use DM.
>
> Changes in v4:
> - fix DM_I2C case:
Hi Simon,
> The current device model enabled eeprom code only works if
> CONFIG_SYS_I2C_EEPROM_BUS is set.
>
> This patch makes it work without that define so that the bus
> number passed to 'eeprom_init' is used.
Reviewed-by: Lukasz Majewski
>
> Signed-off-by: Simon Goldschmidt
>
Hi Rick,
On Tue, 2019-04-23 at 13:42 +0800, Andes wrote:
> From: Rick Chen
>
> In current RISC-V SMP flow, AE350 will encounter the the write
> failure problem since hart_lottery and available_harts_lock was
> not in ram address but in flash address when booing from flash.
>
> This patch can
Remove outdated macros and comments (not used any more, outdated due to
DM conversion) from socfpga_common.h.
Signed-off-by: Simon Goldschmidt
---
Changes in v4: None
Changes in v3:
- changed commit message: s/defines/macros and comments/
Changes in v2:
- remove even more outdated things
Remove outdated defines (not used any more, outdated due to DM
conversion) from various socfpga files in include/config.
Signed-off-by: Simon Goldschmidt
Acked-by: Marek Vasut
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- added (this) patch with further cleanups to the socfpga
socfpga_common.h defines CONFIG_SYS_BOOTMAPSZ to 64 MiB.
Since having this define overrides the 'bootm_size' env variable for
the whole socfpga platform, let's remove this define from socfpga_common.h
and instead rely on the 'bootm_size' env variable (which is initialized
to 160 MiB in the same
All socfpga boards except for vining_fpga use DM_I2C. Enable
DM_I2C for this board and set the EEPROM defines via Kconfig
(enabling CONFIG_I2C_EEPROM from MISC).
Signed-off-by: Simon Goldschmidt
---
Changes in v4:
- fix DM_I2C case: don't call i2c_set_bus_num() since this is
done in
This series cleans up the include/configs/socfpga_common.h file a bit.
It removes some defines that are used nowhere and cleans up some
leftovers after various subsystems have been converted to use DM.
Changes in v4:
- fix DM_I2C case: don't call i2c_set_bus_num() since this is
done in
This reverts commit 65a97e7fcf54feb7c4ebe1aee8a572830af4cf51.
The 'eeprom' command has been converted to work with DM_I2C in a patch
submitted around the same time as this commit:
commit 0c07a9b4078d ("eeprom: Add device model based I2C support to eeprom
command")
Signed-off-by: Simon
The current device model enabled eeprom code only works if
CONFIG_SYS_I2C_EEPROM_BUS is set.
This patch makes it work without that define so that the bus
number passed to 'eeprom_init' is used.
Signed-off-by: Simon Goldschmidt
Reviewed-by: Heiko Schocher
---
Changes in v3:
- use eeprom_init()
Hi, I am using device based on Atheros AR9344.
When U-Boot initialize net device I get error
mdio_register: non unique device name 'gmac0'
dm tree command shows that eth_ag7xxx is not probed.
ag7xxx_eth_probe -> ag7xxx_mac_probe -> ag933x_phy_setup ->
ag933x_phy_setup_reset_set ->
Cc: U-Boot Mailing List
The following changes since commit 6c5f8dd540d7a8eff244d4c27a09451ca12c8d20:
Merge branch 'master' of git://git.denx.de/u-boot-usb (2019-04-21
19:00:04 -0400)
are available in the Git repository at:
git://git.denx.de/u-boot-efi.git tags/efi-2019-07-rc1-3
for you
The usage of socfpga_sdram_apply_static_cfg() seems rather dubious and
is confirmed to lead to a rare system hang when enabling bridges. This
patch removes the socfpga_sdram_apply_static_cfg() altogether, because
it's use seems unjustified and problematic.
The socfpga_sdram_apply_static_cfg()
This commit is necessary to be able to re-use the pinctrl code in early
SPL to properly configure pins.
The problem is that those "static" structures (without explicit
initialization) are placed in the SDRAM area, which corresponds to
u-boot proper (not even SPL).
Hence, when one wants to
> This fixes RK3288 SPL hanging or hitting this assert:
> drivers/core/ofnode.c:183: ofnode_first_subnode: Assertion
> `ofnode_valid(node)' failed.
>
> Signed-off-by: Urja Rannikko
> Reviewed-by: Simon Glass
> Reviewed-by: Philipp Tomsich
> ---
> drivers/pinctrl/pinctrl-uclass.c | 3 +++
> 1
> This failed and caused a boot failure on c201, and afaik
> the pins should be setup by the new pinctrl driver.
>
> Signed-off-by: Urja Rannikko
> Reviewed-by: Simon Glass
> Reviewed-by: Philipp Tomsich
> ---
> arch/arm/mach-rockchip/rk3288-board.c | 12
> 1 file changed, 12
> TIMER7_BASE is no used by source code now, remove it.
>
> Signed-off-by: Kever Yang
> Reviewed-by: Philipp Tomsich
> ---
>
> arch/arm/include/asm/arch-rockchip/hardware.h | 2 --
> 1 file changed, 2 deletions(-)
>
Applied to u-boot-rockchip, thanks!
> Even though the priv-structure and the claim-bus function contain
> logic for 16bit frames and for unidirectional transfer modes, neither
> of these is used anywhere in the driver.
>
> This removes the unused (as in "has no effect") logic and fields.
>
> Signed-off-by: Philipp Tomsich
> ---
>
> The maximum transfer length (in a single transaction) for the Rockchip
> SPI controller is 64Kframes (i.e. 0x1 frames) of 8bit or 16bit
> frames and is encoded as (num_frames - 1) in CTRLR1. The existing
> code subtracted the "minus 1" twice for a maximum transfer length of
> 0x (64K -
> To support unaligned output buffers (i.e. 'in' in the terminology of
> the SPI framework), this change splits each 16bit FIFO element after
> reading and writes them to memory in two 8bit transactions. With this
> change, we can now always use the optimised mode for receive-only
> transcations
> The logic in the main transmit loop took a bit of reading the TRM to
> fully understand (due to silent assumptions based in internal logic):
> the "wait until idle" at the end of each iteration through the loop is
> required for the transmit-path as each clearing of the ENA register
> (to update
> The SPI controller's documentation (I only had access to the RK3399,
> RK3368 and PX30 TRMs) specifies that, when operating in master-mode,
> the controller will stop the SCLK to avoid RXFIFO overruns and TXFIFO
> underruns. Looks like my worries that we'd need to support DMA-330
> (aka PL330)
> For the RK3399-Q7 we recommend storing SPL and u-boot.itb in the
> on-module 32MBit (and sometimes even larger, if requested as part of a
> configure-to-order configuration) SPI-NOR flash that is clocked for a
> bitrate of 49.5MBit/s and connected in a single-IO configuration (the
> RK3399 only
> Over the last quarter, a part of our production has used NOR flash
> from Gigadevice in addition to the Winbond parts that we typically
> source. This requires the SPI_FLASH_GIGADEVICE config to be set.
>
> Enable SPI_FLASH_GIGADEVICE in the board's default defconfig.
>
> Signed-off-by:
> While rkspi_enable_chip is called with true/false everywhere else in
> the file, one call site uses '0' to denot 'false'.
> This change this one parameter to 'false' and effects consistency.
>
> Signed-off-by: Philipp Tomsich
> ---
>
> drivers/spi/rk_spi.c | 2 +-
> 1 file changed, 1
> In analysing delays introduced for large SPI reads, the absence of any
> indication when a delay was inserted (to ensure the CS toggling is
> observed by devices) became apparent.
>
> Add an additional debug-only debug message to record the insertion and
> duration of any delay (note that the
Hi Tom
On 4/22/19 12:59 AM, Tom Rini wrote:
> On Fri, Apr 19, 2019 at 04:03:24PM +, Patrice CHOTARD wrote:
>
>> Hi Tom
>>
>> Please find the pull request for STM32 round 2
>>
>> The following changes since commit 1f4ae66eaab29bfb5d1eb44996f7826c9cd01ed1:
>>
>> Merge tag 'arc-for-2019.07'
in the git repository at:
https://github.com/pchotard/u-boot.git tags/u-boot-stm32-mcu-20190423
for you to fetch changes up to c406a474311c1ee3c4303a7e85db4a8e45966e31:
mmc: stm32_sdmmc2: Fix r1b timeout issue (2019-04-23 15:42:28 +0200
pretty sure i know the answer to this, but i'm going to ask it
anyway ... should all header files under include/configs/ be included
in a build either directly or indirectly via the value in
CONFIG_SYS_CONFIG_NAME?
i'm aware of that Kbuild setting and what it's used for:
config
Hi Padmarao,
On Thu, Apr 18, 2019 at 2:21 AM Padmarao Begari
wrote:
>
> This patch adds Microchip MPFS Icicle Board support.
nits: Board->board. Please fix the commit message too.
> For now, NS16550 serial driver is only enabled.
> The Microchip MPFS Icicle defconfig by default builds
> U-Boot
Hi Peng,
On Mon, Apr 22, 2019 at 11:00 PM Peng Fan wrote:
> Honestly I am not familiar with imx_usb, we use mfgtool previously and not
> uuu tool.
> Would you share where to download imx_usb and any doc,
> Then we will debug this issue.
You can get imx_usb_loader tool from
On Tue, Apr 23, 2019 at 8:14 PM Bin Meng wrote:
>
> Hi Rick,
>
> On Tue, Apr 23, 2019 at 1:47 PM Andes wrote:
> >
> > From: Rick Chen
> >
>
> typo in the commit title: seletable -> selectable
>
> > In smp flow this two features only can be enabled when U-Boot
>
> this->these
>
> > boot from
Hi Rick,
On Tue, Apr 23, 2019 at 1:47 PM Andes wrote:
>
> From: Rick Chen
>
nits in the commit title: boot->booting
> When AE350 was booting from ram, use OF_PRIOR_STAGE instead
> of OF_PRIOR_STAGE.
This should be CONFIG_OF_BOARD
>
> Signed-off-by: Rick Chen
> Cc: Greentime Hu
> ---
>
Hi Rick,
On Tue, Apr 23, 2019 at 1:47 PM Andes wrote:
>
> From: Rick Chen
>
commit title should read: prior_stage_fdt_address should only be used
when OF_PRIOR_STAGE is enabled
> This patch will fix prior_stage_fdt_address write failure problem, when
> AE350 was booting from flash.
>
> When
Hi Rick,
On Tue, Apr 23, 2019 at 1:47 PM Andes wrote:
>
> From: Rick Chen
nits in the commit title: boot->booting
>
> Add two defconfig to support AE350 SMP boot from flash
boot->bootings
> by disable CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS.
disable->disabling
>
> Signed-off-by:
Hi Rick,
On Tue, Apr 23, 2019 at 1:47 PM Andes wrote:
>
> From: Rick Chen
>
typo in the commit title: seletable -> selectable
> In smp flow this two features only can be enabled when U-Boot
this->these
> boot from ram. It shall be disabled when U-Boot boot from flash.
boot->boots
>
> Add
On 4/23/19 7:40 AM, Simon Goldschmidt wrote:
> On Mon, Apr 22, 2019 at 9:08 PM Marek Vasut wrote:
>>
>> On 4/22/19 8:31 PM, Simon Goldschmidt wrote:
>>> The following changes since commit
>>> 6c5f8dd540d7a8eff244d4c27a09451ca12c8d20:
>>>
>>> Merge branch 'master' of git://git.denx.de/u-boot-usb
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