On Tue, 7 May 2019 13:29:41 +
Peng Fan wrote:
> > Subject: Re: [i.MX8MM+CCF 12/41] clk: fixed_rate: add pre reloc flag
> >
> > On Tue, 30 Apr 2019 10:18:12 +
> > Peng Fan wrote:
> >
> > > Add pre reloc flag to use this driver before relocation
> > >
> > > Signed-off-by: Peng Fan
> >
On 05/08/2019 01:41 PM, Jagan Teki wrote:
> Since rockchip have an individual doc/README.rockchip, it would
> be better to update the same instead of maintaining it separately
> in board files.
>
> So, add the documentation for rk3399
> - procedure to build for Rockchip miniloader and
> U-Boot
On 05/08/2019 01:41 PM, Jagan Teki wrote:
> Add initial support for Rock PI 4 board.
>
> Specification
> - Rockchip RK3399
> - LPDDR4
> - eMMC
> - SD card slot
> - RTL8211E 1Gbps
> - HDMI In/Out, DP, MIPI DSI/CSI
> - PCIe M.2
> - USB 2.0, USB-3.0
> - USB C Type
>
> Commit details of rk3399-rock-p
> -Original Message-
> From: Lukasz Majewski [mailto:lu...@denx.de]
> Sent: 2019年5月8日 14:46
> To: Peng Fan
> Cc: sba...@denx.de; feste...@gmail.com; dl-uboot-imx
> ; s...@chromium.org; ja...@amarulasolutions.com;
> s...@denx.de; u-boot@lists.denx.de; tr...@konsulko.com
> Subject: Re: [i.
On Tue, 7 May 2019 13:27:45 +
Peng Fan wrote:
> > Subject: Re: [i.MX8MM+CCF 11/41] clk: fixed_rate: export
> > clk_fixed_rate
> >
> > Hi Peng,
> >
> > > Export the structure for others to use.
> > >
> > > Signed-off-by: Peng Fan
> > > ---
> > > drivers/clk/clk_fixed_rate.c | 8 +---
DRAM init would require in
- TPL stage if target support TPL and
- SPL stage if target support SPL alone
So, don't initialize the dram in SPL if TPL defined and at
the same time enable it if TPL undefined which is SPL alone.
Tested in TPL and SPL supported boards.
Signed-off-by: Jagan Teki
---
If PMIC is not probed successfully, it is still OK to boot
with default configuration although power is not optimized.
Default voltage of SW1A/SW1B is 1.1V/1.0V for PC32PF3000A1EP
on pico according to table 42 of spec of PF3000 ver 9.0.
Default mode of SW1A/SW1B is APS as expected(table 47).
Sig
Add default configuration to run u-boot as BL33 in the boot flow case
of ATF(ARM Trusted Firmware) -> OPTEE -> U-boot.
Signed-off-by: Jun Nie
---
configs/pico-imx7d_bl33_defconfig | 66 +++
1 file changed, 66 insertions(+)
create mode 100644 configs/pico-imx7
Add Documentation of BL33 usage case. U-boot is in
non-secure world in this case.
Signed-off-by: Jun Nie
---
board/technexion/pico-imx7d/README.pico-imx7d_BL33 | 44 ++
1 file changed, 44 insertions(+)
create mode 100644 board/technexion/pico-imx7d/README.pico-imx7d_BL33
di
Correct uart clock root ID. Incorrect ID may result the
clock is gated because rate value 0 is returned in
imx_get_uartclk()
The ID can be ignored if CONFIG_SKIP_LOWLEVEL_INIT is not enabled
because init_clk_uart() will enable all uart clocks in that case.
Signed-off-by: Jun Nie
---
arch/arm/in
Skip secure related initialization in arch_cpu_init if low level
init is skipped. Because these should be done in early stage
firmware, such as ARM trusted firmware.
Signed-off-by: Jun Nie
---
arch/arm/mach-imx/mx7/soc.c | 43 ---
1 file changed, 28 inser
Subtracts CONFIG_OPTEE_TZDRAM_SIZE from the available DRAM size so that
the OPTEE memory is not override during u-boot relocation.
Note the OPTEE live in the end part of DRAM and OPTEE boot process will
itself subtract the DRAM region it lives in from the memory map passed
to Linux.
Signed-off-by
Add boot option to boot from fitimage to support verified boot.
The boot script plain text file should be packed into fit blob as
image with name of bootscr.
Signed-off-by: Jun Nie
---
include/configs/pico-imx7d.h | 38 +++---
1 file changed, 35 insertions(+), 3 d
Share configs in mx7 to skip low level init if we are in the case where
OPTEE is loaded already (maybe by ARM Trusted Firmware) and that most of
the low level initialization is already done and that we may/should skip
it doing them here.
Fix the definition detection with size detection to decide w
Add configuration to boot U-boot as BL33 case. The boot flow
is ATF -> OPTEE -> U-boot.
Changes vs V3:
- Remove CONFIG_IMX_CONSOLE_UART_ID.
- Add workaround if PMIC is not probed successfully.
- Add non-secure world cpu initilization for CONFIG_SKIP_LOWLEVEL_INIT case.
Changes vs V2:
- Revise fix
On Wed, 8 May 2019 08:19:45 +0200
Lukasz Majewski wrote:
> Hi Peng,
>
> > Hi Lukasz,
> >
> > > Subject: [PATCH] Revert "mmc: fsl_esdhc: fix sd/mmc ddr mode clock
> > > setting issue"
> > >
> > > This reverts commit 72a89e0da5ac6a4ab929b15a2b656f04f50767f6,
> > > which causes the imx53 HSC to
> Subject: Re: [i.MX8MM+CCF 08/41] clk: export mux/divider ops
>
> On Tue, 7 May 2019 13:25:00 +
> Peng Fan wrote:
>
> > > Subject: Re: [i.MX8MM+CCF 08/41] clk: export mux/divider ops
> > >
> > > On Tue, 30 Apr 2019 10:17:58 +
> > > Peng Fan wrote:
> > >
> > > > Export mux/divider ops
Signed-off-by: Matwey V. Kornilov
---
configs/rock64-rk3328_defconfig | 91 +
1 file changed, 91 insertions(+)
create mode 100644 configs/rock64-rk3328_defconfig
diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig
new file mode
From: Kever Yang
Enable SPL support and some related option in Kconfig.
Signed-off-by: Kever Yang
[cherry picked from
https://github.com/rockchip-linux/u-boot/commit/430b01462bf3f24aaf7920ae2587a6943c39ab5d
with minor modifications]
Signed-off-by: Matwey V. Kornilov
---
arch/arm/mach-rockch
rk3328-rock64.dts has been taken from Linux kernel with minor
modifications.
Signed-off-by: Matwey V. Kornilov
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3328-rock64-u-boot.dtsi | 30
arch/arm/dts/rk3328-rock64.dts | 294 +
3
From: Kever Yang
Enable SPL_FRAMEWORK and SPL related base addr and size.
Signed-off-by: Kever Yang
[cherry picked from
https://github.com/rockchip-linux/u-boot/commit/cb2b7a1bc75ebb116b1eb9b0ae0223e84d86fc4b
with minor modifications]
Signed-off-by: Matwey V. Kornilov
---
include/configs/rk
From: Kever Yang
rk3328 spl is locate at dram, so do not have strict size limit,
suppose to enable storage media controller driver, load ATF and
U-Boot, then boot into ATF.
Signed-off-by: Kever Yang
[cherry picked from
https://github.com/rockchip-linux/u-boot/commit/4ebe3968b683190cb8e5741aa72
This series adds initial basic support for Pine64 Rock64 board.
The ROCK64 is a credit card size SBC based on Rockchip RK3328 Quad-Core ARM
Cortex A53.
This series allow building u-boot SPL and u-boot.itb for Rock64 board.
Unfortunately, proprietary TPL is stil required for deploy:
./tools/mkim
On Tue, 7 May 2019 13:25:00 +
Peng Fan wrote:
> > Subject: Re: [i.MX8MM+CCF 08/41] clk: export mux/divider ops
> >
> > On Tue, 30 Apr 2019 10:17:58 +
> > Peng Fan wrote:
> >
> > > Export mux/divider ops for composite usage
> > >
> > > Signed-off-by: Peng Fan
> > > ---
> > > include
Hi Peng,
> Hi Lukasz,
>
> > Subject: [PATCH] Revert "mmc: fsl_esdhc: fix sd/mmc ddr mode clock
> > setting issue"
> >
> > This reverts commit 72a89e0da5ac6a4ab929b15a2b656f04f50767f6, which
> > causes the imx53 HSC to hang as the eMMC is not working properly
> > anymore.
> >
> > The exact error
Add initial support for Rock PI 4 board.
Specification
- Rockchip RK3399
- LPDDR4
- eMMC
- SD card slot
- RTL8211E 1Gbps
- HDMI In/Out, DP, MIPI DSI/CSI
- PCIe M.2
- USB 2.0, USB-3.0
- USB C Type
Commit details of rk3399-rock-pi-4.dts sync from Linux 5.1-rc2:
"arm64: dts: rockchip: add ROCK Pi 4
Add default SPL_FIT_GENERATOR py script for rockchip platforms if
specific target enabled SPL_LOAD_FIT.
So, this would help get rid of explicitly mentioning the default
SPL FIT generator in defconfigs. however some targets, like puma_rk3399
still require their own FIT generator so in those cases t
On 5/8/19 3:08 AM, Takahiro Akashi wrote:
On Wed, May 08, 2019 at 02:59:08AM +0200, Heinrich Schuchardt wrote:
On 5/8/19 1:59 AM, Takahiro Akashi wrote:
On Tue, May 07, 2019 at 09:13:24PM +0200, Heinrich Schuchardt wrote:
Implement unloading of images in the Exit() boot services:
* unload ima
Add initial support for Nanopc T4 board.
Specification
- Rockchip RK3399
- Dual-Channel 4GB LPDDR3-1866
- SD card slot
- 16GB eMMC
- RTL8211E 1Gbps
- AP6356S WiFI/BT
- HDMI In/Out, DP, MIPI DSI/CSI, eDP
- USB 3.0, 2.0
- USB Type C power and data
- GPIO expansion ports
- DC 12V/2A
Commit details o
Add initial support for Rockpro64 board.
Specification
- Rockchip RK3399
- 2/4GB Dual-Channel LPDDR3
- SD card slot
- eMMC socket
- 128Mb SPI Flash
- Gigabit ethernet
- PCIe 4X slot
- WiFI/BT module socket
- HDMI In/Out, DP, MIPI DSI/CSI, eDP
- USB 3.0, 2.0
- USB Type C power and data
- GPIO expan
Add initial support for Nanopi NEO4 board.
Specification
- Rockchip RK3399
- 1GB DDR3-1866
- SD card slot
- eMMC Socket
- RTL8211E 1Gbps
- AP6212 WiFI/BT
- HDMI In/Out, DP, MIPI CSI
- USB 3.0, 2.0
- USB Type C power and data
- GPIO expansion ports
- DC 5V/3A
Commit details of rk3399-nanopi-neo4.d
Since rockchip have an individual doc/README.rockchip, it would
be better to update the same instead of maintaining it separately
in board files.
So, add the documentation for rk3399
- procedure to build for Rockchip miniloader and
U-Boot SPL options
- procedure to boot from SD for Rockchip mini
Few SPL and U-Boot proper configs are common to all rk3399 target
defconfigs, move them and select it from platform kconfig.
Moved configs:
- SPL_ATF
- SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
- SPL_LOAD_FIT
- SPL_CLK if SPL
- SPL_PINCTRL if SPL
- SPL_RAM if SPL
- SPL_REGMAP if SPL
- SPL_SYSCO
sdmmc cd pin is configured as RK_FUNC_GPIO which is wrong and
indeed failed to detect the sdcard on the board with below error
Card did not respond to voltage select!
So, fix it by replacing RK_FUNC_GPIO with RK_FUNC_1 which
is already defined in rk3399.dts so make use of same like
other boards
Add initial support for Nanopi M4 board.
Specification
- Rockchip RK3399
- Dual-Channel 4GB LPDDR3-1866
- SD card slot
- eMMC socket
- RTL8211E 1Gbps
- AP6356S WiFI/BT
- HDMI In/Out, DP, MIPI DSI/CSI
- USB 3.0 x4
- USB Type C power and data
- GPIO1, GPIO2 expansion ports
- DC5V/3A
Commit details
Sync rk3399-nanopi4.dtsi from Linux 5.1-rc2 tag.
Linux commit details about the rk3399-nanopi4.dtsi sync:
"arm64: dts: rockchip: Add nanopi4 bluetooth"
(sha1: 3e2f0bb72be36aa6c14ee7f11ac4dd8014801030)
Signed-off-by: Jagan Teki
Reviewed-by: Paul Kocialkowski
Reviewed-by: Kever Yang
---
arch/ar
To make successful build with dts(i) files syncing from Linux 5.1-rc2
the rk3399.dtsi would require pwm2_pin_pull_down.
So, sync the pwm2_pin_pull_down node from Linux 5.1-rc2. Since this
node is strictly not part of any commit alone, I have mentioned
Linux 5.1-rc2 tag for future reference of whe
(Sorry for the noice, I have missed to send two patches from v7)
This is v7 resend patchset for New rk3399 boards support wrt previous
version[1]
Unfortunately initial version of creating rk3399-u-boot.dtsi and
orangepi rk3399 changes are merged, so this is rework on top of
u-boot-rockchip/mast
Hi Kever,
> Subject: [PATCH] bouncebuf: add feature to support buffer only available in
> DRAM
>
> Some DMA which inside peripheral controller can only access space in DRAM
> area, the target address outside DRAM is not available.
> eg. Rockchip MMC contrller's internal DMA can only access DRAM a
Hi Simon,
On Wed, May 8, 2019 at 11:41 AM Simon Glass wrote:
>
> Hi Bin,
>
> On Tue, 7 May 2019 at 21:33, Bin Meng wrote:
> >
> > Hi Simon,
> >
> > On Tue, May 7, 2019 at 6:07 PM Bin Meng wrote:
> > >
> > > Hi Simon,
> > >
> > > On Fri, May 3, 2019 at 12:52 AM Simon Glass wrote:
> > > >
> > >
On Wed, May 8, 2019 at 11:41 AM Simon Glass wrote:
>
> Add a version of samus which supports booting from TPL to SPL and then
> to U-Boot. This allows TPL to select from an A or B SPL to support
> verified boot with field upgrade.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
>
On Wed, May 8, 2019 at 11:41 AM Simon Glass wrote:
>
> This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d.
>
> Unfortunately this has a dramatic impact on the pre-relocation memory
> used on x86 platforms (increasing it by 2KB) since it increases the
> overhead for each PCI device from 2
On Wed, May 8, 2019 at 11:41 AM Simon Glass wrote:
>
> Add nvdata drivers for the TPM and RTC as used on samus. These are needed
> for Chromium OS verified boot on samus.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2: N
On Wed, May 8, 2019 at 12:40 PM Bin Meng wrote:
>
> On Wed, May 8, 2019 at 11:41 AM Simon Glass wrote:
> >
> > Add tags to allow required nodes to be present in SPL / TPL.
> >
> > Signed-off-by: Simon Glass
> >
> > ---
> >
> > Changes in v4:
> > - Update commit message to not mention the sysrese
On Wed, May 8, 2019 at 11:41 AM Simon Glass wrote:
>
> Add tags to allow required nodes to be present in SPL / TPL.
>
> Signed-off-by: Simon Glass
>
> ---
>
> Changes in v4:
> - Update commit message to not mention the sysreset driver.
> - Drop change to SPI flash memory-map property
>
> Changes
On Tue, 2019-05-07 at 22:00 +0200, Simon Goldschmidt wrote:
>
> On 07.05.19 19:25, Andreas Dannenberg wrote:
> >
[...]
> >
> > While I also have a working solution based on the existing FS
> > loader
> > framework this has its own challenges, namely by its very nature
> > only
> > addressing a s
On Tue, 2019-05-07 at 21:44 +0200, Marek Vasut wrote:
> On 5/7/19 9:43 PM, Simon Goldschmidt wrote:
> >
> >
> >
> > On 07.05.19 21:41, Marek Vasut wrote:
> > >
> > > On 5/7/19 9:36 PM, Simon Goldschmidt wrote:
> > > >
> > > >
> > > >
> > > > On 07.05.19 21:19, Marek Vasut wrote:
> > > > >
>
On 5/8/19 5:07 AM, Ley Foon Tan wrote:
> Fix SPI flash environment erase size error.
>
> CONFIG_ENV_SECT_SIZE is set to 4KB. Enable CONFIG_SPI_FLASH_USE_4K_SECTORS
> to allow erase one environment sector.
>
> Fix error below:
>
> SOCFPGA_STRATIX10 # saveenv
> Saving Environment to SPI Flash...
>
On 05/08/2019 02:36 AM, Jagan Teki wrote:
> Add initial support for Nanopi NEO4 board.
>
> Specification
> - Rockchip RK3399
> - 1GB DDR3-1866
> - SD card slot
> - eMMC Socket
> - RTL8211E 1Gbps
> - AP6212 WiFI/BT
> - HDMI In/Out, DP, MIPI CSI
> - USB 3.0, 2.0
> - USB Type C power and data
> - GP
On 05/08/2019 02:36 AM, Jagan Teki wrote:
> Add initial support for Rockpro64 board.
>
> Specification
> - Rockchip RK3399
> - 2/4GB Dual-Channel LPDDR3
> - SD card slot
> - eMMC socket
> - 128Mb SPI Flash
> - Gigabit ethernet
> - PCIe 4X slot
> - WiFI/BT module socket
> - HDMI In/Out, DP, MIPI D
On 05/08/2019 02:36 AM, Jagan Teki wrote:
> Add initial support for Nanopc T4 board.
>
> Specification
> - Rockchip RK3399
> - Dual-Channel 4GB LPDDR3-1866
> - SD card slot
> - 16GB eMMC
> - RTL8211E 1Gbps
> - AP6356S WiFI/BT
> - HDMI In/Out, DP, MIPI DSI/CSI, eDP
> - USB 3.0, 2.0
> - USB Type C
On 05/08/2019 02:36 AM, Jagan Teki wrote:
> sdmmc cd pin is configured as RK_FUNC_GPIO which is wrong and
> indeed failed to detect the sdcard on the board with below error
>
> Card did not respond to voltage select!
>
> So, fix it by replacing RK_FUNC_GPIO with RK_FUNC_1 which
> is already def
On 05/08/2019 02:36 AM, Jagan Teki wrote:
> Sync rk3399-nanopi4.dtsi from Linux 5.1-rc2 tag.
>
> Linux commit details about the rk3399-nanopi4.dtsi sync:
> "arm64: dts: rockchip: Add nanopi4 bluetooth"
> (sha1: 3e2f0bb72be36aa6c14ee7f11ac4dd8014801030)
>
> Signed-off-by: Jagan Teki
> Reviewed-by
On 05/08/2019 02:36 AM, Jagan Teki wrote:
> Few SPL and U-Boot proper configs are common to all rk3399 target
> defconfigs, move them and select it from platform kconfig.
>
> Moved configs:
> - SPL_ATF
> - SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
> - SPL_LOAD_FIT
> - SPL_CLK if SPL
> - SPL_PINCT
On 05/08/2019 02:36 AM, Jagan Teki wrote:
> Add default SPL_FIT_GENERATOR py script for rockchip platforms if
> specific target enabled SPL_LOAD_FIT.
>
> So, this would help get rid of explicitly mentioning the default
> SPL FIT generator in defconfigs. however some targets, like puma_rk3399
> st
On 05/08/2019 02:36 AM, Jagan Teki wrote:
> To make successful build with dts(i) files syncing from Linux 5.1-rc2
> the rk3399.dtsi would require pwm2_pin_pull_down.
>
> So, sync the pwm2_pin_pull_down node from Linux 5.1-rc2. Since this
> node is strictly not part of any commit alone, I have me
On 05/08/2019 02:24 AM, Jagan Teki wrote:
> CONFIG_SPL_TEXT_BASE was available in configs/rk3399_common.h
> when the OrangePI rk3399 board supported during first
> version patch.
>
> But, later below change which move this config into Kconfig and
> same has been merged in mainline tree.
> "config
Add a version of samus which supports booting from TPL to SPL and then
to U-Boot. This allows TPL to select from an A or B SPL to support
verified boot with field upgrade.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Sort defconfi
Hi Bin,
On Tue, 7 May 2019 at 21:33, Bin Meng wrote:
>
> Hi Simon,
>
> On Tue, May 7, 2019 at 6:07 PM Bin Meng wrote:
> >
> > Hi Simon,
> >
> > On Fri, May 3, 2019 at 12:52 AM Simon Glass wrote:
> > >
> > > At present SPL is used on 64-bit platforms, to allow SPL to be built as
> > > a 32-bit p
Add tags to allow required nodes to be present in SPL / TPL.
Signed-off-by: Simon Glass
---
Changes in v4:
- Update commit message to not mention the sysreset driver.
- Drop change to SPI flash memory-map property
Changes in v3:
- Remove unneeded pch-reset node
Changes in v2: None
arch/x86/
This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d.
Unfortunately this has a dramatic impact on the pre-relocation memory
used on x86 platforms (increasing it by 2KB) since it increases the
overhead for each PCI device from 220 bytes to 412 bytes.
The offending line is in UCLASS_DRIVER(
Add nvdata drivers for the TPM and RTC as used on samus. These are needed
for Chromium OS verified boot on samus.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/x86/dts/chromebook_samus.dts | 22 +-
1 f
On 05/08/2019 02:21 AM, Jagan Teki wrote:
> Now we have
> - board specific -u-boot.dtsi files for board specific u-boot
> dts changes.
> - soc specific rk3399-u-boot.dtsi for soc specific u-boot
> dts changes.
>
> So, include the rk3399-u-boot-dtsi on respective board -u-boot.dtsi
> and drop
At present SPL is used on 64-bit platforms, to allow SPL to be built as
a 32-bit program and U-Boot proper to be built as 64-bit.
However it is useful to be able to use SPL on any x86 platform, where
U-Boot needs to be updated in the field. Then SPL can select which U-Boot
to run (A or B) and most
On 05/08/2019 02:21 AM, Jagan Teki wrote:
> Devicetree files in RK3399 platform is synced from Linux, like other
> platforms does. Apart from these u-boot in rk3399 would also require
> some u-boot specific node like dmc.
>
> dmc node has big chunk of DDR timing parameters which are specific
> to
On 05/08/2019 02:21 AM, Jagan Teki wrote:
> Add u-boot,dm-pre-reloc property for spi1, so-that the
> subsequent rk3399 boards which boot from SPI.
>
> This help to separate the u-boot specific properties away
> from base dts files so-that the Linux sync become easy and
> meaningful.
>
> Signed-of
On 05/08/2019 02:21 AM, Jagan Teki wrote:
> - Sometimes u-boot specific dtsi files are included
> automatically which would build for entire rockchip SoC,
> even-though the respective dtsi should used it for specific
> family of rockchip SoC.
> - Sometimes u-boot specific dts nodes or prope
Hi Simon,
On Tue, May 7, 2019 at 6:07 PM Bin Meng wrote:
>
> Hi Simon,
>
> On Fri, May 3, 2019 at 12:52 AM Simon Glass wrote:
> >
> > At present SPL is used on 64-bit platforms, to allow SPL to be built as
> > a 32-bit program and U-Boot proper to be built as 64-bit.
> >
> > However it is useful
Hi Simon,
On Wed, May 8, 2019 at 11:04 AM Simon Glass wrote:
>
> Hi Bin,
>
> On Tue, 7 May 2019 at 03:28, Bin Meng wrote:
> >
> > Hi Simon, Thierry,
> >
> > On Fri, May 3, 2019 at 12:22 AM Simon Glass wrote:
> > >
> > > Hi Thierry,
> > >
> > > On Thu, 2 May 2019 at 03:25, Thierry Reding wrote:
Fix SPI flash environment erase size error.
CONFIG_ENV_SECT_SIZE is set to 4KB. Enable CONFIG_SPI_FLASH_USE_4K_SECTORS
to allow erase one environment sector.
Fix error below:
SOCFPGA_STRATIX10 # saveenv
Saving Environment to SPI Flash...
SF: Detected mt25qu02g with page size 256 Bytes, erase siz
Hi Bin,
On Tue, 7 May 2019 at 03:28, Bin Meng wrote:
>
> Hi Simon, Thierry,
>
> On Fri, May 3, 2019 at 12:22 AM Simon Glass wrote:
> >
> > Hi Thierry,
> >
> > On Thu, 2 May 2019 at 03:25, Thierry Reding wrote:
> > >
> > > On Thu, May 02, 2019 at 12:09:49AM +0800, Bin Meng wrote:
> > > > +Thierr
On 5/8/19 4:42 AM, Ley Foon Tan wrote:
> On Tue, May 7, 2019 at 9:04 PM Marek Vasut wrote:
>>
>> On 5/7/19 8:01 AM, Ley Foon Tan wrote:
>>> Fix SPI flash environment erase size error.
>>>
>>> Erase size of flash mt25qu02g on Stratix 10 should be 64KB.
>>>
>>> SOCFPGA_STRATIX10 # saveenv
>>> Saving
On Tue, May 7, 2019 at 9:04 PM Marek Vasut wrote:
>
> On 5/7/19 8:01 AM, Ley Foon Tan wrote:
> > Fix SPI flash environment erase size error.
> >
> > Erase size of flash mt25qu02g on Stratix 10 should be 64KB.
> >
> > SOCFPGA_STRATIX10 # saveenv
> > Saving Environment to SPI Flash...
> > SF: Detect
Hi Fabio,
> Subject: [PATCH] imx: mkimage_fit_atf: Fix DTC warnings
>
> When generating the flash.bin binary the following DTC warnings are seen:
>
> u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/uboot@1 has
> a unit name, but no reg property
> u-boot.itb.tmp: Warning (unit_address
Hi Lukasz,
> Subject: [PATCH] Revert "mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting
> issue"
>
> This reverts commit 72a89e0da5ac6a4ab929b15a2b656f04f50767f6, which
> causes the imx53 HSC to hang as the eMMC is not working properly anymore.
>
> The exact error message:
> MMC write: dev # 0,
On Wed, May 08, 2019 at 02:59:08AM +0200, Heinrich Schuchardt wrote:
> On 5/8/19 1:59 AM, Takahiro Akashi wrote:
> >On Tue, May 07, 2019 at 09:13:24PM +0200, Heinrich Schuchardt wrote:
> >>Implement unloading of images in the Exit() boot services:
> >>
> >>* unload images that are not yet started,
On 5/8/19 1:59 AM, Takahiro Akashi wrote:
On Tue, May 07, 2019 at 09:13:24PM +0200, Heinrich Schuchardt wrote:
Implement unloading of images in the Exit() boot services:
* unload images that are not yet started,
* unload started applications,
* unload drivers returning an error.
Signed-off-by:
On 5/8/19 1:56 AM, Takahiro Akashi wrote:
On Tue, May 07, 2019 at 06:54:45PM +0200, Heinrich Schuchardt wrote:
On 5/7/19 9:30 AM, Takahiro Akashi wrote:
On Tue, May 07, 2019 at 09:12:56AM +0200, Heinrich Schuchardt wrote:
On 5/7/19 8:16 AM, Takahiro Akashi wrote:
On Tue, May 07, 2019 at 08:04
On Tue, May 07, 2019 at 09:13:24PM +0200, Heinrich Schuchardt wrote:
> Implement unloading of images in the Exit() boot services:
>
> * unload images that are not yet started,
> * unload started applications,
> * unload drivers returning an error.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> v
On Tue, May 07, 2019 at 06:54:45PM +0200, Heinrich Schuchardt wrote:
> On 5/7/19 9:30 AM, Takahiro Akashi wrote:
> >On Tue, May 07, 2019 at 09:12:56AM +0200, Heinrich Schuchardt wrote:
> >>On 5/7/19 8:16 AM, Takahiro Akashi wrote:
> >>>On Tue, May 07, 2019 at 08:04:26AM +0200, Heinrich Schuchardt w
Hi Tom,
The following changes since commit 8d7f06bbbef16f172cd5e9c4923cdcebe16b8980:
I rebased on your master and built for BB Black. DHCP seems to work fine.
MLO also now fits again.
Merge branch 'master' of git://git.denx.de/u-boot-sh (2019-05-07 09:38:00
-0400)
are available in the git re
Hi Pierre-Jean,
On Tue, May 7, 2019 at 6:55 PM Pierre-Jean Texier wrote:
>
> Since the pico-pi uses the distroboot,
> this commit remove the 'script' variable (cf boot_scripts).
>
> Signed-off-by: Pierre-Jean Texier
Yes, we should better remove it:
Reviewed-by: Fabio Estevam
_
Since the pico-pi uses the distroboot,
this commit remove the 'script' variable (cf boot_scripts).
Signed-off-by: Pierre-Jean Texier
---
include/configs/pico-imx7d.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h
index 365a598..a683
Hi Breno,
On Tue, May 7, 2019 at 5:19 PM Breno Matheus Lima wrote:
>
> According to hab.c code we have to notify the ROM code if the MMU is
> enabled or not. This is achieved by setting the "pu_irom_mmu_enabled"
> to 0x1.
>
> The current address in hab.c code is wrong for i.MX6SL, according to RO
According to hab.c code we have to notify the ROM code if the MMU is
enabled or not. This is achieved by setting the "pu_irom_mmu_enabled"
to 0x1.
The current address in hab.c code is wrong for i.MX6SL, according to ROM
map file the correct address is 0x00901c60.
As we are writing in the wrong ad
On 07.05.19 19:25, Andreas Dannenberg wrote:
TI K3 SoCs like the AM654x devices are fundamentally dependent on a
firmware called SYSFW (System Firmware) being loaded into the dedicated
DMSC (Device Management and Security Controller) processor to provide
various services via TISCI (Texas Instru
On 5/7/19 9:43 PM, Simon Goldschmidt wrote:
>
>
> On 07.05.19 21:41, Marek Vasut wrote:
>> On 5/7/19 9:36 PM, Simon Goldschmidt wrote:
>>>
>>>
>>> On 07.05.19 21:19, Marek Vasut wrote:
According to SoCFPGA Cyclone V datasheet rev.2018.01.26 page 175
(Chapter 5, FPGA Manager, data regist
On 07.05.19 21:41, Marek Vasut wrote:
On 5/7/19 9:36 PM, Simon Goldschmidt wrote:
On 07.05.19 21:19, Marek Vasut wrote:
According to SoCFPGA Cyclone V datasheet rev.2018.01.26 page 175
(Chapter 5, FPGA Manager, data register) and Arria10 datasheet
rev.2017.07.22 page 211 (Chapter 5.4.1.2, F
On 5/7/19 9:42 PM, Simon Goldschmidt wrote:
>
>
> On 07.05.19 21:20, Marek Vasut wrote:
>> On SoCFPGA Gen5 systems, it can rarely happen that a reboot from Linux
>> will result in stale data in PL310 L2 cache controller. Even if the L2
>> cache controller is disabled via the CTRL register CTRL_EN
On 07.05.19 21:20, Marek Vasut wrote:
On SoCFPGA Gen5 systems, it can rarely happen that a reboot from Linux
will result in stale data in PL310 L2 cache controller. Even if the L2
cache controller is disabled via the CTRL register CTRL_EN bit, those
data can interfere with operation of devices
On 07.05.19 21:19, Marek Vasut wrote:
According to SoCFPGA Cyclone V datasheet rev.2018.01.26 page 175
(Chapter 5, FPGA Manager, data register) and Arria10 datasheet
rev.2017.07.22 page 211 (Chapter 5.4.1.2, FPGA Manager, img_data_w
register), the FPGA data register must be written with writes
On 07.05.19 21:20, Marek Vasut wrote:
Pull the PL310 clearing code into common code, so it can be reused
by Arria10.
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dalon Westergreen
Cc: Dinh Nguyen
Cc: Simon Goldschmidt
Cc: Tien Fong Chee
Reviewed-by: Simon Goldschmidt
---
arch
On 5/7/19 9:36 PM, Simon Goldschmidt wrote:
>
>
> On 07.05.19 21:19, Marek Vasut wrote:
>> According to SoCFPGA Cyclone V datasheet rev.2018.01.26 page 175
>> (Chapter 5, FPGA Manager, data register) and Arria10 datasheet
>> rev.2017.07.22 page 211 (Chapter 5.4.1.2, FPGA Manager, img_data_w
>> re
On 5/7/19 9:28 PM, Simon Goldschmidt wrote:
>
>
> On 07.05.19 21:18, Marek Vasut wrote:
>> Pull out the u-boot,dm-pre-reloc from
>> socfpga_arria10_socdk_sdmmc_handoff.dtsi
>> into separate dtsi header file to make it easier to patch in custom
>> handoff
>> dtsi files, without having to manually
On 07.05.19 21:18, Marek Vasut wrote:
Pull out the u-boot,dm-pre-reloc from socfpga_arria10_socdk_sdmmc_handoff.dtsi
into separate dtsi header file to make it easier to patch in custom handoff
dtsi files, without having to manually add the U-Boot bits. Shuffle the include
clauses in the A10 DT
On 07.05.19 21:14, Wolfgang Grandegger wrote:
Am 07.05.19 um 13:37 schrieb Simon Goldschmidt:
On Tue, May 7, 2019 at 9:41 AM Wolfgang Grandegger
wrote:
Am 06.05.19 um 22:16 schrieb Simon Goldschmidt:
Am 06.05.2019 um 17:45 schrieb Wolfgang Grandegger:
Re-add support for Aries Embedded
On 07.05.19 21:17, Andreas Dannenberg wrote:
Hi Simon,
On Tue, May 07, 2019 at 08:16:07PM +0200, Simon Goldschmidt wrote:
On 07.05.19 19:25, Andreas Dannenberg wrote:
Introduce a framework that allows loading the System Firmware (SYSFW)
binary as well as the associated configuration data f
On SoCFPGA Gen5 systems, it can rarely happen that a reboot from Linux
will result in stale data in PL310 L2 cache controller. Even if the L2
cache controller is disabled via the CTRL register CTRL_EN bit, those
data can interfere with operation of devices using DMA, like e.g. the
DWMMC controller.
Pull the PL310 clearing code into common code, so it can be reused
by Arria10.
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dalon Westergreen
Cc: Dinh Nguyen
Cc: Simon Goldschmidt
Cc: Tien Fong Chee
---
arch/arm/mach-socfpga/include/mach/misc.h | 1 +
arch/arm/mach-socfpga/misc.c
According to SoCFPGA Cyclone V datasheet rev.2018.01.26 page 175
(Chapter 5, FPGA Manager, data register) and Arria10 datasheet
rev.2017.07.22 page 211 (Chapter 5.4.1.2, FPGA Manager, img_data_w
register), the FPGA data register must be written with writes with
non-incrementing address.
The curren
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