Sughosh,
On Mon, Mar 23, 2020 at 12:42:01PM +0530, Sughosh Ganu wrote:
> Add support for the get_image_info and set_image routines, which are
> part of the efi firmware management protocol.
>
> The current implementation uses the set_image routine for updating the
> u-boot binary image for the
On 3/31/20 2:34 PM, Rayagonda Kokatanur wrote:
> From: Bharat Kumar Reddy Gooty
>
> Enable SDHCI_QUIRK_BROKEN_R1B quirk.
Is there any problem or special reason to add this quirks?
Best Regards,
Jaehoon Chung
>
> Signed-off-by: Bharat Kumar Reddy Gooty
> Signed-off-by: Rayagonda Kokatanur
>
move host.mmc before sdhci_setup_cfg
Signed-off-by: Rayagonda Kokatanur
Signed-off-by: Bharat Kumar Reddy Gooty
---
drivers/mmc/iproc_sdhci.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/iproc_sdhci.c b/drivers/mmc/iproc_sdhci.c
index
This patch series adds following,
-Fix possible memory leak in probe()
-Enable R1B response quirk
-Fix compilation warning
-Rearrange the code probe()
Bharat Kumar Reddy Gooty (2):
drivers: mmc: iproc_sdhci: fix possible memory leak
drivers: mmc: iproc_sdhci: enable broken R1B response quirk
From: Bharat Kumar Reddy Gooty
Enable SDHCI_QUIRK_BROKEN_R1B quirk.
Signed-off-by: Bharat Kumar Reddy Gooty
Signed-off-by: Rayagonda Kokatanur
---
drivers/mmc/iproc_sdhci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/iproc_sdhci.c
set_ios_post return type changed from void to int, correcting
the same to fix compilation warning.
Signed-off-by: Rayagonda Kokatanur
Signed-off-by: Bharat Kumar Reddy Gooty
---
drivers/mmc/iproc_sdhci.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
From: Bharat Kumar Reddy Gooty
Free the pointer variable 'iproc_sdhci' upon failure to fix
possible memory leak.
Signed-off-by: Bharat Kumar Reddy Gooty
Signed-off-by: Rayagonda Kokatanur
---
drivers/mmc/iproc_sdhci.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git
On Fri, Mar 27, 2020 at 06:27:53AM +0100, Heinrich Schuchardt wrote:
> The UEFI spec requires support for the FAT file system.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> lib/efi_loader/Kconfig | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/lib/efi_loader/Kconfig
On Fri, Mar 27, 2020 at 06:27:56AM +0100, Heinrich Schuchardt wrote:
> If the EFI_OPTIONAL_PTR is set in DebugDisposition, a NULL pointer does not
> constitute an invalid parameter.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> include/efi_api.h| 2 ++
>
Hi Mani,
> Just tested v8 on bubblegum96 and it doesn't boot. I can't see any debug
> print on the console, so I'm guessing something basic going wrong. Will
> try to find the regression if I find some time and keep you posted.
Thanks for trying it. Looks like issue is with clock driver (not
Heinrich,
On Wed, Mar 18, 2020 at 11:04:05AM +0900, AKASHI Takahiro wrote:
> Heinrich,
>
> Thank you for your quick review.
>
> On Tue, Mar 17, 2020 at 08:49:12AM +0100, Heinrich Schuchardt wrote:
> > On 3/17/20 3:12 AM, AKASHI Takahiro wrote:
> > > Summary
> > > ===
> > > 'UpdateCapsule'
The following changes since commit 93330d4ce416208fe202e304e5a18166c57ac569:
Prepare v2020.04-rc4 (2020-03-30 19:29:27 -0400)
are available in the Git repository at:
git://git.denx.de/u-boot-socfpga.git master
for you to fetch changes up to df8e15af2bed62a5a93c5783ec9e32b9029bb010:
arm:
On Tue, Mar 24, 2020 at 09:19:55AM +0530, Sughosh Ganu wrote:
> On Mon, 23 Mar 2020 at 17:20, Heinrich Schuchardt
> wrote:
>
> > On 3/23/20 8:11 AM, Sughosh Ganu wrote:
> > > Add a efidebug subcommand to initiate a firmware update using the efi
> > > firmware management protocol(fmp) set_image
On 1/4/19 10:55 AM, Patrice Chotard wrote:
Hi,
> @@ -215,7 +220,9 @@ U_BOOT_DRIVER(gpio_stm32) = {
> .id = UCLASS_GPIO,
> .of_match = stm32_gpio_ids,
> .probe = gpio_stm32_probe,
> +#ifndef CONFIG_SPL_BUILD
> .ops= _stm32_ops,
> +#endif
> .flags =
On Fri, Mar 27, 2020 at 01:26:09PM +, Kim Bøndergaard wrote:
> I'm struggling with a u-boot as an uefi overlay on x86 (currently Qemu).
> Basically it is working, but I'm now considering how /where to store my
> u-boot environment.
>
> I need to have it stored in a device being accessible
> -Original Message-
> From: Marek Vasut
> Sent: Tuesday, March 31, 2020 8:52 AM
> To: Tan, Ley Foon ; u-boot@lists.denx.de
> Cc: Ley Foon Tan ; See, Chin Liang
> ; Simon Goldschmidt
>
> Subject: Re: [PATCH v2] arm: dts: agilex: Enable QSPI
>
> On 3/31/20 2:45 AM, Ley Foon Tan wrote:
The AV96 RGMII uses different pinmux for ETH_RGMII_TXD0, ETH_RGMII_RXD2
and ETH_RGMII_TX_CTL. Use the correct pinmux to make ethernet operational.
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
V2: No change
---
arch/arm/dts/stm32mp157a-avenger96.dts | 4 ++--
1 file
The AV96 is in fact an assembly of DH Electronics DHCOR SoM on top
of an AV96 reference board. Split the DTs to reflect that and make
sure to DHCOR SoM can be reused on other boards easily.
It is also highly recommended to configure the board for the DHCOM
make stm32mp15_dhcom_basic_defconfig
On 3/31/20 2:45 AM, Ley Foon Tan wrote:
> Enable QSPI for Agilex SoC devkit.
>
> Signed-off-by: Ley Foon Tan
>
> ---
> v2:
> - Fixed missing ";".
> ---
> arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 4
> 1 file changed, 4 insertions(+)
>
> diff --git
Use DT /aliases node to establish a stable phandle to the configuration
EEPROM. This permits the configuration EEPROM to be moved e.g. to a
different address or a different bus. Adjust the board code to handle
new phandle lookup.
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice
Add PHY reset GPIO on AV96 ethernet PHY.
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
V2: No change
---
arch/arm/dts/stm32mp157a-avenger96.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts
The PLL4 is supplying SDMMC12, SDMMC3 and SPDIF with 120 MHz and
FDCAN with 96 MHz. This isn't good for the SDMMC interfaces, which
can not easily divide the clock down to e.g. 50 MHz for high speed
SD and eMMC devices, so those devices end up running at 30 MHz as
that is 120 MHz / 4. Adjust the
The core and vdd PMIC buck regulators were misconfigured, which caused
instability of the board and malfunction of high-speed interfaces, like
the RGMII. Configure the PMIC correctly to repair these problems. Also,
model the missing Enpirion EP53A8LQI on the DHCOR SoM as a fixed regulator.
The DH Electronics DHCOR SOM has QSPI NOR on the SoM itself, add it
into the DT.
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
V2: Drop the explicit flash type in DT node, use spi-flash
---
arch/arm/dts/stm32mp157a-avenger96.dts | 20
1 file
The board has an EEPROM on the same I2C bus as PMIC, at address 0x53.
The EEPROM contains the board MAC address.
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
V2: No change
---
arch/arm/dts/stm32mp157a-avenger96.dts | 6 ++
1 file changed, 6 insertions(+)
diff
Add another mux option for DWMAC RGMII, this is used on AV96 board.
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
V2: No change
---
arch/arm/dts/stm32mp157-pinctrl.dtsi | 51
1 file changed, 51 insertions(+)
diff --git
Add another mux option for SDMMC2 pins 4..7, this is used on AV96 board.
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
V2: Use correct pin AFs
---
arch/arm/dts/stm32mp157-pinctrl.dtsi | 21 +
1 file changed, 21 insertions(+)
diff --git
The SD uses different pinmux for the D123DIRline, use such a pinmux,
otherwise there is a pinmux collision on the AV96. Add missing SD
voltage regulator switch and enable SDR104 operation.
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
V2: New patch
---
Add another mux option for SDMMC1 direction pins, in particular
SDMMC1_D123DIR, this is used on AV96 board.
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
V2: New patch
---
arch/arm/dts/stm32mp157-pinctrl.dtsi | 24
1 file changed, 24
The eMMC uses different pinmux for the top four data lines, use such
a pinmux, otherwise it takes a very long time until the test for 8bit
operation times out. And this is the correct pinmux per schematic too.
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
V2: Update
The sdmmc1_dir_pins_a: sdmmc1-dir-0 layout changed in commit 35a54d41d9d4
("ARM: dts: stm32mp1: sync device tree with v5.2-rc4") such that pins{};
became pins1{};pins2{};, however the SPL extras were not updated to reflect
that change. Fix this.
This fixes booting from SD1 X9 slot on the AV96
This series fixes the Avenger96 board. Since there are way too many patches
floating around on the ML and because I found various other details that
needed fixing, I decided to bundle the whole set of fixes into this series.
This should go into current release, otherwise the board doesn't even
Enable QSPI for Agilex SoC devkit.
Signed-off-by: Ley Foon Tan
---
v2:
- Fixed missing ";".
---
arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
On 3/31/20 1:31 AM, Simon Glass wrote:
> Hi Marek,
Hi,
> On Sun, 22 Mar 2020 at 09:34, Marek Vasut wrote:
>>
>> On 3/22/20 4:17 PM, Simon Glass wrote:
>>> Hi Marek,
>>
>> Hi,
>>
>>> On Sat, 21 Mar 2020 at 20:15, Marek Vasut wrote:
On 3/22/20 3:08 AM, Simon Glass wrote:
> Hi
On 3/31/20 2:15 AM, Tan, Ley Foon wrote:
>>> On 3/27/20 9:24 AM, Ley Foon Tan wrote:
Enable QSPI for Agilex SoC devkit.
Signed-off-by: Ley Foon Tan
---
arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 4
1 file changed, 4
> > On 3/27/20 9:24 AM, Ley Foon Tan wrote:
> >> Enable QSPI for Agilex SoC devkit.
> >>
> >> Signed-off-by: Ley Foon Tan
> >> ---
> >> arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 4
> >> 1 file changed, 4 insertions(+)
> >>
> >> diff --git
Hi Niel,
On Mon, 30 Mar 2020 at 10:07, Niel Fourie wrote:
>
> Hi Simon
>
> On 3/28/20 9:05 PM, Simon Glass wrote:
> > Hi Niel,
> >
> > On Wed, 25 Mar 2020 at 07:47, Niel Fourie wrote:
> >>
> >> Expand warnings printed by Makefile after compile when legacy
> >> drivers are in use. These include:
On Sun, 29 Mar 2020 at 21:56, Kever Yang wrote:
>
> The tool need to use fdtdec_get_child_count(), make it available for
> HOST_CC.
>
> Signed-off-by: Kever Yang
> Reviewed-by: Punit Agrawal
> ---
>
> Changes in v4:
> - add function comment for fdtdec_get_child_count() in fdt_support.h
>
>
On Sun, 29 Mar 2020 at 11:59, Ovidiu Panait wrote:
>
> Move the ARM-specific reserve_mmu definition from common/board_f.c
> to arch/arm/lib/cache.c.
>
> Signed-off-by: Ovidiu Panait
> ---
> arch/arm/lib/cache.c | 28
> common/board_f.c | 28
On Sun, 29 Mar 2020 at 10:05, Dario Binacchi wrote:
>
> Add test case to cover dev_read_u64 and dev_read_u64_default functions.
>
> Signed-off-by: Dario Binacchi
> ---
>
> arch/sandbox/dts/test.dts | 1 +
> include/test/ut.h | 16
> test/dm/test-fdt.c| 10
On Sun, 29 Mar 2020 at 10:05, Dario Binacchi wrote:
>
> Now reading a 32 bit value from a device-tree property can be expressed
> as reading the first element of an array with a single value.
>
> Signed-off-by: Dario Binacchi
>
> ---
>
> drivers/core/of_access.c | 16 +---
>
On Sun, 29 Mar 2020 at 10:05, Dario Binacchi wrote:
>
> The patch adds helper functions to allow reading a single indexed u32
> value from a device-tree property containing multiple u32 values, that
> is an array of integers.
>
> Signed-off-by: Dario Binacchi
> ---
>
> arch/sandbox/dts/test.dts
On Sun, 29 Mar 2020 at 11:59, Ovidiu Panait wrote:
>
> Introduce arch_reserve_mmu to allow for architecture-specific reserve_mmu
> routines. Also, define a weak nop stub for it.
>
> Signed-off-by: Ovidiu Panait
> ---
> arch/arm/lib/cache.c | 2 +-
> common/board_f.c | 9 ++---
>
Hi Bin,
On Mon, 30 Mar 2020 at 03:42, Bin Meng wrote:
>
> Hi Simon,
>
> On Sun, Mar 29, 2020 at 4:58 AM Simon Glass wrote:
> >
> > Hi Bin,
> >
> > On Thu, 26 Mar 2020 at 10:38, Bin Meng wrote:
> > >
> > > Hi Simon,
> > >
> > > On Fri, Mar 27, 2020 at 12:20 AM Simon Glass wrote:
> > > >
> > >
Hi Ovidiu,
On Sun, 29 Mar 2020 at 11:59, Ovidiu Panait wrote:
>
> As a preparation for turning reserve_mmu into an arch-specific variant,
> introduce arm_reserve_mmu on ARM. It implements the default routine for
> reserving memory for MMU TLB and needs to be weakly defined in order to allow
>
From: Jway Lin
Add Cortina Access LED controller support for CA SOCs
Signed-off-by: Jway Lin
Signed-off-by: Alex Nemirovsky
CC: Simon Glass
---
Changes in v4:
- remove unused macros
- remove cortina prefix from macros
- remove use BSS variable
- further cleanup to meet code style
From: Pengpeng Chen
Add SPI Flash controller driver for Cortina Access
CA SoCs
Signed-off-by: Pengpeng Chen
Signed-off-by: Alex Nemirovsky
CC: Jagan Teki
CC: Vignesh R
---
Changes in v4: None
Changes in v3:
- Fixup syntax issues related to checkpatch.pl cleanup
Changes in v2: None
Add I2C board support for Cortina Access Presidio Engineering Board
Signed-off-by: Alex Nemirovsky
CC: Heiko Schocher
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
configs/cortina_presidio-asic-emmc_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git
From: Jway Lin
Add LED support for Cortina Access Presidio Engineering Board
Signed-off-by: Jway Lin
Signed-off-by: Alex Nemirovsky
Reviewed-by: Simon Glass
CC: Simon Glass
---
Changes in v4:
- rename DT blink rate symbol
Changes in v3: None
Changes in v2: None
Add SPI NAND and NOR support for Cortina Access
Presidio Engineering Board
Signed-off-by: Alex Nemirovsky
CC: Jagan Teki
CC: Vignesh R
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/dts/ca-presidio-engboard.dts| 8 ++--
From: Arthur Li
Add I2C controller support for Cortina Access CA SoCs
Signed-off-by: Arthur Li
Signed-off-by: Alex Nemirovsky
CC: Heiko Schocher
---
Changes in v4:
- Utilize standard I2C macros from
- Return ETIMEDOUT in funcs that can timeout
- Return i2c_xfer_init() result to caller
From: Arthur Li
Initial DesignWare based DM support for Cortina Access CA SoCs.
Signed-off-by: Arthur Li
Signed-off-by: Alex Nemirovsky
CC: Peng Fan
---
Changes in v4:
- Rename DT compatible name
- Remove uneccessary if-statement to support 8-bit buswidth
- Remove redundant error msg
-
Add initial eMMC support for Cortina Access Presidio
Engineering Board
Signed-off-by: Alex Nemirovsky
CC: Peng Fan
---
Changes in v4:
- Change DT compatiblity name to match change in driver's name
- Remove unused io_ds and fifo_mode fields from DT
Changes in v3: None
Changes in v2: None
Add Parallel NAND CA support to Cortina Access
Presidio Engineering Board support
Signed-off-by: Alex Nemirovsky
CC: Miquel Raynal
CC: Simon Glass
---
configs/cortina_presidio-asic-bch16_defconfig | 35 ++
configs/cortina_presidio-asic-bch24_defconfig | 36
This release adds the following drivers and
integrates support into the Cortina Access
Presidio Engineering Board:
CA SoC eMMC/SD controller
CA SoC I2C controller
CA Soc LED controller
CA SPI NAND and NOR controller
Changes in v4:
- Rename DT compatible name
- Remove
Hi Marek,
On Sun, 22 Mar 2020 at 09:34, Marek Vasut wrote:
>
> On 3/22/20 4:17 PM, Simon Glass wrote:
> > Hi Marek,
>
> Hi,
>
> > On Sat, 21 Mar 2020 at 20:15, Marek Vasut wrote:
> >>
> >> On 3/22/20 3:08 AM, Simon Glass wrote:
> >>> Hi Marek,
> >>
> >> Hi,
> >>
> >>> I think at this point
This is split from the original series in an attempt to get things applied
in chunks.
This section includes patches up to and including the 'acpi' command.
Changes in v3:
- Add a pointer to information about acpi,compatible
- Add forward declarations for the functions
- Add missing error check
On Mon, Mar 30, 2020 at 01:58:59PM +0200, Michal Simek wrote:
> Commit f4dc714aaa2d ("arm64: Turn u-boot.bin back into an ELF file after
> relocate-rela")
> introduce REMAKE_ELF option to recreate u-boot.elf from u-boot ->
> u-boot.bin + DT -> u-boot.elf.
>
> The best is to ilustrate it from
Hey all,
So, I've gotten out of the habit of tagging rcs on cycle. This month I
have been taking in changes sparingly and I'm not concerned that things
have gone in that wouldn't have, if I had tagged -rc4/rc5 on schedule.
Things have been going to the -next branch as expected, and I think
that
On Mon, Mar 30, 2020 at 11:56:24AM +0800, Kever Yang wrote:
> The image is usually stored in block device like emmc, SD card, make the
> offset of image data aligned to block(512 byte) can avoid data copy
> during boot process.
> eg. SPL boot from FIT image with external data:
> - SPL read the
On Mon, Mar 30, 2020 at 12:44:27PM +0530, Jagan Teki wrote:
> Hi Tom,
>
> Please pull this PR.
>
> Summary:
> - SPL SPI support R40, H6 (Andre)
> - eMMC boot part on a64-olinuxino (Petr)
>
> thanks,
> Jagan.
>
> The following changes since commit 3586cb82277e8af9eae38b354bb8b2aee38ee377:
>
>
On Mon, Mar 30, 2020 at 10:04:52AM +, Priyanka Jain wrote:
> Dear Tom,
>
> Please find my pull-request for u-boot-fsl-qoriq/master
> https://travis-ci.org/github/p-priyanka-jain/u-boot/builds/668558786
>
> I know this is a bit late in the window, sorry for that but these are some of
>
It is useful to dump ACPI tables in U-Boot to see what has been generated.
Add a command to handle this.
To allow the command to find the tables, add a position into the global
data.
Support subcommands to list and dump the tables.
Signed-off-by: Simon Glass
Reviewed-by: Wolfgang Wallner
---
Move this code to a generic location so that we can test it with sandbox.
This requires adding a few new fields to acpi_ctx, so drop the local
variables used in the original code.
Also use mapmem to avoid pointer-to-address casts which don't work on
sandbox.
Signed-off-by: Simon Glass
We don't actually support tables without an XSDT so we can drop this dead
code.
Signed-off-by: Simon Glass
Reviewed-by: Wolfgang Wallner
---
Changes in v3: None
Changes in v2: None
arch/x86/lib/acpi_table.c | 15 ++-
1 file changed, 2 insertions(+), 13 deletions(-)
diff --git
Put this in the context along with the other important pointers.
Signed-off-by: Simon Glass
Reviewed-by: Wolfgang Wallner
---
Changes in v3: None
Changes in v2: None
include/dm/acpi.h | 2 ++
lib/acpi/acpi_table.c | 10 --
test/dm/acpi.c| 5 +
3 files changed, 11
We always write three basic tables to ACPI at the start. Move this into
its own function, along with acpi_fill_header(), so we can write a test
for this code.
Signed-off-by: Simon Glass
---
Changes in v3:
- Beef up the comment explaining how the unaligned address is used
- Fix 'XDST' typo
-
Call the new core function to permit devices to write their own ACPI
tables. These tables will appear after all other tables.
Signed-off-by: Simon Glass
Reviewed-by: Wolfgang Wallner
---
Changes in v3: None
Changes in v2: None
arch/x86/lib/acpi_table.c | 2 ++
1 file changed, 2 insertions(+)
The current code uses an address but a pointer would result in fewer
casts. Also it repeats the alignment code in a lot of places so this would
be better done in a helper function.
Update write_acpi_tables() to make use of the new acpi_ctx structure,
adding a few helpers to clean things up.
A device may want to write out ACPI tables to describe itself to Linux.
Add a method to permit this.
Reviewed-by: Wolfgang Wallner
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2:
- Drop definition of ACPI_TABLE_CREATOR
- Generalise the ACPI function recursion with
The DMA Remapping Reporting (DMAR) table contains information about DMA
remapping.
Add a version simple version of this table with only the minimum fields
filled out. i.e. no entries.
Reviewed-by: Bin Meng
Signed-off-by: Simon Glass
---
Changes in v3:
- Add missing error check in
This file is potentially useful to other architectures saddled with ACPI
so move most of its contents to a common location.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Reviewed-by: Wolfgang Wallner
---
Changes in v3:
- Add forward declarations for the functions
- Move acpi_table.h to
Each ACPI table has its own version number. Add the version numbers in a
single function so we can keep them consistent and easily see what
versions are supported.
Start a new acpi_table file in a generic directory to house this function.
We can move things over to this file from x86 as needed.
Add this binding from Linux v5.4.
Signed-off-by: Simon Glass
---
Changes in v3:
- Split out hid-over-i2c into its own patch
Changes in v2: None
.../input/hid-over-i2c.txt| 44 +++
1 file changed, 44 insertions(+)
create mode 100644
This header relates to ACPI and we are about to add some more ACPI
headers. Move this one into a new directory so they are together.
Signed-off-by: Simon Glass
---
Changes in v3:
- Add new patch to move acpi_s3.h to include/acpi/
Changes in v2: None
arch/x86/cpu/apollolake/cpu_spl.c|
Since ut_asserteq_mem() uses bin2hex() we should include this header in
ut.h to avoid errors. Add it.
Signed-off-by: Simon Glass
---
Changes in v3:
- Add new patch to add hexdump.h to the unit test header
Changes in v2: None
include/test/ut.h | 1 +
1 file changed, 1 insertion(+)
diff --git
Devices need to report various identifiers in the ACPI tables. Rather than
hard-coding these in drivers it is typically better to put them in the
device tree.
Add a binding file to describe this.
Signed-off-by: Simon Glass
---
Changes in v3:
- Add a pointer to information about acpi,compatible
Add a sandbox test for the basic ACPI functionality we have so far.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Reviewed-by: Wolfgang Wallner
---
Changes in v3: None
Changes in v2:
- Add in the acpi_table.h header file to this patch
arch/sandbox/dts/test.dts | 4 ++
The ASL compiler cannot handle C structures and the like so needs some
sort of header guard around these.
We already have an __ASSEMBLY__ #define but it seems best to create a new
one for ACPI since the rules may be different.
Add the check to a few files that ACPI always includes.
ACPI (Advanced Configuration and Power Interface) is a standard for
specifying information about a platform. It is a little like device
tree but the bindings are part of the specification and it supports an
interpreted bytecode language.
Driver model does not use ACPI for U-Boot's configuration,
At present the cr50 driver claims the locality and does not release it for
Linux. This causes problems. Fix this by tracking what is claimed, and
adding a 'remove' method.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3: None
Changes in v2: None
drivers/tpm/cr50_i2c.c | 13
Some files are taken or modified from coreboot, but the files are
no-longer part of the coreboot project. Fix the wording in a few places.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Reviewed-by: Wolfgang Wallner
---
Changes in v3: None
Changes in v2: None
Add the C version of this header. It includes a few Chrome OS bits which
are disabled for a normal build.
Signed-off-by: Simon Glass
---
Changes in v3:
- Fix stray #endif
Changes in v2:
- Drop the Chrome OS pieces
- Rename the 'coreboot' console to 'U-Boot'
At present if reading a BAR returns 0x (e.g. the device is not
present) then the value is masked and a different value is returned.
This makes it harder to detect the problem when debugging.
Update the function to avoid masking in this case.
Signed-off-by: Simon Glass
Reviewed-by: Bin
With P2SB the initial BAR (base-address register) is set up by TPL and
this is used unchanged right through U-Boot.
At present the reading of this address is split between the ofdata() and
probe() methods. There are a few problems that are unique to the p2sb.
One is that its children need to call
With ACPI we need to describe the settings of the SPI bus. Add enums to
handle this.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Reviewed-by: Wolfgang Wallner
---
Changes in v3: None
Changes in v2:
- Add trailing commas to enum
- Don't bracket the definitions with DM_SPI
include/spi.h
Add a means to avoid configuring a device when needed. Add an explanation
of why this is useful to the binding file.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3:
- Drop acpi,name in example
Changes in v2: None
doc/device-tree-bindings/pci/x86-pci.txt | 23
This device should use ready-gpios rather than ready-gpio. Fix it.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3: None
Changes in v2: None
arch/x86/dts/chromebook_coral.dts | 2 +-
doc/device-tree-bindings/gpio/intel,apl-gpio.txt
Different CPUs may support different address widths, meaning the amount of
memory they can address. Add a property for this to the cpu_info struct.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3: None
Changes in v2: None
drivers/cpu/cpu_sandbox.c | 1 +
include/cpu.h
At present the cleanup() method is called on every transfer. It should
only be called on failing transfers. Fix this and tidy up the error
handling a little.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3: None
Changes in v2: None
drivers/tpm/tpm-uclass.c | 13
Add a comment for the private structure
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3: None
Changes in v2:
- Drop the other comment change since it is already applied
drivers/tpm/cr50_i2c.c | 9 +
1 file changed, 9 insertions(+)
diff --git
Hi,
On Wed, 18 Mar 2020 at 11:44, Simon Glass wrote:
>
> When booting a FIT, if 'bootm' is used without a specified configuration,
> U-Boot will use the default one provided in the FIT. But it does not
> actually check that the signature is for that configuration.
>
> This means that it is
On 3/30/20 4:26 AM, Heinrich Schuchardt wrote:
> %s/a EMMC/an eMMC/g
>
> Signed-off-by: Heinrich Schuchardt
Reviewed-by: Jaehoon Chung
Best Regards,
Jaehoon Chung
> ---
> cmd/mmc.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/cmd/mmc.c b/cmd/mmc.c
> index
Hi Tom,
> -Original Message-
> From: Eugeniy Paltsev
> Sent: Monday, March 30, 2020 10:45 PM
> To: uboot-snps-...@synopsys.com; Alexey Brodkin
> Cc: u-boot@lists.denx.de; Eugeniy Paltsev
> Subject: [PATCH v2 0/3] ARC: IO: rework IO accessors
>
> Fixing of DW SPI which was broken by
>
On Thu, Mar 26, 2020 at 6:25 AM Bryan O'Donoghue wrote:
>
> Linux commit 232ba3a51cc2 ('net: phy: Micrel KSZ8061: link failure after
> cable connect') implements a fix for the above errata.
>
> This patch replicates that errata fix in an ksz8061 specific init routine.
>
> Signed-off-by: Bryan
On Thu, Mar 26, 2020 at 9:01 AM Michal Simek wrote:
>
> When MACB_ZYNQ is enabled there is compilation warnings
> drivers/net/macb.c: In function ‘_macb_init’:
> drivers/net/macb.h:675:33: error: ‘MACB_DMACFG’ undeclared (first use in this
> function);
> did you mean ‘MACB_MCF’?
>
We must use compiler barriers in C-version read/write IO accessors
before and after operation (read or write) so it won't be reordered
by compiler.
Fixes commit 07906b3dad15 ("ARC: Switch to generic accessors")
Signed-off-by: Eugeniy Paltsev
---
arch/arc/include/asm/io.h | 31
We must use 'volatile' in C-version read/write IO accessors
implementation to avoid merging several reads (writes) into
one read (write), or optimizing them out by compiler.
Fixes commit 07906b3dad15 ("ARC: Switch to generic accessors")
Signed-off-by: Eugeniy Paltsev
---
We add memory barriers for __raw_readX / __raw_writeX accessors same
way as it is done for readX and writeX accessors as lots of U-boot
driver uses __raw_readX / __raw_writeX instead of proper accessor
with barrier.
It will save us from lot's of debugging in the future and it is OK
as U-Boot is
Fixing of DW SPI which was broken by
commit 07906b3dad15 ("ARC: Switch to generic accessors")
lead me to several fixes in ARC IO accessors code.
Eugeniy Paltsev (3):
ARC: IO: add volatile to accessors
ARC: IO: add compiler barriers to IO accessors
ARC: IO: add MB for __raw_* memory
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