From: Suneel Garapati
Add support for I2C controllers found on Octeon II/III and Octeon TX
TX2 SoC platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Suneel Garapati
Signed-off-by: Stefan Roese
Cc: Heiko Schocher
Cc: Simon Glass
Cc: Daniel Schwierzeck
Cc: Aaron Williams
Cc: Chandraka
Hi Marek,
> From: U-Boot On Behalf Of Patrick DELAUNAY
> Sent: mercredi 22 avril 2020 10:25
>
> Dear Marek,
>
> > From: Marek Vasut
> > Sent: vendredi 10 avril 2020 20:56
> >
> > Add default U-Boot configuration for the DHCOR SoM on AV96 board.
> >
> > Signed-off-by: Marek Vasut
> > Cc: Maniv
Hi,
> From: Marek Vasut
> Sent: mercredi 22 avril 2020 13:18
>
> Add default U-Boot configuration for the DHCOR SoM on AV96 board.
>
> Reviewed-by: Patrick Delaunay
> Signed-off-by: Marek Vasut
> Cc: Manivannan Sadhasivam
> Cc: Patrick Delaunay
> Cc: Patrice Chotard
> ---
> V2: No change
>
Hi,
> From: Marek Vasut
> Sent: mercredi 22 avril 2020 13:18
>
> The AV96 board does exist in multiple variants. To cater for all of them,
> implement
> board code handling. There are two GPIOs which code the type of the board,
> read
> them out and use the value to pick the correct device tre
Hi,
> From: Marek Vasut
> Sent: mercredi 22 avril 2020 13:18
>
> Add weak implementation of board_early_init_f() hook into the
> STM32MP1 SPL. This can be used to read out e.g. configuration straps before
> initializing the DRAM.
>
> Reviewed-by: Patrick Delaunay
> Signed-off-by: Marek Vasut
Hi,
> From: Marek Vasut
> Sent: mercredi 22 avril 2020 13:18
>
> Add support for multiple DRAM configuration subnodes, while retaining the
> support for a single flat DRAM configuration node. This is useful on systems
> which can be manufactured in multiple configurations and where the DRAM
> co
Hi,
> From: Marek Vasut
> Sent: mercredi 22 avril 2020 13:18
>
> Adjust the DDR configuration dtsi such that they only generate the DRAM
> configuration node, the DDR controller node is moved into the stm32mp157-u-
> boot.dtsi itself. This permits including multiple DDR configuration dtsi
> fil
Hi,
> From: Marek Vasut
> Sent: mercredi 22 avril 2020 13:18
>
> The DHCOR board does exist in multiple variants with different DDR3 DRAM
> sizes.
> To cater for all of them, implement DDR3 code handling.
> There are two GPIOs which code the DRAM size populated on the SoM, read them
> out and u
Hi Daniel,
On 13.05.20 14:49, Daniel Schwierzeck wrote:
sorry for the delay ;)
NP. I know that its sometimes not easy to find the time for this
maintainer / review job. ;)
Am 02.05.20 um 10:59 schrieb Stefan Roese:
From: Aaron Williams
This patch adds very basic support for the Octeon III
On 13.05.20 14:59, Daniel Schwierzeck wrote:
Am 02.05.20 um 10:59 schrieb Stefan Roese:
This patch enables the usage of CONFIG_MIPS_L2_CACHE without
CONFIG_MIPS_CM, which is what is needed for the newly added Octeon
platform.
Signed-off-by: Stefan Roese
---
arch/mips/lib/cache.c | 13
On 13.05.20 15:05, Daniel Schwierzeck wrote:
Am 02.05.20 um 10:59 schrieb Stefan Roese:
The Octeon platform is cache coherent and cache flushes and invalidates
are not needed. This patch makes use of the newly introduced Kconfig
option CONFIG_MIPS_CACHE_COHERENT to effectively disable all the
Simon,
On 05/05/20 12:20 pm, Faiz Abbas wrote:
> Hi,
>
> On 04/05/20 6:44 pm, Simon Glass wrote:
>> Hi Bart,
>>
>> On Mon, 4 May 2020 at 01:10, Bartosz Golaszewski wrote:
>>>
>>> pt., 1 maj 2020 o 20:32 Tom Rini napisał(a):
On Thu, Apr 30, 2020 at 01:43:30PM +0200, Bartosz Golaszewski
On 13.05.20 15:10, Daniel Schwierzeck wrote:
Am 02.05.20 um 10:59 schrieb Stefan Roese:
WG (bit 11) needs to be set on Octeon to enable writing bits 63:30 of
the exception base register.
Signed-off-by: Stefan Roese
---
arch/mips/lib/traps.c | 4
1 file changed, 4 insertions(+)
diff
Hi Simon,
-"Simon Glass" schrieb: -
> Betreff: [PATCH v2 05/35] acpi: Support generation of ACPI code
>
> Add a new file to handle generating ACPI code programatically. This is
> used when information must be dynamically added to the tables, e.g. the
> SSDT.
>
> Initial support is just
On 13.05.20 15:16, Daniel Schwierzeck wrote:
Am 02.05.20 um 10:59 schrieb Stefan Roese:
With the introduction of the MIPS Octeon support, lets use the newly
added Kconfig symbol CONFIG_CPU_MIPS64_OCTEON instead of the old Linux
CONFIG_CPU_CAVIUM_OCTEON one (which was never set). Remove these
r
On 13.05.20 16:47, Daniel Schwierzeck wrote:
Am 02.05.20 um 10:59 schrieb Stefan Roese:
This patch adds very basic minimal support for the Marvell Octeon 3
CN73xx based EBB7304 EVK. Please note that the basic Octeon port does
not support DDR3/4 initialization yet. To still use U-Boot on with t
Hi Tom,
Please have a look at the updates for RPi below.
I know I'm a bit late in the cycle. I'll try to send my pull requests earlier
next time, sorry for that.
I just pushed the tag, so the CI is not green yet:
https://travis-ci.org/github/mbgg/u-boot/builds/686914330
https://gitlab.denx.de/u-b
On 13.05.20 17:03, Daniel Schwierzeck wrote:
Am 02.05.20 um 10:59 schrieb Stefan Roese:
This patch adds a UCLASS_SYSRESET sysreset driver for the Octeon SoC
family.
Signed-off-by: Stefan Roese
---
drivers/sysreset/Kconfig | 7
drivers/sysreset/Makefile | 1 +
d
On 15/04/2020 21:59, Tom Rini wrote:
> On Tue, Apr 14, 2020 at 08:23:10PM -0600, Simon Glass wrote:
>> Hi,
>>
>> On Sun, 22 Mar 2020 at 21:16, Simon Glass wrote:
>>>
>>> At present the pinctrl nodes are not enabled in pre-relocation U-Boot so
>>> the UARTs do not correctly select the pinconfig
On 14.05.20 01:43, Daniel Schwierzeck wrote:
Am 02.05.20 um 10:59 schrieb Stefan Roese:
From: Aaron Williams
This patch adds very basic support for the Octeon III SoCs. Only
CFI parallel NOR flash and UART is supported for now.
Please note that the basic Octeon port does not include the DDR
Hi,
> From: Patrick DELAUNAY
> Sent: mercredi 18 mars 2020 09:23
>
>
> This serie migrate the dynamically build MTD
> (CONFIG_SYS_MTDPARTS_RUNTIME) and the DFU configuration
> (CONFIG_SET_DFU_ALT_INFO) previously based on ENV variables to
> CONFIG_.
>
> These patches reduce the size of the env
Hi,
> From: Patrick DELAUNAY
> Sent: mercredi 18 mars 2020 09:25
>
>
> Add a specific command stm32prog for STM32MP soc family witch allows to
> update the devices on the board with the STMicroelectronics tool
> STM32CubeProgrammer (http://www.st.com/STM32CubeProg).
>
> This command use the sa
Hi Simon,
On 29.04.20 20:04, Simon Glass wrote:
On Wed, 29 Apr 2020 at 01:08, Stefan Roese wrote:
Including the assembler headers before including common.h etc leads to
compilation errors upon MIPS64 based platforms using OF_LIVE. This
patch reorders the include files to the "correct" oder.
Hi,
> From: Patrick DELAUNAY
> Sent: mercredi 22 avril 2020 14:29
>
>
> It is a V2 for the serie
> http://patchwork.ozlabs.org/project/uboot/list/?series=167872
>
> Rebased on master branch and after the first reviews:
>
> [01/16] arm: stm32mp: update dependency for STM32_ETZPC
> is already
Hi Patrice
> From: Patrice CHOTARD
> Sent: jeudi 30 avril 2020 18:41
>
> On DK1/2 board, when a 1.5A power supply is detected, a warning message is
> displayed. In this message, "1.5mA" is displayed instead of "1.5A".
>
> Signed-off-by: Patrice Chotard
> ---
>
> board/st/stm32mp1/stm32mp1.c
Hi,
> From: Marek Vasut
> Sent: lundi 27 avril 2020 13:16
>
> The commit 132e5b68986d ("ARM: dts: stm32: Split AV96 into DHCOR SoM and
> AV96 board") was not applied correctly and in full, and omitted an important
> split
> of the SoM into 3V3 and 1V8 options. The Avenger96 board is based on th
Hi Marek,
> From: Marek Vasut
> Sent: mercredi 29 avril 2020 15:09
>
> Add custom DDR DRAM settings for the DHCOR and DHCOM SoMs and put
> them into use by the board file instead of the default ones. These new DRAM
> settings are a better fit for the SoMs.
>
> Signed-off-by: Marek Vasut
> Cc:
Hi,
> From: Marek Vasut
> Sent: lundi 27 avril 2020 12:27
>
> Define I2C EEPROM bus and address, so that the 'eeprom' command uses the
> correct ones and does not generate the following error:
> eeprom_rw_block: Cannot find udev for a bus 0
>
> Signed-off-by: Marek Vasut
> Cc: Patrick Dela
Hi
> From: Marek Vasut
> Sent: lundi 27 avril 2020 12:27
>
> The SPI NOR nWP line is connected to GPIO PF7 on the SoM, pull the GPIO line
> high by default to clear SPI NOR WP.
>
> Signed-off-by: Marek Vasut
> Cc: Patrick Delaunay
> Cc: Patrice Chotard
> ---
> arch/arm/dts/stm32mp15xx-dhcom
Hi,
> From: Patrick DELAUNAY
> Sent: jeudi 30 avril 2020 16:30
>
> Activate the data cache in SPL and in U-Boot before relocation.
>
> In arch_cpu_init(), the function early_enable_caches() sets the early TLB,
> early_tlb[] located .init section, and set cacheable:
> - for SPL, all the SYSRAM
>
Hi
> From: Patrick DELAUNAY
> Sent: jeudi 30 avril 2020 16:30
>
> Activate cache on DDR to improve the accesses to DDR used by SPL:
> - CONFIG_SPL_BSS_START_ADDR
> - CONFIG_SYS_SPL_MALLOC_START
>
> Cache is configured only when DDR is fully initialized, to avoid speculative
> access
> and issu
Hi,
> From: Patrick DELAUNAY
> Sent: jeudi 30 avril 2020 09:52
>
> Change the mmc displayed name in U-Boot for stm32_sdmmc2 driver to
> “STM32 SD/MMC”.
>
> This stm32_sdmmc2 driver is for version 2 of the ST HW IP SDMMC but the
> displayed name "STM32 SDMMC2" is confusing for user, between the
Hi,
> From: Patrick DELAUNAY
> Sent: vendredi 24 avril 2020 15:48
> To: u-boot@lists.denx.de
> Cc: Lionel DEBIEVE ; Patrick DELAUNAY
> ; Lukasz Majewski ; Patrice
> CHOTARD ; U-Boot STM32 mailman.stormreply.com>
> Subject: [PATCH] clk: stm32mp1: fix CK_MPU calculation
> Importance: High
>
> Fro
Hi,
> From: Patrick DELAUNAY
> Sent: jeudi 30 avril 2020 15:53
> To: u-boot@lists.denx.de
> Cc: Patrick DELAUNAY ; Marek Vasut
> ; Tom Rini ; U-Boot STM32 st...@st-md-mailman.stormreply.com>
> Subject: [PATCH] ARM: dts: stm32mp1: DT alignment with Linux 5.7-rc2
> Importance: High
>
> DT alignme
> -Original Message-
> From: Priyanka Jain (OSS)
> Sent: Tuesday, May 12, 2020 2:57 PM
> To: Chaitanya Sakinam ; u-
> b...@lists.denx.de; joe.hershber...@ni.com
> Cc: bmeng...@gmail.com; Alexandru Marginean
> ; s...@chromium.org; Z.q. Hou
> ; Andy Tang ;
> tommyh...@gmail.com; Anji Jaga
This Kconfig symbol will be introduced with the base Octeon MIPS support.
Using it, its possible to use a TEXT_BASE address which differs from
the reset PC. And with the earliest function call to mips_sram_init()
the CPU will transfer execution to the actual TEXT_BASE region. So after
returning fro
This patch adds very basic support for the Octeon III SoCs. Only CFI
parallel UART, reset and NOR flash are supported for now.
Please note that the basic Octeon port does not include the DDR3/4
initialization yet. This will be added in some follow-up patches later.
To still use U-Boot on with th
This patch adds __weak to flush_cache() in lib/cache.c. This makes it
possible to overwrite this function by a platforms specific version,
like done with the Octeon base port.
Signed-off-by: Stefan Roese
---
Changes in v2:
- New patch
arch/mips/lib/cache.c | 2 +-
1 file changed, 1 insertion(
This patch enables the usage of CONFIG_MIPS_L2_CACHE without
CONFIG_MIPS_CM, which is what is needed for the newly added Octeon
platform.
Signed-off-by: Stefan Roese
---
Changes in v2:
- Restructure patch by adding empty functions to asm/cm.h instead
arch/mips/include/asm/cm.h | 12 ++
This patch opts-out the compilation of get_tbclk() if
CONFIG_SYS_MIPS_TIMER_FREQ is not defined. This is used on the Octeon
platform, where the weak get_tbclk() function is overwritten by its
platform specific one.
Signed-off-by: Stefan Roese
---
Changes in v2:
- New patch
arch/mips/cpu/time.
From: Aaron Williams
Thips patch adds some more register definitions which will be used by
the Octeon platform.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
Changes in v2: None
arch/mips/include/asm/mipsregs.h | 19 ++-
1 file changed, 18 insertions(+), 1 de
This patch adds the base dtsi file for the Octeon 3 cn73xx SoC.
Signed-off-by: Stefan Roese
---
Changes in v2: None
MAINTAINERS| 1 +
arch/mips/dts/mrvl,cn73xx.dtsi | 64 ++
2 files changed, 65 insertions(+)
create mode 100644 arch/mips/dts
This patch adds a UCLASS_SYSRESET sysreset driver for the Octeon SoC
family.
Signed-off-by: Stefan Roese
---
Changes in v2: None
drivers/sysreset/Kconfig | 7
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_octeon.c | 52 ++
3 fi
WG (bit 11) needs to be set on Octeon to enable writing bits 63:30 of
the exception base register.
Signed-off-by: Stefan Roese
---
Changes in v2:
- Move bit macro definition to mipsregs.h
arch/mips/include/asm/mipsregs.h | 1 +
arch/mips/lib/traps.c| 4
2 files changed, 5 ins
Since Octeon now runs from L2 cache, we can't reset the cache at this
time. So let's opt-out this function on Octeon, as the cache is
coherent on Octeon anyways.
Signed-off-by: Stefan Roese
---
Changes in v2:
- New patch
arch/mips/cpu/start.S | 2 ++
1 file changed, 2 insertions(+)
diff --gi
From: Aaron Williams
This patch adds very basic support for the Octeon III SoCs. Only
CFI parallel NOR flash and UART is supported for now.
Please note that the basic Octeon port does not include the DDR3/4
initialization yet. This will be added in some follow-up patches
later. To still use U-Bo
This patch adds very basic minimal support for the Marvell Octeon 3
CN73xx based EBB7304 EVK. Please note that the basic Octeon port does
not support DDR3/4 initialization yet. To still use U-Boot on with this
port, the L2 cache (4MiB) is used as RAM. This way, U-Boot can boot
to the prompt on this
Using .set mips3/32/64 without .set push/pop is fragile. This patch
solves this issue by sync'ing the inline-asm functions with the
latest Linux ones.
Signed-off-by: Stefan Roese
---
Changes in v2: None
arch/mips/include/asm/mipsregs.h | 44 +++-
1 file changed, 26
Hi Tom,
Please pull the STM32 related fixes for v2020.07-rc3 = u-boot-stm32-20200514
With the following changes:
- stm32mp1: migrate MTD and DFU configuration in Kconfig
- stm32mp1: add command stm32prog
- stm32mp1: several board and arch updates
- stm32mp1: activate data cache in SPL and
Added a misc driver to handle OTP memory in SiFive SoCs.
Signed-off-by: Pragnesh Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
drivers/misc/Kconfig | 7 +
drivers/misc/Makefile | 1 +
drivers/misc/sifive-otp.c | 273 ++
3 files changed, 28
Use the OTP DM driver to set the serial environment variable.
Signed-off-by: Pragnesh Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
arch/riscv/dts/fu540-c000-u-boot.dtsi | 14 +++
.../dts/hifive-unleashed-a00-u-boot.dtsi | 2 +
board/sifive/fu540/Kconfig
For SPL_SEPARATE_BSS, Device tree will be put at _image_binary_end
Signed-off-by: Pragnesh Patel
Reviewed-by: Anup Patel
Reviewed-by: Jagan Teki
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
arch/riscv/cpu/u-boot-spl.lds | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/cpu/u-bo
This series add support for SPL to FU540. U-Boot SPL can boot from
L2 LIM (0x0800_) and jump to OpenSBI(FW_DYNAMIC firmware) and
U-Boot proper from MMC devices.
This series depends on:
[1] https://patchwork.ozlabs.org/patch/1281853
[2] https://patchwork.ozlabs.org/patch/1281852
All these toge
Devicetree files in FU540 platform is synced from Linux, like other
platforms does. Apart from these U-Boot in FU540 would also require
some U-Boot specific node like clint.
So, create board specific -u-boot.dtsi files. This would help of
maintain U-Boot specific changes separately without touchin
When build U-Boot SPL, meet an issue of undefined reference to
'crc7' for drivers/mmc/mmc_spi.c, so let's compile crc7.c when
CONFIG_MMC_SPI selected.
Signed-off-by: Pragnesh Patel
Reviewed-by: Heinrich Schuchardt
---
lib/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --gi
Add DDR controller and phy register settings, taken from fsbl
(https://github.com/sifive/freedom-u540-c000-bootloader.git)
Signed-off-by: Pragnesh Patel
---
.../dts/fu540-hifive-unleashed-a00-ddr.dtsi | 1489 +
1 file changed, 1489 insertions(+)
create mode 100644 arch/riscv/d
Add driver for fu540 to support ddr initialization in SPL.
This driver is based on FSBL
(https://github.com/sifive/freedom-u540-c000-bootloader.git)
Signed-off-by: Pragnesh Patel
---
board/sifive/fu540/Kconfig | 2 +
drivers/ram/Kconfig| 1 +
drivers/ram/Makefile |
Add dmc node to enable ddr driver. dmc is used to
initialize the memory controller.
Signed-off-by: Pragnesh Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
arch/riscv/dts/fu540-c000-u-boot.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dt
Release ethernet clock reset once clock is initialized.
This is necessary to do as U-Boot proper needs ethernet
clock.
Signed-off-by: Pragnesh Patel
---
drivers/clk/sifive/fu540-prci.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/clk/sifive/fu540-prci.c b/dri
Added clock enable and disable functions in prci ops
Signed-off-by: Pragnesh Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
drivers/clk/sifive/fu540-prci.c | 108
1 file changed, 96 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/sifive/fu540-prci
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel
---
arch/riscv/Kconfig | 1 +
arch/riscv/cpu/fu540/Kconfig | 15 ++
arch/riscv/cpu/fu540/Makefile| 7 +
arch/riscv/cpu/fu540/cpu.c | 22
This sync has changes required to use GPIO in U-Boot and
U-Boot SPL.
Sync dts from linux v5.7-rc2 commit:
"riscv: dts: Add GPIO reboot method to HiFive Unleashed DTS file"
(sha1: 0a91330b2af9f71cd483f92774182b58f6d9)
Signed-off-by: Pragnesh Patel
Reviewed-by: Bin Meng
---
arch/riscv/dts/fu
Release ddr clock reset once clock is initialized
Signed-off-by: Pragnesh Patel
---
drivers/clk/sifive/fu540-prci.c | 51 +
1 file changed, 45 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index bf06c
From: Jagan Teki
This is a sample GPT partition layout for SD card,
right now three important partitions are added to
make the system bootable.
partition layout:
PartStart LBA End LBA Name
Attributes
Type GUID
Partition GUID
1 0x0022 0x00
From: Jagan Teki
Add U-Boot proper sector start offset for SiFive FU540.
This value is based on the partition layout supported
by SiFive FU540.
u-boot.itb need to write on this specific offset so-that
the SPL will retrieve it from here and load.
Signed-off-by: Jagan Teki
Reviewed-by: Bin Meng
OpenSBI generic platform support provides platform specific
functionality based on the FDT passed by previous booting stage.
Depends on OpenSBI commit:
platform: Add generic FDT based platform support
(sha1: f1aa9e54e6ae70aeac638d5b75093520f65d)
Signed-off-by: Pragnesh Patel
---
doc/board/s
Add a support for SPL which will boot from L2 LIM (0x0800_) and
then SPL will boot U-Boot FIT image (OpenSBI FW_DYNAMIC + u-boot.bin)
from MMC boot devices.
SPL related code is leveraged from FSBL
(https://github.com/sifive/freedom-u540-c000-bootloader.git)
Signed-off-by: Pragnesh Patel
Revi
With sifive_fu540_defconfig:
User can use FSBL or u-boot-spl.bin anyone at a time.
For FSBL,
fsbl->fw_payload.bin (opensbi + U-Boot)
For u-boot-spl.bin,
u-boot-spl.bin->FIT image (opensbi + U-Boot proper + dtb)
U-Boot SPL will be loaded by ZSBL from SD card (replace fsbl.bin with
u-boot-spl.bin
The new pointer points to flash found and that would
assign it to global 'flash' pointer for further flash
operations and also keep track of old flash pointer.
This would happen if the probe is successful or even
failed, but current code assigning new into flash before
and after checking the new.
Currently spi-nor code is assigning _write ops for SST
and other flashes separately.
Just call the sst_write from generic write ops and return
if SST flash found, this way it avoids the confusion of
multiple write ops assignment during the scan and makes
it more feasible for code readability.
No
Cleanup of SF, no precise functionality changes.
Any inputs?
Jagan.
Jagan Teki (5):
mtd: spi: Call sst_write in _write ops
cmd: sf Drop reassignment of new into flash
env: sf: Preserve and free the previous flash
mtd: sf: Drop plat from sf_probe
mtd: spi: Use IS_ENABLED to prevent ifde
env_flash is a global flash pointer, and the probe would
happen only if env_flash is NULL, but there is no checking
and free the pointer if is not NULL.
So, this patch frees the env_flash if it's not NULL, and
get the probed flash in new flash pointer and finally
assign into env_flash.
Note: Simi
dm_spi_slave_platdata used in sf_probe for printing
plat->cs value and there is no relevant usage apart
from this.
We have enouch debug messages available in SPI and SF
areas so drop this plat get and associated bug statement.
Cc: Simon Glass
Cc: Vignesh R
Signed-off-by: Jagan Teki
---
driver
Use IS_ENABLED to prevent ifdef in sf_probe.c
Cc: Simon Glass
Cc: Vignesh R
Cc: Daniel Schwierzeck
Signed-off-by: Jagan Teki
---
drivers/mtd/spi/sf_internal.h | 10 ++
drivers/mtd/spi/sf_probe.c| 17 -
2 files changed, 18 insertions(+), 9 deletions(-)
diff --git a
In order to update our to a newer version that no
longer provides ACCESS_ONCE() but only READ_ONCE()/WRITE_ONCE() we need
to convert arch/arm/mach-tegra/ivc.c to the other macros.
Cc: Tom Warren
Signed-off-by: Tom Rini
---
arch/arm/mach-tegra/ivc.c | 20 ++--
1 file changed, 10
Borrowing from Linux commit 78a5255ffb6a ("Stop the ad-hoc games with
-Wno-maybe-initialized")
move to have maybe-initialized warnings be handled with building with
W=2 instead of playing more guessing games with newer compilers.
Signed-off-by: Tom Rini
---
Makefile | 3 +++
1 file changed, 3 i
In order to update our to a newer version that no
longer provides ACCESS_ONCE() but only READ_ONCE()/WRITE_ONCE() we need
to convert arch/x86/include/asm/atomic.h to the other macros.
Cc: Simon Glass
Cc: Bin Meng
Signed-off-by: Tom Rini
---
arch/x86/include/asm/atomic.h | 2 +-
1 file changed
As part of re-syncing our Kconfig logic up to v4.19, we had missed
adding this new file that includes helper macros. To quote the upstream
commit e1cfdc0e72fc ("kconfig: add basic helper macros to
scripts/Kconfig.include"):
Kconfig got text processing tools like we see in Make. Add Kconfig
help
Enable the new CONFIG_OPTIMIZE_INLINING and CONFIG_SPL_OPTIMIZE_INLINING
options for this platform. With gcc-9.2 from kernel.org this saves us
1784 bytes in U-Boot and 80 bytes in SPL.
Cc: Marek Vasut
Cc: Chin-Liang See
Cc: Dinh Nguyen
Signed-off-by: Tom Rini
---
configs/socfpga_stratix10_de
In the Linux kernel, support for forcing inline functions to be made
inline, rather than allowing the compiler to make its own choice has
been removed. With respect to performance, modern GCC (and Clang) do a
good job at deciding when to, or not to, inline code and there are no
run-time requiremen
Unless we mark the function as 'static inline' it may end up being
non-inlined by the compiled and result in duplicate functions.
Cc: Marek Vasut
Cc: Simon Goldschmidt
Cc: Ley Foon Tan
Signed-off-by: Tom Rini
---
arch/arm/mach-socfpga/include/mach/misc.h | 2 +-
1 file changed, 1 insertion(+)
There are cases where when we allow the compiler to decide about making
inline decisions rather than forcing them it can save us space.
For now, we keep the default values for inlining that we have had
historically.
Cc: Masahiro Yamada
Signed-off-by: Tom Rini
---
Kconfig
Copy these from Linux v5.7-rc5 tag.
This brings in some handy new attributes and is otherwise important to
keep in sync.
We drop the reference to smp_read_barrier_depends() as it is not
relevant on the architectures we support at this time, based on where
it's implemented in Linux today. We drop
A large number of changes have happened upstream since our last sync
in commit 65e05ddc1ae2 ("kconfiglib: Update to the 12.14.0 release").
The big motivation for this sync is support for user defined macros
within Kconfig.
Cc: Masahiro Yamada
Signed-off-by: Tom Rini
---
tools/buildman/kconfigl
Tested-by: Angelo Dureghello
Environment size: 680/8188 bytes
stmark2 $ bdi
boot_params = 0x47d96770
DRAM bank = 0x
-> start= 0x4000
-> size = 0x0800
memstart= 0x4000
memsize = 0x0800
flashstart = 0x
flashsize = 0x
flashoffset = 0x0
I'm bringing up efiboot on a ARM64 board which runs without TF-a and PSCI,
therefore the secondary cores are brought up by spin-tables. I ran into
several problems. Here are the fixes.
Michael Walle (4):
efi_loader: aarch64: align runtime section to 64kb
efi_loader: check alignment in efi_add_
The start parameter must be aligned to EFI_PAGE_SIZE.
Fixes: 5a37a2f0140c ("armv8: ls2080a: Declare spin tables as reserved for efi
loader")
Signed-off-by: Michael Walle
---
arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/
The first argument has to be aligned with EFI_PAGE_SIZE. This alignment
is already checked for external callers but it is not checked for
internal callers. Unfortunately, most of the time the return value is
not checked, so scream loud and clear.
Signed-off-by: Michael Walle
---
lib/efi_loader/e
Commit 7a82c3051c8f ("efi_loader: Align runtime section to 64kb")
already aligned the memory region to 64kb, but it does not align the
actual efi runtime code. Thus it is likely, that efi_add_memory_map()
actually adds a larger memory region than the efi runtime code really
is, which is no error I
On some architectures, specifically the layerscape, the secondary cores
wait for an interrupt before entering the spin-tables. This applies only
to boards which doesn't have PSCI provided by TF-a and u-boot does the
secondary cores handling.
bootm/booti already call that function for ARM architectu
How can I use TPM in u-boot for secure boot ?
U-Boot has TPM support and it provide some driver support and commands.
I have enabled TPM support in u-boot.
But I don't know how to use it ?
Have anybody used TPM in uboot ?
--
Sent from: http://u-boot.10912.n7.nabble.com/
CC: ja...@amarulasolutions.com
вт, 12 мая 2020 г. в 21:25, Roman Stratiienko :
>
> H6 SOC needs additional initialization of PHY registers. Corresponding
> changes can be found in the kernel patch [1].
>
> Without this changes there is no enumeration of 'musb' gadget.
>
> [1] -
> https://git.ker
CC: ja...@amarulasolutions.com
пт, 8 мая 2020 г. в 15:29, Roman Stratiienko :
>
> Same was done in the kernel for all devices compatible with
> 'allwinner,sun8i-a33-musb' at [1] and [2].
>
> Fixes musb initialization on H6 SOC.
>
> [1] -
> https://git.kernel.org/pub/scm/linux/kernel/git/stable/li
Update the compatible associated with the STM32 MPU glue
in the DWC ethernet driver.
The supported compatible is the specific "st,stm32mp1-dwmac"
as indicated in Linux binding
Documentation/devicetree/bindings/net/stm32-dwmac.txt
and not the "snps,dwmac-4.20a" only used to the select IP
version.
Hi Stefan,
OK. Feel free to pull it in if you like as you have my review tag.
Regards,
SImon
On Thu, 14 May 2020 at 03:30, Stefan Roese wrote:
>
> Hi Simon,
>
> On 29.04.20 20:04, Simon Glass wrote:
> > On Wed, 29 Apr 2020 at 01:08, Stefan Roese wrote:
> >>
> >> Including the assembler headers
The get_sw_write_prot API is used to get the write-protected
bits of flash by reading the status register and other wards
it's API for reading register bits.
1) This kind of requirement can be achieved using existing
flash operations and flash locking API calls instead of
making a separate f
Hi Simon,
On 14.05.20 14:49, Simon Glass wrote:
OK. Feel free to pull it in if you like as you have my review tag.
Thanks Simon. Since Daniel will be the one pulling the Octeon patchset
once we've reached the necessary ack's, he now knows that he can pull
this one as well. But this will take a
Update the compatible associated with the STM32 MPU glue
in the DWC ethernet driver.
The supported compatible is the specific "st,stm32mp1-dwmac"
as indicated in Linux binding
Documentation/devicetree/bindings/net/stm32-dwmac.txt
and not the "snps,dwmac-4.20a" only used to the select IP
version.
Signed-off-by: Christian Gmeiner
---
arch/x86/cpu/coreboot/tables.c | 14 ++
arch/x86/include/asm/arch-coreboot/sysinfo.h | 2 ++
arch/x86/include/asm/coreboot_tables.h | 11 +++
3 files changed, 27 insertions(+)
diff --git a/arch/x86/cpu/coreboot/tables.
UCLASS_SPI_FLASH driver at driver/mtd/spi is a generic
spi flash driver to probe jedec,spi-nor flash chips.
Technically a probe call in U_BOOT_DRIVER is local to that
driver and not applicable to use it another driver or in
another code.
The apollolake SPL code using the generic probe by adding
e
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