This series add support for SPL to FU540. U-Boot SPL can boot from
L2 LIM (0x0800_) and jump to OpenSBI(FW_DYNAMIC firmware) and
U-Boot proper from MMC devices.
This series is also available here [1] for testing
[1] https://github.com/pragnesh26992/u-boot/tree/spl
How to test this patch:
1) G
Use the OTP DM driver to set the serial environment variable.
Signed-off-by: Pragnesh Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Reviewed-by: Jagan Teki
Tested-by: Jagan Teki
---
arch/riscv/dts/fu540-c000-u-boot.dtsi | 14 +++
.../dts/hifive-unleashed-a00-u-boot.dtsi | 2
Added a misc driver to handle OTP memory in SiFive SoCs.
Signed-off-by: Pragnesh Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Reviewed-by: Jagan Teki
Tested-by: Jagan Teki
---
drivers/misc/Kconfig | 7 +
drivers/misc/Makefile | 1 +
drivers/misc/sifive-otp.c | 275 +++
When build U-Boot SPL, meet an issue of undefined reference to
'crc7' for drivers/mmc/mmc_spi.c, so let's compile crc7.c when
CONFIG_MMC_SPI selected.
Signed-off-by: Pragnesh Patel
Reviewed-by: Heinrich Schuchardt
Reviewed-by: Bin Meng
Acked-by: Jagan Teki
---
lib/Makefile | 2 +-
1 file chan
Devicetree files in FU540 platform is synced from Linux, like other
platforms does. Apart from these U-Boot in FU540 would also require
some U-Boot specific node like clint.
So, create board specific -u-boot.dtsi files. This would help of
maintain U-Boot specific changes separately without touchin
For SPL_SEPARATE_BSS, Device tree will be put at _image_binary_end
Signed-off-by: Pragnesh Patel
Reviewed-by: Anup Patel
Reviewed-by: Jagan Teki
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Tested-by: Jagan Teki
---
arch/riscv/cpu/u-boot-spl.lds | 1 +
1 file changed, 1 insertion(+)
diff --gi
Add dmc node to enable ddr driver. dmc is used to
initialize the memory controller.
Signed-off-by: Pragnesh Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Reviewed-by: Jagan Teki
Tested-by: Jagan Teki
---
arch/riscv/dts/fu540-c000-u-boot.dtsi | 9 +
1 file changed, 9 insertions(+)
Add driver for fu540 to support ddr initialization in SPL.
This driver is based on FSBL
(https://github.com/sifive/freedom-u540-c000-bootloader.git)
Signed-off-by: Pragnesh Patel
Tested-by: Bin Meng
---
board/sifive/fu540/Kconfig | 2 +
drivers/ram/Kconfig| 1 +
drivers/ram/
Added clock enable and disable functions in prci ops
Signed-off-by: Pragnesh Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Acked-by: Jagan Teki
Tested-by: Jagan Teki
---
drivers/clk/sifive/fu540-prci.c | 108
1 file changed, 96 insertions(+), 12 deletions(-
Add DDR controller and phy register settings, taken from fsbl
(https://github.com/sifive/freedom-u540-c000-bootloader.git)
Signed-off-by: Pragnesh Patel
Tested-by: Bin Meng
Reviewed-by: Jagan Teki
Tested-by: Jagan Teki
---
.../dts/fu540-hifive-unleashed-a00-ddr.dtsi | 1489 +
Release ddr clock reset once clock is initialized
Signed-off-by: Pragnesh Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Reviewed-by: Jagan Teki
Tested-by: Jagan Teki
---
drivers/clk/sifive/fu540-prci.c | 51 +
1 file changed, 45 insertions(+), 6 deletions(-)
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Reviewed-by: Jagan Teki
Tested-by: Jagan Teki
---
arch/riscv/Kconfig | 1 +
arch/riscv/cpu/fu540/Kconfig | 15 ++
arch/riscv/cpu/fu54
U-Boot ethernet works with FSBL flow where releasing ethernet clock
reset is part of FSBL itself but with the SPL, We need to release
ethernet clock reset explicitly for U-Boot proper. With this change
Release ethernet clock reset code in FSBL might not be needed or
unaffected.
Signed-off-by: Prag
From: Jagan Teki
This is a sample GPT partition layout for SD card,
right now three important partitions are added to
make the system bootable.
partition layout:
PartStart LBA End LBA Name
Attributes
Type GUID
Partition GUID
1 0x0022 0x00
From: Jagan Teki
Add U-Boot proper sector start offset for SiFive FU540.
This value is based on the partition layout supported
by SiFive FU540.
u-boot.itb need to write on this specific offset so-that
the SPL will retrieve it from here and load.
Signed-off-by: Jagan Teki
Reviewed-by: Bin Meng
Add a support for SPL which will boot from L2 LIM (0x0800_) and
then SPL will boot U-Boot FIT image (OpenSBI FW_DYNAMIC + u-boot.bin)
from MMC boot devices.
SPL related code is leveraged from FSBL
(https://github.com/sifive/freedom-u540-c000-bootloader.git)
Signed-off-by: Pragnesh Patel
Revi
This sync has changes required to use GPIO in U-Boot and
U-Boot SPL.
Sync dts from linux v5.7-rc2 commit:
"riscv: dts: Add GPIO reboot method to HiFive Unleashed DTS file"
(sha1: 0a91330b2af9f71cd483f92774182b58f6d9)
Signed-off-by: Pragnesh Patel
Reviewed-by: Bin Meng
Reviewed-by: Jagan Tek
With sifive_fu540_defconfig:
User can use FSBL or u-boot-spl.bin anyone at a time.
For FSBL,
fsbl->fw_payload.bin (opensbi + U-Boot)
For u-boot-spl.bin,
u-boot-spl.bin->FIT image (opensbi + U-Boot proper + dtb)
U-Boot SPL will be loaded by ZSBL from SD card (replace fsbl.bin with
u-boot-spl.bin
OpenSBI generic platform support provides platform specific
functionality based on the FDT passed by previous booting stage.
Depends on OpenSBI commit:
platform: Add generic FDT based platform support
(sha1: f1aa9e54e6ae70aeac638d5b75093520f65d)
Signed-off-by: Pragnesh Patel
Reviewed-by: Bin
Hi Masahiro
On 5/20/20 5:45 PM, Masahiro Yamada wrote:
> On Wed, May 20, 2020 at 10:50 PM Patrice CHOTARD
> wrote:
>> Hi Masahiro
>>
>> As indicated into doc/README.fdt-control, it's possible build U-boot with
>> specifying dts-file-name using
>> $ make DEVICE_TREE=
>
> I think this doc might b
On Mon, May 25, 2020 at 2:55 AM Hugh Cole-Baker wrote:
>
>
>
> > On 24 May 2020, at 20:00, Suniel Mahesh wrote:
> >
> >
> >
> > On Sun, May 24, 2020 at 3:52 PM Hugh Cole-Baker wrote:
> >
> > > On 20 May 2020, at 13:08, Jagan Teki wrote:
> > >
> > > It seems like SPI boot on rk3399 with TPL base
On Thu, May 14, 2020 at 6:21 PM Jagan Teki wrote:
>
> The get_sw_write_prot API is used to get the write-protected
> bits of flash by reading the status register and other wards
> it's API for reading register bits.
>
> 1) This kind of requirement can be achieved using existing
>flash operatio
Hi Tom,
Please pull some riscv updates:
- Add Sipeed Maix support.
- sifive: fix palmer's email address.
- Move all SMP related SBI calls to SBI_v01.
https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/690778926
Thanks
Rick
The following changes since commit 9c5fef577494769e3ff07952a8
Hi Simon,
On Fri, May 22, 2020 at 10:20 PM Simon Glass wrote:
>
> Hi Jagan,
>
> On Fri, 22 May 2020 at 08:41, Jagan Teki wrote:
> >
> > Hi Simon,
> >
> > On Fri, May 22, 2020 at 7:55 PM Simon Glass wrote:
> > >
> > > Hi Jagan,
> > >
> > > On Thu, 14 May 2020 at 12:09, Jagan Teki
> > > wrote:
On Sat, May 23, 2020 at 2:55 AM Tom Rini wrote:
>
> On Fri, May 22, 2020 at 09:42:22PM +0530, Jagan Teki wrote:
> > On Wed, May 20, 2020 at 7:40 PM Tom Rini wrote:
> > >
> > > On Wed, May 20, 2020 at 06:46:55PM +0530, Jagan Teki wrote:
> > > > On Wed, May 20, 2020 at 6:32 PM Tom Rini wrote:
> >
SPL has a foot-print constraint, so fully switching a particular
subsystem like SPI or SPI Flash to DM would increase the size of it.
Possible areas to look at are (assume SPL_DM supported)
1) platdata
2) implement board or platform specific spl device driver which
bypassed the actual framework ex
On Fri, May 1, 2020 at 10:15 PM Marek Vasut wrote:
>
> On 5/1/20 6:34 PM, Jagan Teki wrote:
> > sh_spi driver is deprecated, no active updates and
> > no board user, hence dropped the same.
> >
> > Cc: Marek Vasut
> > Cc: Tom Rini
> > Signed-off-by: Jagan Teki
>
> I'll check whether someone sti
Enable CONFIG_PCI and CONFIG_NVME and related configs for the
ROCKPro64 board.
Signed-off-by: Mark Kettenis
---
Changes in v2:
- Extend commit message
configs/rockpro64-rk3399_defconfig | 4
1 file changed, 4 insertions(+)
diff --git a/configs/rockpro64-rk3399_defconfig
b/configs/rockpro
Enable CONFIG_PCI and CONFIG_NVME and related configs for the
Firefly RK3399 board.
Signed-off-by: Mark Kettenis
Reviewed-by: Simon Glass
---
Changes in v2:
- Extend commit message
configs/firefly-rk3399_defconfig | 4
1 file changed, 4 insertions(+)
diff --git a/configs/firefly-rk3399_d
Hi Simon,
On Mon, May 25, 2020 at 9:19 AM Bin Meng wrote:
>
> On Mon, May 25, 2020 at 7:38 AM Simon Glass wrote:
> >
> > This code is very old and has not had much of a clean-up since it was
> > written. This series aims to tidy it up to use error codes, avoid using
> > BSS when not necessary an
On Mon, May 25, 2020 at 2:36 PM Marcin Juszkiewicz
wrote:
>
> W dniu 13.05.2020 o 09:13, frank.wang at rock-chips.com (Frank Wang) pisze:
> > This series add quirks for DWC3 and add Rockchip RK3399 USB3.0 host support.
> >
> > The function has been tested pass on rk3399-evb and roc-rk3399-pc board
Hi Matthias,
On 24.05.2020 20:30, Matthias Brugger wrote:
> On 13/05/2020 11:21, Sylwester Nawrocki wrote:
>> On 12.05.2020 20:47, Sylwester Nawrocki wrote:
>>> This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI
>>> and USB commands. To get it working one has to call the follo
On Mon, May 25, 2020 at 2:57 PM Marcin Juszkiewicz
wrote:
>
> W dniu 25.05.2020 o 11:24, Jagan Teki pisze:
> > On Mon, May 25, 2020 at 2:36 PM Marcin Juszkiewicz
> > wrote:
> >>
> >> W dniu 13.05.2020 o 09:13, frank.wang at rock-chips.com (Frank Wang) pisze:
> >>> This series add quirks for DWC3
Add the bsec driver in SPL, as it is needed by SOC part number detection
to found the supported OPP.
Signed-off-by: Patrick Delaunay
Reviewed-by: Patrice Chotard
---
Changes in v2: None
arch/arm/dts/stm32mp15-u-boot.dtsi | 2 +-
arch/arm/mach-stm32mp/Makefile | 2 +-
arch/arm/mach-stm32
This serie allows to switch the CPU frequency to the max frequency
supported in OPP device tree nodes and supported by STM32MP SOC
(800MHz is supported by STM32MP15xD and STM32MP15xF).
Board also increases the VDDCore voltage to support this new
operation point.
This V2 version of [1] is rebase
This commit adds cpufreq support on stm32mp15x SOC. STM32 cpufreq uses
operating points V2 bindings (no legacy). Nvmem cells have to be used to
know the chip version and then which OPPs are available. Note that STM32
cpufreq driver is mainly based on "cpufreq-dt" driver.
Signed-off-by: Patrick Del
Add a weak functions to save the vddcore voltage value provided
in the OPP node when the clock tree is initialized.
Signed-off-by: Patrick Delaunay
Reviewed-by: Patrice Chotard
---
Changes in v2: None
arch/arm/mach-stm32mp/include/mach/sys_proto.h | 3 +++
drivers/clk/clk_stm32mp1.c
Move function board_ddr_power_init() in a new file stpmic1 in
board/st/common to avoid duplicated code in each board using
stpmic1
Signed-off-by: Patrick Delaunay
Reviewed-by: Patrice Chotard
---
Changes in v2: None
board/dhelectronics/dh_stm32mp1/Makefile | 2 +-
board/st/common/Makefile
Add a function stmpic_init to early initialize the PMIC STPMIC1
- keep vdd on during the reset cycle (to avoid issue when backup battery
is absent)
- Check if debug is enabled to program PMIC according to the bit
This patch allows to remove the compilation of spl.c file from stm32mp1
board in dh
For board using STPMIC1, the vddcore is provided by BUCK1 of STPMIC1
and need to be updated for 800MHz support and only after the clock
tree initialization.
The VDDCORE voltage value is provided by clock driver, saved in global
variable opp_voltage_mv and udpated in SPL board_early_init_f(),
just
This patch allows to switch the CPU frequency to 800MHz on the
ST Microelectronics board (DK1/DK2 and EV1) or dh electronics SOM
using the STM32MP15x SOC and when it is supported by the HW
(for STM32MP15xD and STM32MP15xF).
Signed-off-by: Patrick Delaunay
---
Changes in v2:
- update stm32mp15xx-
The PLL1 node (st,pll1) is optional in device tree, the max supported
frequency define in OPP node is used when the node is absent.
Signed-off-by: Patrick Delaunay
Reviewed-by: Patrice Chotard
---
Changes in v2: None
.../clock/st,stm32mp1.txt | 4 +
drivers/clk/clk_stm32
Move the debug function board_debug_uart_init in spl.c
as the debug_uart_init() function is called in arch_cpu_init()
only for SPL and remove the board.c file.
For TFABOOT, the UART TX pin configuration is done in TF-A.
Signed-off-by: Patrick Delaunay
---
Changes in v2:
- NEW: merge spl.c and b
On Wed, May 13, 2020 at 9:48 PM Jagan Teki
wrote:
> On Mon, May 11, 2020 at 1:36 AM Robert Marko
> wrote:
> >
> > This patch series updates the Toshiba SPI-NAND driver support to match
> > the Linux tree.
> > This imports 2 patches that add support for the new J series, as well
> > as adding x4
On 5/25/20 10:44 AM, Jagan Teki wrote:
> SPL has a foot-print constraint, so fully switching a particular
> subsystem like SPI or SPI Flash to DM would increase the size of it.
>
> Possible areas to look at are (assume SPL_DM supported)
> 1) platdata
> 2) implement board or platform specific spl d
On 5/25/20 10:47 AM, Jagan Teki wrote:
> On Fri, May 1, 2020 at 10:15 PM Marek Vasut wrote:
>>
>> On 5/1/20 6:34 PM, Jagan Teki wrote:
>>> sh_spi driver is deprecated, no active updates and
>>> no board user, hence dropped the same.
>>>
>>> Cc: Marek Vasut
>>> Cc: Tom Rini
>>> Signed-off-by: Jag
Hi Simon,
On 22.05.2020 15:42, Simon Glass wrote:
> On Thu, 21 May 2020 at 23:56, Marek Szyprowski
> wrote:
>> On 19.05.2020 18:47, Simon Glass wrote:
>>> On Tue, 19 May 2020 at 06:00, Marek Szyprowski
>>> wrote:
On 19.05.2020 00:38, Simon Glass wrote:
> On Mon, 18 May 2020 at 07:18,
Marek Vasut [mailto:ma...@denx.de]
> Sent: Friday, May 22, 2020 9:22 PM
[...]
> > - if ((ep_addr & USB_DIR_IN) && !ep_in_found) {
> > - ss->ep_in = ep_addr &
> > - USB_ENDPOINT_NUMBER_MASK;
> > -
Although I think it never occurs, the code doesn't make sense, because
it may allow to assign an IN endpoint to ss->ep_out.
Signed-off-by: Hayes Wang
---
drivers/usb/eth/r8152.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/usb/eth/r8152.c b/drivers/u
The PAL_BDC_CR should be PLA_BDC_CR.
Signed-off-by: Hayes Wang
---
drivers/usb/eth/r8152.c | 8
drivers/usb/eth/r8152.h | 4 ++--
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/usb/eth/r8152.c b/drivers/usb/eth/r8152.c
index 9f7bc7986d..cef79cab49 100644
--- a/dr
v2:
Reword the patch #1 to make it easier to understand.
v1:
These are minor corrections for r8152 driver.
Hayes Wang (2):
eth/r8152: fix assigning the wrong endpoint
eth/r8152: fix typo in register name
drivers/usb/eth/r8152.c | 22 --
drivers/usb/eth/r8152.h | 4 ++--
Hi Simon,
your commit 8e35bb07eb (2016-03-14) "mkimage: Support automatic
creating of a FIT without a .its" added the "-f auto" option to
mkimage. While convenient in many situation, I had to notice that
with "-f auto" there is no checksum information included with any of
the blobs stored in the
In current code there is no cache flush after initializing the scratchpad
buffer array with the scratchpad buffer pointers. This leads to a failure
of the "slot enable" command on the rpi4 board (Broadcom STB PCIe
controller + VL805 USB hub) - the very first TRB transfer on the command
ring fails a
Some PCI Express register offsets are currently defined in multiple
drivers, move them to a common header to avoid re-definitions and
as a pre-requisite for adding new PCIe driver.
While at it replace some spaces with tabs.
Signed-off-by: Sylwester Nawrocki
Reviewed-by: Bin Meng
Reviewed-by: Nic
There might be hardware configurations where 64-bit data accesses
to XHCI registers are not supported properly. This patch removes
the readq/writeq so always two 32-bit accesses are used to read/write
64-bit XHCI registers, similarly as it is done in Linux kernel.
This patch fixes operation of th
From: Marek Szyprowski
Remove the overlap between DRAM and device's IO area.
Signed-off-by: Marek Szyprowski
Signed-off-by: Sylwester Nawrocki
Reviewed-by: Nicolas Saenz Julienne
---
Changes since v1:
- none.
---
arch/arm/mach-bcm283x/init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletio
Hi all,
This patch series adds USB host support for Raspberry Pi 4 board.
It includes the Broadcom STB PCIe controller driver ported from Linux
kernel, a memory mapping update for the xHCI controller on PCIe bus
for 64-bit builds and some related fixes and updates in the usb/xhci
and the pci dr
From: Marek Szyprowski
This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI
and USB commands. To get it working one has to call the following commands:
"pci enum; usb start;", thus such commands have been added to the default
"preboot" environment variable. One has to update th
Add PCI Express capability definitions required by the Broadcom
STB PCIe controller driver.
Signed-off-by: Sylwester Nawrocki
Reviewed-by: Bin Meng
Reviewed-by: Nicolas Saenz Julienne
---
Changes since v3:
- none.
Changes since v2:
- added Current Link Speed defines.
Changes since v1:
- none
From: Marek Szyprowski
Create a non-cacheable mapping for the 0x6 physical memory region,
where MMIO registers for the PCIe XHCI controller are instantiated by the
PCIe bridge.
Signed-off-by: Marek Szyprowski
Signed-off-by: Sylwester Nawrocki
Reviewed-by: Nicolas Saenz Julienne
---
Ch
This patch adds basic driver PCI Express controller found on Broadcom
set-top-box SoCs, e.g. BCM2711.
The code is based on Linux upstream driver (pcie-brcmstb.c) with MSI
handling removed. The inbound access memory region is not currently
parsed from dma-ranges DT property and a fixed 3GB region is
From: Nicolas Saenz Julienne
Imports Al Viro's original Linux commit 00b0c9b82663a, which contains
an in depth explanation and two fixes from Johannes Berg:
e7d4a95da86e0 "bitfield: fix *_encode_bits()",
37a3862e12382 "bitfield: add u8 helpers".
Signed-off-by: Nicolas Saenz Julienne
[s.nawroc
On 5/25/20 9:47 AM, Hayes Wang wrote:
> Although I think it never occurs, the code doesn't make sense, because
> it may allow to assign an IN endpoint to ss->ep_out.
>
> Signed-off-by: Hayes Wang
> ---
> drivers/usb/eth/r8152.c | 14 ++
> 1 file changed, 6 insertions(+), 8 deletions(
To enable DM_VIDEO we must decrease binary size to fix build
breakage for some boards, so drop not needed code. Also add
!DM_VIDEO guards which can be later removed when last non DM
users will be converted.
Signed-off-by: Anatolij Gustschin
---
drivers/video/imx/ipu_disp.c | 12 ---
driv
pt., 22 maj 2020 o 04:02 Faiz Abbas napisał(a):
>
> Cleanup this driver to use dt in U-boot and static platdata in SPL.
> This requires the following steps:
>
> 1. Move all platdata assignment from probe() to ofdata_to_platdata().
>This function is only called in U-boot.
> 2. Replicate all the
RNG module works fine on RockPro64 so let's enable it by default.
=> rng
: 77 08 dd 04 2c 4d b8 cf 25 07 29 2d c0 ce 28 3b w...,M..%.)-..(;
0010: d4 5a 38 68 b1 40 97 59 b8 a5 7c 42 f8 4c 38 28 .Z8h.@.Y..|B.L8(
0020: 25 20 0b 4b f0 1a d5 c1 e6 a2 c2 34 5a 5e 64 26 % .K...4Z
Marek Vasut [mailto:ma...@denx.de]
> Sent: Monday, May 25, 2020 8:03 PM
[...]
ep_out_found = 1;
> > - }
> > + } else if ((ep_addr & USB_DIR_OUT) && !ep_out_found) {
>
>
> Sorry, I was wrong in my previous suggestion, the
On 5/25/20 2:52 PM, Hayes Wang wrote:
> Marek Vasut [mailto:ma...@denx.de]
>> Sent: Monday, May 25, 2020 8:03 PM
> [...]
> ep_out_found = 1;
>>> - }
>>> + } else if ((ep_addr & USB_DIR_OUT) && !ep_out_found) {
>>
>>
>> Sorry,
W dniu 13.05.2020 o 09:13, frank.wang at rock-chips.com (Frank Wang) pisze:
> This series add quirks for DWC3 and add Rockchip RK3399 USB3.0 host support.
>
> The function has been tested pass on rk3399-evb and roc-rk3399-pc board.
>
> For V5 update:
> - Fix dwc3-generic driver followed Marek's
W dniu 24.05.2020 o 22:32, Mark Kettenis pisze:
> The vpcie*-supply properties are optional and these are absent on
> boards like the ROCKPro64 and Firefly RK3399 where the voltage is
> supplied by always-on regulators that are already enabled upon
> boot. Make these regulators optional and proper
Hi Pragnesh,
On Mon, May 25, 2020 at 3:33 PM Pragnesh Patel
wrote:
>
> This series add support for SPL to FU540. U-Boot SPL can boot from
> L2 LIM (0x0800_) and jump to OpenSBI(FW_DYNAMIC firmware) and
> U-Boot proper from MMC devices.
>
> This series is also available here [1] for testing
>
On Mon, May 25, 2020 at 02:01:09PM +0530, Jagan Teki wrote:
> On Sat, May 23, 2020 at 2:55 AM Tom Rini wrote:
> >
> > On Fri, May 22, 2020 at 09:42:22PM +0530, Jagan Teki wrote:
> > > On Wed, May 20, 2020 at 7:40 PM Tom Rini wrote:
> > > >
> > > > On Wed, May 20, 2020 at 06:46:55PM +0530, Jagan T
This would make SPL build to DM_SPL, SPL_OF_CONTROL.
Build fine with warnings, but not tested.
Cc: Vitaly Andrianov
Signed-off-by: Jagan Teki
---
configs/k2e_evm_defconfig| 2 ++
configs/k2g_evm_defconfig| 2 ++
configs/k2hk_evm_defconfig | 2 ++
configs/k2l_e
Now all boards which are using davinci SPI driver
have moved to SPL_DM so drop the unneeded non-dm code.
Cc: Adam Ford
Signed-off-by: Jagan Teki
---
drivers/spi/davinci_spi.c| 157 ---
include/configs/ti_armv7_keystone2.h | 9 --
2 files changed, 166 deleti
W dniu 25.05.2020 o 11:24, Jagan Teki pisze:
> On Mon, May 25, 2020 at 2:36 PM Marcin Juszkiewicz
> wrote:
>>
>> W dniu 13.05.2020 o 09:13, frank.wang at rock-chips.com (Frank Wang) pisze:
>>> This series add quirks for DWC3 and add Rockchip RK3399 USB3.0 host support.
>>>
>>> The function has bee
W dniu 25.05.2020 o 11:32, Jagan Teki pisze:
> On Mon, May 25, 2020 at 2:57 PM Marcin Juszkiewicz
>> No - "scanning bus dwc3 for devices... cannot reset port 1!?" every time
>> and devices plugged into usb-c are ignored.
>
> Can you check 'usb reset' after 'usb start'
Same situation after each '
Hi Bin,
>-Original Message-
>From: Bin Meng
>Sent: 25 May 2020 18:42
>To: Pragnesh Patel
>Cc: U-Boot Mailing List ; Atish Patra
>; Palmer Dabbelt ; Paul
>Walmsley ; Jagan Teki
>; Anup Patel ; Sagar
>Kadam ; Rick Chen
>Subject: Re: [PATCH v12 00/18] RISC-V SiFive FU540 support SPL
>
>[Ex
Hi Marek,
On Mon, 25 May 2020 at 04:48, Marek Szyprowski wrote:
>
> Hi Simon,
>
> On 22.05.2020 15:42, Simon Glass wrote:
> > On Thu, 21 May 2020 at 23:56, Marek Szyprowski
> > wrote:
> >> On 19.05.2020 18:47, Simon Glass wrote:
> >>> On Tue, 19 May 2020 at 06:00, Marek Szyprowski
> >>> wrote
Hi Sylwester,
On Mon, 25 May 2020 at 05:40, Sylwester Nawrocki wrote:
>
> There might be hardware configurations where 64-bit data accesses
> to XHCI registers are not supported properly. This patch removes
> the readq/writeq so always two 32-bit accesses are used to read/write
> 64-bit XHCI reg
Hi Faiz,
On Thu, 21 May 2020 at 20:02, Faiz Abbas wrote:
>
> Cleanup this driver to use dt in U-boot and static platdata in SPL.
> This requires the following steps:
>
> 1. Move all platdata assignment from probe() to ofdata_to_platdata().
>This function is only called in U-boot.
> 2. Replica
Hi Simon,
On 25/05/20 8:27 pm, Simon Glass wrote:
> Hi Faiz,
>
> On Thu, 21 May 2020 at 20:02, Faiz Abbas wrote:
>>
>> Cleanup this driver to use dt in U-boot and static platdata in SPL.
>> This requires the following steps:
>>
>> 1. Move all platdata assignment from probe() to ofdata_to_platdat
This patch provides the documentation for a proposed enhancement to driver
model to reduce overhead in SPL.
The actual patches are not included here because they are based on some
pending work by Walter Lozano which is not in final form.
For now, the source tree is available at:
https://gitla
Hi,
On Mon, 25 May 2020 at 04:35, Marek Vasut wrote:
>
> On 5/25/20 10:44 AM, Jagan Teki wrote:
> > SPL has a foot-print constraint, so fully switching a particular
> > subsystem like SPI or SPI Flash to DM would increase the size of it.
> >
> > Possible areas to look at are (assume SPL_DM suppor
Hi Faiz,
On Mon, 25 May 2020 at 09:33, Faiz Abbas wrote:
>
> Hi Simon,
>
> On 25/05/20 8:27 pm, Simon Glass wrote:
> > Hi Faiz,
> >
> > On Thu, 21 May 2020 at 20:02, Faiz Abbas wrote:
> >>
> >> Cleanup this driver to use dt in U-boot and static platdata in SPL.
> >> This requires the following s
On Mon, May 25, 2020 at 04:01:08PM +0800, ub...@andestech.com wrote:
> Hi Tom,
>
> Please pull some riscv updates:
>
> - Add Sipeed Maix support.
> - sifive: fix palmer's email address.
> - Move all SMP related SBI calls to SBI_v01.
>
> https://travis-ci.org/github/rickchen36/u-boot-riscv/build
On 5/25/20 5:36 PM, Simon Glass wrote:
> Hi,
>
> On Mon, 25 May 2020 at 04:35, Marek Vasut wrote:
>>
>> On 5/25/20 10:44 AM, Jagan Teki wrote:
>>> SPL has a foot-print constraint, so fully switching a particular
>>> subsystem like SPI or SPI Flash to DM would increase the size of it.
>>>
>>> Poss
Hi Marek,
On Mon, 25 May 2020 at 09:43, Marek Vasut wrote:
>
> On 5/25/20 5:36 PM, Simon Glass wrote:
> > Hi,
> >
> > On Mon, 25 May 2020 at 04:35, Marek Vasut wrote:
> >>
> >> On 5/25/20 10:44 AM, Jagan Teki wrote:
> >>> SPL has a foot-print constraint, so fully switching a particular
> >>> sub
At present coral does not build due to a missing header file. The need
for this was introduced recently on master. Fix it.
Fixes: e9a32698517 ("x86: apl: Use devicetree for FSP-M configuration")
Signed-off-by: Simon Glass
---
Changes in v2:
- Add Fixes tag for the first commit that showed this p
On 5/25/20 5:48 PM, Simon Glass wrote:
> Hi Marek,
>
> On Mon, 25 May 2020 at 09:43, Marek Vasut wrote:
>>
>> On 5/25/20 5:36 PM, Simon Glass wrote:
>>> Hi,
>>>
>>> On Mon, 25 May 2020 at 04:35, Marek Vasut wrote:
On 5/25/20 10:44 AM, Jagan Teki wrote:
> SPL has a foot-print constr
On Mon, May 25, 2020 at 02:34:17PM +0200, Anatolij Gustschin wrote:
> To enable DM_VIDEO we must decrease binary size to fix build
> breakage for some boards, so drop not needed code. Also add
> !DM_VIDEO guards which can be later removed when last non DM
> users will be converted.
>
> Signed-off
Hi Simon,
On 25.05.2020 16:57, Simon Glass wrote:
> On Mon, 25 May 2020 at 05:40, Sylwester Nawrocki
> wrote:
>>
>> There might be hardware configurations where 64-bit data accesses
>> to XHCI registers are not supported properly. This patch removes
>> the readq/writeq so always two 32-bit acce
Hi Marek,
On Mon, 25 May 2020 at 09:56, Marek Vasut wrote:
>
> On 5/25/20 5:48 PM, Simon Glass wrote:
> > Hi Marek,
> >
> > On Mon, 25 May 2020 at 09:43, Marek Vasut wrote:
> >>
> >> On 5/25/20 5:36 PM, Simon Glass wrote:
> >>> Hi,
> >>>
> >>> On Mon, 25 May 2020 at 04:35, Marek Vasut wrote:
>
On Sun, 17 May 2020 at 02:28, Rayagonda Kokatanur
wrote:
>
> From: Vikas Gupta
>
> Enable tee and optee drivers.
>
> Signed-off-by: Vikas Gupta
> Signed-off-by: Rayagonda Kokatanur
> ---
> configs/bcm_ns3_defconfig | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
Reviewed-by: Simon
On Sun, 17 May 2020 at 02:25, Rayagonda Kokatanur
wrote:
>
> From: Pramod Kumar
>
> Add development keys used in FIT.
>
> Signed-off-by: Pramod Kumar
> Signed-off-by: Rayagonda Kokatanur
> ---
> board/broadcom/bcmns3/fit/keys/dev.crt | 21 +++
> board/broadcom/bcmns3/fit/keys/d
On Sun, 17 May 2020 at 02:25, Rayagonda Kokatanur
wrote:
>
> Enable FIT config for NS3.
>
> Signed-off-by: Rayagonda Kokatanur
> ---
> configs/bcm_ns3_defconfig | 5 +
> 1 file changed, 5 insertions(+)
Reviewed-by: Simon Glass
On Sun, 17 May 2020 at 02:28, Rayagonda Kokatanur
wrote:
>
> From: Vikas Gupta
>
> Add support for optee
>
> Signed-off-by: Vikas Gupta
> Signed-off-by: Rayagonda Kokatanur
> ---
> arch/arm/dts/ns3.dtsi | 7 +++
> 1 file changed, 7 insertions(+)
>
Reviewed-by: Simon Glass
On Sun, 17 May 2020 at 02:33, Rayagonda Kokatanur
wrote:
>
> From: Vladimir Olovyannikov
>
> Extend Kconfig for the board with board-specific commands selection.
>
> Signed-off-by: Vladimir Olovyannikov
> Signed-off-by: Rayagonda Kokatanur
> ---
> board/broadcom/bcmns3/Kconfig | 4
> 1 fi
Hi Rayagonda,
On Sun, 17 May 2020 at 02:33, Rayagonda Kokatanur
wrote:
>
> From: Vladimir Olovyannikov
>
> Add broadcom error log setup command.
>
> Some Broadcom platforms have ability to record event logs by SCP.
> - Add a logsetup command which is used to perform initial configuration
> of
Hi Stefan,
On Thu, 14 May 2020 at 08:26, Stefan Roese wrote:
>
> From: Suneel Garapati
>
> Add support for GPIO controllers found on Octeon II/III and Octeon TX
> TX2 SoC platforms.
>
> Signed-off-by: Aaron Williams
> Signed-off-by: Suneel Garapati
> Cc: Simon Glass
> Cc: Daniel Schwierzeck
On Sun, 17 May 2020 at 02:37, Rayagonda Kokatanur
wrote:
>
> From: Vikas Gupta
>
> Add nitro image load commands.
>
> Signed-off-by: Vikas Gupta
> Signed-off-by: Rayagonda Kokatanur
> ---
> cmd/bcm/Makefile | 1 +
> cmd/bcm/nitro_image_load.c | 99 +++
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