On Mon, May 17, 2021 at 10:03 AM Bin Meng wrote:
>
> Hi Simon,
>
> On Fri, Apr 30, 2021 at 9:17 PM Bin Meng wrote:
> >
> > 'dma-ranges' frequently exists without parent nodes having 'dma-ranges'.
> > While this is an error for 'ranges', this is fine because DMA capable
> > devices always have a t
At present the AE350 SPL defconfig is using OF_PRIOR_STAGE. The
intention was to use gdb to load device tree before running U-Boot
SPL/proper from RAM. When we switch to OF_SEPARATE we will have to
use our own DT but without "u-boot,dm-spl" in several essential
nodes, SPL does not boot.
Let's add
All the device nodes that refer to plic0 as their interrupt parent
have 2 cells encoded in their interrupts property, but plic0 only
provides 1 cell in #interrupt-cells which is incorrect.
Signed-off-by: Bin Meng
---
arch/riscv/dts/ae350_32.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion
PLIC nodes don't have child nodes, so #address-cells is not needed.
Signed-off-by: Bin Meng
---
arch/riscv/dts/ae350_32.dts | 2 --
arch/riscv/dts/ae350_64.dts | 2 --
2 files changed, 4 deletions(-)
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index b90351e87b..0917b
There are two spaces before "debug' in bootargs. Drop one.
Signed-off-by: Bin Meng
---
arch/riscv/dts/ae350_32.dts | 2 +-
arch/riscv/dts/ae350_64.dts | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index ef110c54a
The SPDX license header is currently missing. Add one.
Signed-off-by: Bin Meng
---
arch/riscv/dts/ae350_32.dts | 2 ++
arch/riscv/dts/ae350_64.dts | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index a0ab5e9be2..ef110c54ae 100644
Replace msleep occurences by udelay.
drivers/pci/pcie_dw_rockchip.c:254:3: warning: implicit
declaration of function 'msleep' [-Wimplicit-function-declaration]
Cc: Patrick Wildt
Cc: Neil Armstrong
Cc: Kever Yang
Signed-off-by: Anand Moon
---
V2: drop the msleep macro.
---
drivers/pci/pc
Drop the unused variable warning below.
drivers/pci/pcie_dw_rockchip.c:161:6: warning: unused variable
'val' [-Wunused-variable]
161 | u32 val;
| ^~~
Cc: Patrick Wildt
Cc: Neil Armstrong
Cc: Kever Yang
Reviewed-by: Neil Armstrong
Signed-off-by: Anand Moon
---
V1
V2: Added Neil
Use the generic error number instead of specific error number.
Changes fix the below error.
drivers/pci/pcie_dw_rockchip.c: In function 'rk_pcie_read':
drivers/pci/pcie_dw_rockchip.c:70:10: error: 'PCIBIOS_UNSUPPORTED'
undeclared (first use in this function)
70 | retur
From: Tianrui Wei
Date: Fri, 4 June 2021 12:45:29 +0800
Subject: [PATCH v5 2/2] riscv: board: Support OpenPiton SoC
This patch add board support for OpenPiton.
Changelog:
v5:
- major changes to device tree
- change defconfig to use OF_SEPARATE and other things
- change some documentation
Signe
From: Tianrui Wei
Date: Fri, 4 June 2021 12:45:29 +0800
Subject: [PATCH v5 1/2] mmc: add OpenPiton mmc support
This patch adds mmc support for OpenPiton board.
Changelog:
v5: move definitions around, changed some incompatible type information
Signed-off-by: Tianrui Wei
Signed-off-by: Jonathan
This patch set is to add OpenPiton board support. Patches are split into
several parts:
- [PATCH 1/2] add OpenPiton support to mmc driver
- [PATCH 2/2] add support for OpenPiton board
Description
- for mmc driver, it's settings are automatically configured at hardware level.
We only need to ex
On 6/4/21 12:28 AM, Damien Le Moal wrote:
On 2021/06/04 12:58, Sean Anderson wrote:
This is something I've been meaning to do for a while but only just got around
to. The CCF has been quite unwieldy in a few ways:
* It is very rigid, and there are not easy ways to hook into it without
rewrit
On 6/3/21 11:58 PM, Sean Anderson wrote:
This adds support for setting clock rates, which was left out of the
initial CCF expunging. There are several tricky bits here, mostly related
to the PLLS:
* The PLL's bypass is broken. If the PLL is reconfigured, any child clocks
will be stopped.
* PL
Now that the k210 clock driver does not depend on CCF, we should no longer
imply it (and probably should not have in the first place). We can also
reduce the pre-relocation malloc arena back to something sensible.
Signed-off-by: Sean Anderson
---
(no changes since v1)
board/sipeed/maix/Kconfig
This adds the unit test for the K210 PLL to the sandbox defconfigs.
Signed-off-by: Sean Anderson
Reviewed-by: Simon Glass
---
(no changes since v1)
configs/sandbox64_defconfig| 2 ++
configs/sandbox_defconfig | 2 ++
configs/sandbox_flattree_defconfig | 2 ++
3 files changed,
This driver no longer serves a purpose now that we have moved away from
CCF. Drop it.
Signed-off-by: Sean Anderson
---
(no changes since v1)
drivers/clk/kendryte/Makefile | 2 +-
drivers/clk/kendryte/bypass.c | 273 --
include/kendryte/bypass.h | 31
Now that we have only one clock driver, we don't need to have our own
subdirectory. Move the driver back with the rest of the clock drivers.
The MAINTAINERS for kendryte pinctrl is also fixed since it has always been
wrong.
Signed-off-by: Sean Anderson
---
(no changes since v1)
MAINTAINERS
Linux has had some stability issues when using AISRAM with a different
frequency from SRAM. Mirror their change here now that we relocate into
AISRAM.
Signed-off-by: Sean Anderson
---
(no changes since v1)
arch/riscv/dts/k210.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/risc
This speeds up boot by preventing multiple reconfigurations of the PLLs.
Signed-off-by: Sean Anderson
---
(no changes since v1)
drivers/clk/kendryte/clk.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c
Now that there no separate PLL driver, we can no longer make the PLL
functions static. By moving the PLL driver in with the rest of the clock
code, we can make these functions static again. We still keep the pll
header for unit testing, but it is pretty reduced.
Signed-off-by: Sean Anderson
---
This adds support for setting clock rates, which was left out of the
initial CCF expunging. There are several tricky bits here, mostly related
to the PLLS:
* The PLL's bypass is broken. If the PLL is reconfigured, any child clocks
will be stopped.
* PLL0 is the parent of ACLK which is the CPU an
This is effectively a complete rewrite to remove all dependency on CCF.
The code is now smaller, and so is the binary (TODO: numbers). It also
takes up less memory at runtime (since we don't have to create 40
udevices). In general, I am much happier with this driver as much of the
complexity and la
Since we are no longer using CCF we cannot use the default soc_clk_dump.
Instead, implement our own.
Signed-off-by: Sean Anderson
---
(no changes since v1)
drivers/clk/kendryte/clk.c | 68 --
1 file changed, 66 insertions(+), 2 deletions(-)
diff --git a/dri
Since 291da96b8e ("clk: Allow clock defaults to be set during re-reloc
state for SPL only") it has been impossible to set clock defaults before
relocation. This is annoying on boards without SPL, since there is no way
to set clock defaults before U-Boot proper. In particular, the aisram rate
must b
This is something I've been meaning to do for a while but only just got around
to. The CCF has been quite unwieldy in a few ways:
* It is very rigid, and there are not easy ways to hook into it without
rewriting many things. See e.g. things like the bypass clock and all the _half
clocks which
Hi Andre,
Le 17/04/2021 à 20:23, Andre Przywara a écrit :
> On Sat, 17 Apr 2021 12:47:23 -0500
> Samuel Holland wrote:
>
> Hi Samuel,
>
>> On 3/31/21 10:39 AM, Andre Przywara wrote:
>>> On 20/02/2021 12:14, Nicolas Boulenguez wrote:
>>>
>>> Hi Arnaud,
>>>
From: Arnaud Ferraris
>>>
>>
On 6/3/21 11:51 AM, Yangbo Lu wrote:
> For eSDHC, power supply is through peripheral circuit.
> Some eSDHC versions have value 0 of the bit but that
> does not reflect the truth. 3.3V is common for SD/MMC,
> and is supported for all boards with eSDHC in current
> u-boot. So, make 3.3V is supported
Add support for 1.3GHz, 1.35GHz and 1.4GHz parts. This is based on
equivalent code in Broadcom's LDK 5.0.6.
Signed-off-by: Chris Packham
---
As Broadcom are currently migrating users to the BCM58525BB1KF14G part
I suspect others may want this. In our case because we wanted to still
run at 1.2GHz
On 6/3/21 8:00 PM, Andreas Rehn wrote:
Am Do., 3. Juni 2021 um 18:58 Uhr schrieb Andre Przywara
mailto:andre.przyw...@arm.com>>:
On Thu, 3 Jun 2021 18:09:25 +0200
Heinrich Schuchardt mailto:xypron.g...@gmx.de>>
wrote:
Hi,
> On 6/3/21 1:04 PM, Andre Przywara wrote:
>
On 6/3/21 6:57 PM, Andre Przywara wrote:
On Thu, 3 Jun 2021 18:09:25 +0200
Heinrich Schuchardt wrote:
Hi,
On 6/3/21 1:04 PM, Andre Przywara wrote:
On Thu, 3 Jun 2021 12:20:34 +0200
Heinrich Schuchardt wrote:
Hi,
On 6/3/21 11:04 AM, Andre Przywara wrote:
On Thu, 3 Jun 2021 09:46:48 +0200
If a test-uclass device is probed outside a test, uts is not defined.
Avoid a NULL dereference in this case.
Signed-off-by: Heinrich Schuchardt
---
test/dm/test-uclass.c | 12
1 file changed, 12 insertions(+)
diff --git a/test/dm/test-uclass.c b/test/dm/test-uclass.c
index 06770173
Am Do., 3. Juni 2021 um 18:58 Uhr schrieb Andre Przywara <
andre.przyw...@arm.com>:
> On Thu, 3 Jun 2021 18:09:25 +0200
> Heinrich Schuchardt wrote:
>
> Hi,
>
> > On 6/3/21 1:04 PM, Andre Przywara wrote:
> > > On Thu, 3 Jun 2021 12:20:34 +0200
> > > Heinrich Schuchardt wrote:
> > >
> > > Hi,
> >
On Thu, 3 Jun 2021 18:09:25 +0200
Heinrich Schuchardt wrote:
Hi,
> On 6/3/21 1:04 PM, Andre Przywara wrote:
> > On Thu, 3 Jun 2021 12:20:34 +0200
> > Heinrich Schuchardt wrote:
> >
> > Hi,
> >
> >> On 6/3/21 11:04 AM, Andre Przywara wrote:
> >>> On Thu, 3 Jun 2021 09:46:48 +0200
> >>> Heinr
On 6/3/21 8:28 AM, Adam Ford wrote:
> The driver is based on the Versaclock driver from the Linux code, but
> due to the differences in the clock API between U-Boot and Linux, some
> pieces had to be changed.
>
> This driver creates a mux, pfd, pll, and a series of fod ouputs.
> Rate
Hi Marek,
Sorry for rate reply.
On 2021/05/25 16:35, Marek Vasut wrote:
On 5/12/21 4:09 PM, Kunihiko Hayashi wrote:
When CONFIG_ENV_IS_NOWHERE is enabled, env_nowhere_init() sets ENV_INVALID
to gd->env_valid, and sets default_environment before relocation to
gd->env_addr. After that, env_init()
On 6/3/21 1:04 PM, Andre Przywara wrote:
On Thu, 3 Jun 2021 12:20:34 +0200
Heinrich Schuchardt wrote:
Hi,
On 6/3/21 11:04 AM, Andre Przywara wrote:
On Thu, 3 Jun 2021 09:46:48 +0200
Heinrich Schuchardt wrote:
Hi Heinrich,
On 6/2/21 3:08 PM, Ramon Fried wrote:
On Tue, Jun 1, 2021 at 12:3
Hi Adam,
On 03/06/21 14:06, Adam Ford wrote:
> On Thu, Jun 3, 2021 at 3:34 AM Luca Ceresoli wrote:
>>
>> On 24/05/21 19:53, Adam Ford wrote:
>>> The driver is based on the Versaclock driver from the Linux code, but
>>> do differences in the clock API between them, some pieces had to change.
>>
>>
On Tue, Apr 27, 2021 at 6:59 PM Marek Vasut wrote:
>
> On 4/28/21 3:51 AM, Tim Harvey wrote:
> > On Tue, Apr 27, 2021 at 10:45 AM Marek Vasut wrote:
> >>
> >> On 4/27/21 7:08 PM, Tim Harvey wrote:
> >>> There is no need to set and/or detect mode in of_to_plat and
> >>> accessing phy registers at
On Thu, Jun 3, 2021 at 9:52 AM Sean Anderson wrote:
>
>
>
> On 6/3/21 4:34 AM, Luca Ceresoli wrote:
> > On 24/05/21 19:53, Adam Ford wrote:
> >> The driver is based on the Versaclock driver from the Linux code, but
> >> do differences in the clock API between them, some pieces had to change.
>
Am Do., 3. Juni 2021 um 16:43 Uhr schrieb Heinrich Schuchardt <
xypron.g...@gmx.de>:
> On 6/3/21 3:56 PM, Andre Przywara wrote:
> > On Fri, 21 May 2021 22:14:00 +0200
> > Andreas Rehn wrote:
> >
> > Hi,
> >
> >> sorry for the late response.
> >
> > same ;-)
> >
> >> I run some test runs and maybe
On Wed, 2 Jun 2021 19:10:01 +0200
Marek Behún wrote:
> The node `internal-regs` is called `internal-regs@d000`
> in Linux' device tree. Rename this in U-Boot also.
>
> No in-tree code depends on this name, so this should be safe.
>
> Signed-off-by: Marek Behún
> ---
> arch/arm/dts/armada
On Wed, 2 Jun 2021 19:09:56 +0200
Marek Behún wrote:
> +#define TURRIS_MOX_BOOTCMD_RESCUE \
> + "setenv bootargs \"console=ttyMV0,115200 " \
> + "earlycon=ar3700_uart,0xd0012000\" && " \
> + "sf probe && " \
> + "sf read ${kernel_addr_r} 0x19 && " \
> +
On Thu, Jun 03, 2021 at 05:07:17PM +0200, Rasmus Villemoes wrote:
> On 03/06/2021 15.39, Tom Rini wrote:
> > Based on the comment in socfpga_soc64_common.h, the intention is for
> > CONFIG_SYS_MEM_RESERVE_SECURE to be unused. However, in the code we do:
> > ...
> >
> > and that will evaluate to t
Hi!
Dne četrtek, 27. maj 2021 ob 01:49:48 CEST je Andre Przywara napisal(a):
> On Wed, 5 May 2021 13:53:05 +0100
> Andre Przywara wrote:
>
> Hi,
>
> > Most clock factors and dividers in the H6 PLLs use a "+1 encoding",
> > which we were missing on two occasions.
>
> can someone please confirm
On 03/06/2021 15.39, Tom Rini wrote:
> Based on the comment in socfpga_soc64_common.h, the intention is for
> CONFIG_SYS_MEM_RESERVE_SECURE to be unused. However, in the code we do:
> ...
>
> and that will evaluate to true. This leads to unwanted code being
Some cleanup made lines beginning wit
On 6/3/21 4:34 AM, Luca Ceresoli wrote:
> On 24/05/21 19:53, Adam Ford wrote:
>> The driver is based on the Versaclock driver from the Linux code, but
>> do differences in the clock API between them, some pieces had to change.
>
> s/do/due to/ ?
> s/had to change/had to be changed/
>
>> This dr
On 6/2/21 9:56 AM, Zhengxun Li wrote:
Hi Sean,
Thanks for your reply.
This clock driver adds support for clock related settings for
Zynq platform.
+config COMMON_CLK_XLNX_CLKWZRD
Why not just CLK_XILNIX_WIZARD? Do we need "COMMON" in here?
Follow the linux patch "clk: c
On 6/3/21 3:56 PM, Andre Przywara wrote:
On Fri, 21 May 2021 22:14:00 +0200
Andreas Rehn wrote:
Hi,
sorry for the late response.
same ;-)
I run some test runs and maybe there is something with the phy itself
or something is missing on sun8i_emac_eth_stop/start?
if you have any patches/id
On Fri, 21 May 2021 22:14:00 +0200
Andreas Rehn wrote:
Hi,
> sorry for the late response.
same ;-)
> I run some test runs and maybe there is something with the phy itself
> or something is missing on sun8i_emac_eth_stop/start?
>
> if you have any patches/ideas to test - let me know!
> maybe s
All symbols that are defined in Kconfig will always be defined (or not)
prior to preprocessing due to the -include directive while building.
However, symbols which are not yet migrated will only be defined (or
not) once the board config.h is included, via . While the end
goal must be to migrate al
Based on the comment in socfpga_soc64_common.h, the intention is for
CONFIG_SYS_MEM_RESERVE_SECURE to be unused. However, in the code we do:
...
and that will evaluate to true. This leads to unwanted code being
compiled. Further, as CONFIG_SYS_MEM_RESERVE_SECURE has not been
migrated to Kconfig
With the changes in commit 588efcdd72fc ("powerpc: Don't use relative
include for config.h in global_data.h") fixing the root of the problem,
we no longer need this re-inclusion.
This reverts commit f6c0d365d3e8ee8e4fd3ebe2ed957c2bca9d3328.
Cc: Matt Merhar
Signed-off-by: Tom Rini
---
I will nee
As there is an arch/powerpc/include/asm/config.h file using "" to get
config.h here can lead to using that rather than include/config.h. This
in turn can lead to a mismatch in the size of gd.
Cc: Matt Merhar
Signed-off-by: Tom Rini
---
arch/powerpc/include/asm/global_data.h | 2 +-
1 file chan
There is a QSPI NOR flash part on the board. Because this chip isn't
yet supported in Linux, but it is supported in U-Boot, and the
face that the RPC_SPI compatible names are different in U-Boot and
Linux, the device tree updates are confined to -u-boot.dtsi files.
In order to use the QSPI, TF-A
From: Kevin Scholz
Update the ddr settings to use the DDR reg config tool rev 0.5.0.
This enables 2666MTs LPDDR configuration on J7200.
Signed-off-by: Kevin Scholz
Signed-off-by: Praneeth Bajjuri
Tested-by: Suman Anna
---
...00.dtsi => k3-j7200-ddr-evm-lp4-2666.dtsi} | 437 +-
The driver is based on the Versaclock driver from the Linux code, but
due to the differences in the clock API between U-Boot and Linux, some
pieces had to be changed.
This driver creates a mux, pfd, pll, and a series of fod ouputs.
Rate Usecnt Name
-
On Thu, Jun 3, 2021 at 3:34 AM Luca Ceresoli wrote:
>
> On 24/05/21 19:53, Adam Ford wrote:
> > The driver is based on the Versaclock driver from the Linux code, but
> > do differences in the clock API between them, some pieces had to change.
>
> s/do/due to/ ?
> s/had to change/had to be changed/
On Thu, 3 Jun 2021 12:20:34 +0200
Heinrich Schuchardt wrote:
Hi,
> On 6/3/21 11:04 AM, Andre Przywara wrote:
> > On Thu, 3 Jun 2021 09:46:48 +0200
> > Heinrich Schuchardt wrote:
> >
> > Hi Heinrich,
> >
> >> On 6/2/21 3:08 PM, Ramon Fried wrote:
> >>> On Tue, Jun 1, 2021 at 12:35 AM Heinric
Use the more generic reset-gpios property name.
Signed-off-by: Jorge Ramirez-Ortiz
Acked-by: Michal Simek
---
v5: added Acked-by: Michal Simek
.../tpm2/tis-tpm2-spi.txt | 3 ++-
drivers/tpm/tpm2_tis_spi.c| 23 ---
2 files changed, 17
On 6/3/21 12:38 PM, Jorge Ramirez-Ortiz wrote:
> Use the more generic reset-gpios property name.
>
> Signed-off-by: Jorge Ramirez-Ortiz
> ---
>
> v4: s/will be deprecated/is deprecated
>
> .../tpm2/tis-tpm2-spi.txt | 3 ++-
> drivers/tpm/tpm2_tis_spi.c
Use the more generic reset-gpios property name.
Signed-off-by: Jorge Ramirez-Ortiz
---
v4: s/will be deprecated/is deprecated
.../tpm2/tis-tpm2-spi.txt | 3 ++-
drivers/tpm/tpm2_tis_spi.c| 23 ---
2 files changed, 17 insertions(+), 9 d
On 6/3/21 11:04 AM, Andre Przywara wrote:
On Thu, 3 Jun 2021 09:46:48 +0200
Heinrich Schuchardt wrote:
Hi Heinrich,
On 6/2/21 3:08 PM, Ramon Fried wrote:
On Tue, Jun 1, 2021 at 12:35 AM Heinrich Schuchardt wrote:
Dear all,
network is broken in U-Boot on orangepi_pc_defconfig:
Thanks fo
Hi Peter
On 2021/6/2 下午7:51, Peter Robinson wrote:
On Wed, Jun 2, 2021 at 12:47 PM Joseph Chen wrote:
RK3568 is a high-performance and low power quad-core application
processor designed for personal mobile internet device and AIoT
equipments.
Signed-off-by: Joseph Chen
---
arch/arm/includ
On 6/3/21 11:21 AM, Jorge Ramirez-Ortiz wrote:
> Use the more generic reset-gpios property name.
>
> Signed-off-by: Jorge Ramirez-Ortiz
> ---
>
> v3: maintained the legacy property in the docs
>
> .../tpm2/tis-tpm2-spi.txt | 3 ++-
> drivers/tpm/tpm2_tis_spi.c
Use the more generic reset-gpios property name.
Signed-off-by: Jorge Ramirez-Ortiz
---
v3: maintained the legacy property in the docs
.../tpm2/tis-tpm2-spi.txt | 3 ++-
drivers/tpm/tpm2_tis_spi.c| 23 ---
2 files changed, 17 insertions(
Enable config to support gpt command on AM642 evm/sk and enable config for
FDT library overlay support
Signed-off-by: Aswath Govindraju
---
configs/am64x_evm_a53_defconfig | 2 ++
configs/am64x_evm_r5_defconfig | 1 +
2 files changed, 3 insertions(+)
diff --git a/configs/am64x_evm_a53_defconfi
From: Kishon Vijay Abraham I
Enable configs to support eMMC boot.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Aswath Govindraju
---
configs/am64x_evm_a53_defconfig | 1 +
configs/am64x_evm_r5_defconfig | 2 ++
2 files changed, 3 insertions(+)
diff --git a/configs/am64x_evm_a53_defc
Kconfig symbols for SYS_MMC_ENV_DEV and SYS_MMC_ENV_PART have been added by
commit 7d080773347c1f6e0e896d9284134a2a411155d6. Therefore, move the
definitions of configs to corresponding board defconfig files and enable
configs to save env in eMMC.
Also enable config for FAT write in U-Boot.
Fixes:
From: Kishon Vijay Abraham I
Enable configs to support HS200/HS400.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Aswath Govindraju
---
configs/am64x_evm_a53_defconfig | 5 +
1 file changed, 5 insertions(+)
diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defco
A Wilink wireless device is connected to MMCSD0 subsystem and is not
supported in U-Boot. Therefore, disable main_sdhci0 device tree node in
U-Boot.
If main_sdhci0 device tree node is disabled then the the index of
main_sdhci1 node becomes 0 which leads to break in boot flow. Therefore,
add an ali
Function spl_boot_mode() is called in common/spl/spl_mmc.c, to find the
boot mode for a given boot device. This function was renamed to
spl_mmc_boot_mode() by commit e97590654aea4c964f49bd915543a417d0c76996.
Therefore, rename spl_boot_mode to spl_mmc_boot_mode.
Fixes: 57dba04afbb7 ("arm: mach-k3:
On Thu, 3 Jun 2021 09:46:48 +0200
Heinrich Schuchardt wrote:
Hi Heinrich,
> On 6/2/21 3:08 PM, Ramon Fried wrote:
> > On Tue, Jun 1, 2021 at 12:35 AM Heinrich Schuchardt
> > wrote:
> >>
> >> Dear all,
> >>
> >> network is broken in U-Boot on orangepi_pc_defconfig:
Thanks for the report!
>
The following series of patches add support for,
- HS200/HS400 speed modes
- eMMC boot mode
- gpt and FDT library overlay
This series of patches,
- dependent on
https://patchwork.ozlabs.org/project/uboot/list/?series=237442
- applies on top of,
https://patchwork.ozlabs.org/project/uboot/list/
On 01/06/21, Michal Simek wrote:
>
>
> On 6/1/21 9:35 AM, Jorge Ramirez-Ortiz, Foundries wrote:
> > On 01/06/21, Michal Simek wrote:
> >>
> >>
> >> On 6/1/21 8:09 AM, Jorge Ramirez-Ortiz wrote:
> >>> Use the more generic reset-gpios propery name.
> >>>
> >>> Signed-off-by: Jorge Ramirez-Ortiz
>
On 24/05/21 19:53, Adam Ford wrote:
> The driver is based on the Versaclock driver from the Linux code, but
> do differences in the clock API between them, some pieces had to change.
s/do/due to/ ?
s/had to change/had to be changed/
> This driver creates a mux, pfd, pll, and a series of fod ouput
psgtr node should be below pinctrl for easier comparion among dts files.
That's why move that nodes to different location.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-zcu100-revC.dts | 14 +++---
arch/arm/dts/zynqmp-zcu106-revA.dts | 14 +++---
2 files changed, 14 insert
Historically dpdma and dpsub are placed at the end of files. Move nodes
there for easier comparison among dts files.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/dts/zynqmp-
dp_aclk is not used anywhere that's why remove it.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-clk-ccf.dtsi | 7 ---
1 file changed, 7 deletions(-)
diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index 987792e5c511..5ee7aa244552 100644
--- a/arch/ar
Trivial patch.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
index b0506c08418e..8f361e47bda1 100644
--- a/arch/arm/dts/zynqmp-zc175
dwc3 can be used only for higher speeds than super-speed that's why
explicitly set it up.
This is also aligned with other ZynqMP dts files.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 1 +
arch/arm/dts/zynqmp-zcu106-revA.dts | 1 +
arch/arm/dts/zynqmp-zcu111-
Remove unused phy.h from zc1232 DTS.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-zc1232-revA.dts | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/dts/zynqmp-zc1232-revA.dts
b/arch/arm/dts/zynqmp-zc1232-revA.dts
index 65dd4e1f3a5d..7543855c9fda 100644
--- a/arch/arm/dts/zynqm
Hi,
this series is trying to clean and sync DTS files. At the end we want to
have all these files be in sync with the Linux kernel based on DT binding
available in the Linux kernel.
Thanks,
Michal
Michal Simek (6):
arm64: zynqmp: Remove additional header from zc1232 DT
arm64: zynqmp: Add ma
On Thu, Jun 3, 2021 at 2:43 AM 陈健洪 wrote:
>
> Hi, Peter:
>
> 在 2021/6/2 19:51, Peter Robinson 写道:
> > On Wed, Jun 2, 2021 at 12:47 PM Joseph Chen wrote:
> >> RK3568 is a high-performance and low power quad-core application
> >> processor designed for personal mobile internet device and AIoT
> >>
Commit 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency") leads to
network failure on the OrangePi PC.
=> dhcp
sun8i_emac_eth_start: Timeout
According to the commit message the change of the MDIO frequency is only
required for external PHYs.
Fixes: 4f0278dac56a ("net: sun8i-emac: Low
pca953x also depends on i2c that's why add dependency to Kconfig.
Where GPIO is enabled but I2C compilation error pops up.
Signed-off-by: Michal Simek
---
drivers/gpio/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index d
On 6/2/21 3:08 PM, Ramon Fried wrote:
On Tue, Jun 1, 2021 at 12:35 AM Heinrich Schuchardt wrote:
Dear all,
network is broken in U-Boot on orangepi_pc_defconfig:
U-Boot 2021.07-rc3-00059-gd8729a114e (May 31 2021 - 21:26:56 +)
Allwinner Technology
eth0: ethernet@1c3
=> dhcp
sun8i_emac_
Am 3. Juni 2021 04:51:19 MESZ schrieb Yangbo Lu :
>Drop CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33.
>CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT
>is used instead.
>
>Signed-off-by: Yangbo Lu
Acked-by: Michael Walle [for kontron-sl28]
Hi Grzegorz
On 6/2/21 7:09 PM, Grzegorz Szymaszek wrote:
> Enable the SDMMC2 device tree node, as well as the pins it uses, in
> U-Boot SPL.
>
> Signed-off-by: Grzegorz Szymaszek
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> ---
> Changes for v2:
>- rebased on current master
>- added
Hi Grzegorz
On 6/2/21 7:09 PM, Grzegorz Szymaszek wrote:
> Enable the SDMMC2 eMMC high-speed DDR mode as it is done in the
> corresponding Linux kernel device tree.
>
> Signed-off-by: Grzegorz Szymaszek
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> ---
> Changes for v2:
>- rebased on curr
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