The current Makefile rule requires there to be a 'Module' line in the
pylint output, like this:
* Module binman.fip_util
This line only appears if pylint has some comments about the module. We
cannot rely on it for naming.
Update the code to instead use the filename as the
add kaslrseed key word to extlinux.conf,
which means generate kaslr-seed for linux
with this patch exlinux.conf boot item looks like
label l0
menu testing
linux /boot/vmlinuz-5.15.16-arm
initrd /boot/initramfs-5.15.16-arm.img
fdtdir /boot/dtbs/5.15.16-arm/
On Fri, Jan 28, 2022 at 8:48 PM Tim Harvey wrote:
>
> On Fri, Jan 28, 2022 at 6:04 PM Adam Ford wrote:
> >
> > On Fri, Jan 28, 2022 at 7:50 PM Tim Harvey wrote:
> > >
> > > On Wed, Jan 26, 2022 at 10:36 AM Adam Ford wrote:
> > > >
> > > > On Wed, Jan 26, 2022 at 12:31 PM Michael Nazzareno
On 1/26/22 09:38, Jesse Taube wrote:
On 1/26/22 09:13, Andre Przywara wrote:
On Tue, 4 Jan 2022 19:35:06 -0500
Jesse Taube wrote:
Hi Jesse,
I was checking some bits and pieces here, so sorry for the delay. I saw
your v2, and will review that ASAP, so that we get one step closer. Please
On 1/28/22 21:37, Andre Przywara wrote:
On Fri, 28 Jan 2022 21:31:28 -0500
Jesse Taube wrote:
On 1/28/22 21:25, Andre Przywara wrote:
On Wed, 26 Jan 2022 08:53:28 -0500
Jesse Taube wrote:
From: Icenowy Zheng
Add device tree files for suniv and
Lichee Pi Nano it is a board based on
On Fri, Jan 28, 2022 at 6:04 PM Adam Ford wrote:
>
> On Fri, Jan 28, 2022 at 7:50 PM Tim Harvey wrote:
> >
> > On Wed, Jan 26, 2022 at 10:36 AM Adam Ford wrote:
> > >
> > > On Wed, Jan 26, 2022 at 12:31 PM Michael Nazzareno Trimarchi
> > > wrote:
> > > >
> > > > HI Adam
> > > >
> > > > On Wed,
On 1/28/22 21:40, Andre Przywara wrote:
On Wed, 26 Jan 2022 08:53:17 -0500
Jesse Taube wrote:
Hi Jesse,
This patch set aims to add support for the SUNIV and F1C100s.
Support has been in linux for a while now, but not in u-boot.
This patchset contains:
- CPU specific initialization code
-
On 1/28/22 21:05, Andre Przywara wrote:
On Wed, 26 Jan 2022 08:53:20 -0500
Jesse Taube wrote:
From: Icenowy Zheng
Some Allwinner SoCs use ARM926EJ-S core.
Add Allwinner/sunXi specific code to ARM926EJ-S CPU dircetory.
It looks like we eventually won't need this, since the SPL linker
On Wed, 26 Jan 2022 08:53:17 -0500
Jesse Taube wrote:
Hi Jesse,
> This patch set aims to add support for the SUNIV and F1C100s.
> Support has been in linux for a while now, but not in u-boot.
>
> This patchset contains:
> - CPU specific initialization code
> - SUNIV dram driver
> - SUNIV clock
On Fri, 28 Jan 2022 21:31:28 -0500
Jesse Taube wrote:
> On 1/28/22 21:25, Andre Przywara wrote:
> > On Wed, 26 Jan 2022 08:53:28 -0500
> > Jesse Taube wrote:
> >
> >> From: Icenowy Zheng
> >>
> >> Add device tree files for suniv and
> >> Lichee Pi Nano it is a board based on F1C100s.
> >
On 1/28/22 21:25, Andre Przywara wrote:
On Wed, 26 Jan 2022 08:53:28 -0500
Jesse Taube wrote:
From: Icenowy Zheng
Add device tree files for suniv and
Lichee Pi Nano it is a board based on F1C100s.
As mentioned in the other email, please do a 1:1 copy from the current
Linux tree. Yes,
On Wed, 26 Jan 2022 08:53:28 -0500
Jesse Taube wrote:
> From: Icenowy Zheng
>
> Add device tree files for suniv and
> Lichee Pi Nano it is a board based on F1C100s.
As mentioned in the other email, please do a 1:1 copy from the current
Linux tree. Yes, this will miss MMC and USB, but I am
On Wed, 26 Jan 2022 08:53:26 -0500
Jesse Taube wrote:
> From: Icenowy Zheng
>
> Adds support for SUNIV and the F1C100s.
>
> Signed-off-by: Icenowy Zheng
> Signed-off-by: Jesse Taube
With that comment fixed, as you mentioned in the reply to this mail,
and with making sure the V3s comment
On Wed, 26 Jan 2022 08:53:23 -0500
Jesse Taube wrote:
> From: Icenowy Zheng
>
> This patch aims to add header files for the suniv.
> The header files included add support for uart, and clocks.
>
> Signed-off-by: Icenowy Zheng
> Signed-off-by: Jesse Taube
Thanks for the changes, looks good
On Wed, 26 Jan 2022 08:53:21 -0500
Jesse Taube wrote:
> From: Icenowy Zheng
>
> This commit introduces suniv dt-bindings headers needed for
> device tree files.
Looks better, but please do a verbatim copy from a (recent) Linux tree,
using the mainline file names, and noting the tag or commit
On Wed, 26 Jan 2022 08:53:20 -0500
Jesse Taube wrote:
> From: Icenowy Zheng
>
> Some Allwinner SoCs use ARM926EJ-S core.
>
> Add Allwinner/sunXi specific code to ARM926EJ-S CPU dircetory.
It looks like we eventually won't need this, since the SPL linker script
is basically identical to the
On Fri, Jan 28, 2022 at 7:50 PM Tim Harvey wrote:
>
> On Wed, Jan 26, 2022 at 10:36 AM Adam Ford wrote:
> >
> > On Wed, Jan 26, 2022 at 12:31 PM Michael Nazzareno Trimarchi
> > wrote:
> > >
> > > HI Adam
> > >
> > > On Wed, Jan 26, 2022 at 7:01 PM Adam Ford wrote:
> > > >
> > > > On Wed, Jan
On Wed, Jan 26, 2022 at 10:36 AM Adam Ford wrote:
>
> On Wed, Jan 26, 2022 at 12:31 PM Michael Nazzareno Trimarchi
> wrote:
> >
> > HI Adam
> >
> > On Wed, Jan 26, 2022 at 7:01 PM Adam Ford wrote:
> > >
> > > On Wed, Jan 26, 2022 at 11:24 AM Michael Nazzareno Trimarchi
> > > wrote:
> > > >
> >
On Wed, Jan 26, 2022 at 02:33:34AM +, 张 宁 wrote:
> Hi, Chris Morgan
>
> thank you to add kaslrseed to U-boot, do you have plan to add it to
> extlinux.conf?
If extlinux.conf can run commands for U-Boot it should be as simple as doing the
following:
Load your devicetree from external
On Wed, Dec 15, 2021 at 02:53:43PM +1300, Campbell Suter wrote:
> Previously, if root had more than 256 files or otherwise needed to be an
> ldir, sqfsls would emit the error 'Inode not found.' which was caused by
> code in sqfs_search_dir assuming it was a regular directory inode.
>
>
On RK3568, a register bit must be set to enable Enhanced Strobe.
However, it appears that the address of this register may differ from
vendor to vendor and should be read from the underlying MMC IP. Let the
Rockchip SDHCI driver read this address and set the relevant bit when
Enhanced Strobe
On RK3399, a register bit must be set to enable Enhanced Strobe.
Let the Rockchip SDHCI driver set it when Enhanced Strobe configuration
is requested. However, having it set makes the lower-speed modes stop
working and makes reinitialization fail, so let it be unset as needed in
set_control_reg().
The Rockchip RK3399 eMMC PHY has to be power-cycled while changing its
clock speed to some higher speeds. This is dependent on the desired
SDHCI clock speed, and it looks like the PHY should be powered off while
setting the SDHCI clock in these cases.
Commit ac804143cfd1 ("mmc: rockchip_sdhci:
Delegate setting the Enhanced Strobe configuration to individual drivers
if they set a function for it. Return -ENOTSUPP if they do not, like
what the MMC uclass does.
Signed-off-by: Alper Nebi Yasak
Reviewed-by: Jaehoon Chung
---
Changes in v4:
- Add comment for SDHCI set_enhanced_strobe()
My rk3399-gru-kevin has some problems with the eMMC. The board can boot
to U-Boot proper with the eMMC working at a low speed, but trying to
reinitialize it with "mmc dev 0" or "mmc rescan" makes it unusable. If
the HS400 mode is enabled, it times out while executing tuning and
doesn't even start
On 1/28/22 09:28, Andre Przywara wrote:
On Thu, 27 Jan 2022 23:51:09 -0500
Jesse Taube wrote:
Hi Jesse,
On 1/27/22 19:41, Andre Przywara wrote:
On Thu, 27 Jan 2022 15:40:13 -0500
Jesse Taube wrote:
Hi,
On 1/27/22 05:21, Andre Przywara wrote:
On Wed, 26 Jan 2022 08:53:19 -0500
On Wed, Dec 22, 2021 at 05:36:04PM -0500, Samuel Dionne-Riel wrote:
> Signed-off-by: Samuel Dionne-Riel
> Reviewed-by: Simon Glass
> ---
> arch/sandbox/dts/test.dts | 10 +++
> configs/sandbox_defconfig | 2 +
> drivers/Kconfig| 2 +
> drivers/Makefile
On 21/01/2022 18:20, Simon Glass wrote:
> On Tue, 11 Jan 2022 at 06:40, Alper Nebi Yasak
> wrote:
>> diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
>> index 278473899c7c..f0d7ba4774d6 100644
>> --- a/drivers/mmc/rockchip_sdhci.c
>> +++ b/drivers/mmc/rockchip_sdhci.c
>>
We don't have to recalculate the image hash every time we check against a
new db/dbx entry. So let's add a flag forcing it to run once since we only
support sha256 hashes
Suggested-by: Heinrich Schuchardt
Signed-off-by: Ilias Apalodimas
---
lib/efi_loader/efi_signature.c | 5 -
1 file
A mix of signatures and hashes in db doesn't always work as intended.
Currently if the digest algorithm is not explicitly set to sha256 we
stop walking the security database and reject the image.
That's problematic in case we find and try to check a signature before
inspecting the sha256 hash.
On Thu, Dec 16, 2021 at 11:26:38AM +0100, Matthias Schiffer wrote:
> Having U-Boot look up the passed partition name even though an alias
> exists is unexpected, leading to warning messages (when the alias name
> doesn't exist as a real partition name) or the use of the wrong
> partition.
>
>
On Wed, Oct 13, 2021 at 05:01:37PM +0200, Patrick Delaunay wrote:
> In DFU v1.1 specification [1] the DFU_UPLOAD (Short Frame)
> is handled only in dfuUPLOADIDLE state:
>
> - Figure A.1 Interface state transition diagram
>
> - the state description in chapter A.2
>
> A.2.3 State 2 dfuIDLE
>
On Sun, May 09, 2021 at 01:25:24AM +0300, Roman Stratiienko wrote:
> In case CONFIG_FASTBOOT_FLASH_MMC_DEV == 0, compile-time condition
> is not met and fastboot_set_reboot_flag() fails.
>
> Fixes: a362ce214f03 ("fastboot: Implement generic fastboot_set_reboot_flag")
> Signed-off-by: Roman
From: Jan Kiszka
We can and should run the node generator only when creating a new image.
When we read it back, there is no need to generate nodes - they already
exits, and binman does not dive that deep into the image - and there is
no way to provide the required fdt-list. So store the mode in
On RISC-V a new UEFI protocol has been introduced. Support printing
its GUID using %pUs.
Cc: Sunil V L
Signed-off-by: Heinrich Schuchardt
---
cf.
[RFC PATCH V2 1/2] efi_loader: Enable RISCV_EFI_BOOT_PROTOCOL support
https://lists.denx.de/pipermail/u-boot/2022-January/473505.html
---
lib/uuid.c
Fix the following warning in SPL and make sure that even DTs which
enforce Vbus detection using u-boot,force-vbus-detection;, the DFU
in SPL will work.
dwc2-udc-otg usb-otg@4900: prop pinctrl-0 index 0 invalid phandle
Signed-off-by: Marek Vasut
Cc: Patrice Chotard
Cc: Patrick Delaunay
---
Hello Tim,
> -Original Message-
> From: Tim Harvey
> Sent: Friday, January 28, 2022 12:20 AM
> To: ZHIZHIKIN Andrey
> Cc: u-boot
> Subject: Re: [PATCH] imx: ventana: correct splashimage load address
>
>
> On Tue, Jan 18, 2022 at 8:40 AM Tim Harvey wrote:
> >
> > On Mon, Jan 17, 2022
On 2022-01-28 19:19, Aurelien Jarno wrote:
> On 2022-01-28 19:03, Heinrich Schuchardt wrote:
> > On 1/28/22 14:47, Alexandre Ghiti wrote:
> > > The following description is copied from the equivalent patch for the
> > > Linux Kernel proposed by Aurelien Jarno:
> > >
> > > From version 2.38,
On 1/28/22 19:03, Heinrich Schuchardt wrote:
On 1/28/22 14:47, Alexandre Ghiti wrote:
The following description is copied from the equivalent patch for the
Linux Kernel proposed by Aurelien Jarno:
From version 2.38, binutils default to ISA spec version 20191213. This
means that the csr
On 2022-01-28 19:03, Heinrich Schuchardt wrote:
> On 1/28/22 14:47, Alexandre Ghiti wrote:
> > The following description is copied from the equivalent patch for the
> > Linux Kernel proposed by Aurelien Jarno:
> >
> > From version 2.38, binutils default to ISA spec version 20191213. This
> >
On 1/28/22 14:47, Alexandre Ghiti wrote:
The following description is copied from the equivalent patch for the
Linux Kernel proposed by Aurelien Jarno:
From version 2.38, binutils default to ISA spec version 20191213. This
means that the csr read/write (csrr*/csrw*) instructions and fence.i
On 1/28/22 08:30, Jaehoon Chung wrote:
Hi Marek,
Hi,
On 1/28/22 12:40, Marek Vasut wrote:
This reverts commit b5874b552ffa09bc1dc5dec6b5dd376c62dab45d.
It seems the iMX8MM SDHC controller always reports DAT0 line status
as zero after voltage switch at the end of mmc_switch_voltage(), even
On 1/28/22 16:18, Sunil V L wrote:
This adds support for new RISCV_EFI_BOOT_PROTOCOL to
communicate the boot hart ID to bootloader/kernel on RISC-V
UEFI platforms.
The specification of the protocol is hosted at:
https://github.com/riscv-non-isa/riscv-uefi
Signed-off-by: Sunil V L
---
On 1/28/22 16:18, Sunil V L wrote:
Add a test for the RISCV_EFI_BOOT_PROTOCOL.
Signed-off-by: Sunil V L
---
lib/efi_selftest/Makefile | 1 +
lib/efi_selftest/efi_selftest_riscv.c | 119 ++
2 files changed, 120 insertions(+)
create mode 100644
On Mon, Dec 06, 2021 at 02:45:11PM +0900, Masami Hiramatsu wrote:
> Since dfu is not only used for USB, and some platform only
> supports DFU_OVER_TFTP or EFI capsule update, dfu_alt_info
> is defined on such platforms too.
>
> For such platform, 'dfu list' command is useful to check
> how the
SION (Software Input On Field) - force the select mode input path
Signed-off-by: Angus Ainslie
---
arch/arm/dts/imx8mq-pinfunc.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/imx8mq-pinfunc.h b/arch/arm/dts/imx8mq-pinfunc.h
index b94b02080a..b51e4faea5 100644
---
to adjust the root path length.
Eg to 256 from Linux Kernel
Signed-off-by: Andre Kalb
---
include/net.h | 2 +-
net/Kconfig | 6 ++
net/bootp.c | 2 +-
3 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/include/net.h b/include/net.h
index b02e4f630c..6f3f3dfcd4 100644
---
On Thu, Sep 30, 2021 at 06:22:06PM +0200, Frieder Schrempf wrote:
> From: Frieder Schrempf
>
> This doesn't include any functional changes, but allows us to use the
> size parameter to report the actual written bytes back to the caller.
>
> This is useful in cases of unaligned writes to serial
Add a test for the RISCV_EFI_BOOT_PROTOCOL.
Signed-off-by: Sunil V L
---
lib/efi_selftest/Makefile | 1 +
lib/efi_selftest/efi_selftest_riscv.c | 119 ++
2 files changed, 120 insertions(+)
create mode 100644 lib/efi_selftest/efi_selftest_riscv.c
diff
This adds support for new RISCV_EFI_BOOT_PROTOCOL to
communicate the boot hart ID to bootloader/kernel on RISC-V
UEFI platforms.
The specification of the protocol is hosted at:
https://github.com/riscv-non-isa/riscv-uefi
Signed-off-by: Sunil V L
---
include/efi_api.h | 4 +++
This patch series adds the support in u-boot for new RISCV_EFI_BOOT_PROTOCOL
for RISC-V
UEFI platforms. This protocol is required to communicate the boot hart ID to the
bootloader/kernel which need to follow the EFI calling conventions.
The latest draft spec of this new protocol is available at
On Thu, Jan 27, 2022 at 9:57 AM Heinrich Schuchardt
wrote:
>
> unmatched.rst describes booting from SD card or from SPI. But only for
> booting from SPI the boot selection settings are described.
>
> Add the missing information.
>
> Fix a typo 'uSD'.
>
> Signed-off-by: Heinrich Schuchardt
> ---
On Thu, 27 Jan 2022 23:51:09 -0500
Jesse Taube wrote:
Hi Jesse,
> On 1/27/22 19:41, Andre Przywara wrote:
> > On Thu, 27 Jan 2022 15:40:13 -0500
> > Jesse Taube wrote:
> >
> > Hi,
> >
> >> On 1/27/22 05:21, Andre Przywara wrote:
> >>> On Wed, 26 Jan 2022 08:53:19 -0500
> >>> Jesse Taube
On Fri, Jan 28, 2022 at 9:47 PM Alexandre Ghiti
wrote:
>
> The following description is copied from the equivalent patch for the
> Linux Kernel proposed by Aurelien Jarno:
>
> From version 2.38, binutils default to ISA spec version 20191213. This
> means that the csr read/write (csrr*/csrw*)
On Thu, Jan 27, 2022 at 2:11 PM Anup Patel wrote:
>
> Quite a few RISC-V emulators and ISS (including Spike) have host
> transfer interface (HTIF) based console. This patch adds HTIF
> based console driver for RISC-V platforms which depends totally
> on DT node for HTIF register base address.
>
>
The following description is copied from the equivalent patch for the
Linux Kernel proposed by Aurelien Jarno:
>From version 2.38, binutils default to ISA spec version 20191213. This
means that the csr read/write (csrr*/csrw*) instructions and fence.i
instruction has separated from the `I`
Add the PDU001 board specific DT files to MAINTAINERS. This should
help for better tracking of changes to these files.
Signed-off-by: Felix Brack
---
board/eets/pdu001/MAINTAINERS | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/board/eets/pdu001/MAINTAINERS
On Thu, Jan 27, 2022 at 2:11 PM Anup Patel wrote:
>
> Enable support for HTIF console so that we can use QEMU RISC-V U-Boot
> on RISC-V emulators and ISS having it.
>
> Signed-off-by: Anup Patel
> Reviewed-by: Philipp Tomsich
> Reviewed-by: Rick Chen
> ---
> board/emulation/qemu-riscv/Kconfig
On Fri, Jan 28, 2022 at 02:01:41PM +0900, AKASHI Takahiro wrote:
> Hi, Simon,
>
>
> On Thu, Jan 27, 2022 at 08:05:56AM -0700, Simon Glass wrote:
> > Hi Takahiro,
> >
> > On Thu, 9 Dec 2021 at 23:58, AKASHI Takahiro
> > wrote:
> > >
> > > # This is a kind of snapshot of my current work.
> > >
On Fri, 2022-01-28 at 11:18 +0100, Heiko Thiery wrote:
> This option is selected implicitly when [SPL_]CLK_IMX8MM is selected.
>
> Signed-off-by: Heiko Thiery
Reviewed-by: Marcel Ziswiler
[snip]
On Fri, 2022-01-28 at 11:18 +0100, Heiko Thiery wrote:
> The clock composite is required when using the clock framework. So
> select it automatically.
>
> Signed-off-by: Heiko Thiery
Reviewed-by: Marcel Ziswiler
[snip]
Hello Grant,
Am Thu, Jan 27, 2022 at 04:46:48PM - schrieb Grant Edwards:
> What is the "right" way to modify a defconfig file?
>
> Most sources I've found just say things like "edit the defconfig
> file". That seems error-prone -- especially when dealing with settings
> that have side
This option is selected implicitly when [SPL_]CLK_IMX8MM is selected.
Signed-off-by: Heiko Thiery
---
configs/imx8mm-cl-iot-gate-optee_defconfig| 2 --
configs/imx8mm-cl-iot-gate_defconfig | 2 --
configs/imx8mm-icore-mx8mm-ctouch2_defconfig | 2 --
The clock composite is required when using the clock framework. So
select it automatically.
Signed-off-by: Heiko Thiery
---
drivers/clk/imx/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 96721bcbf3..1800b1860b 100644
---
sdl.c is compiled against the SDL library.
Trying to redefine wchar_t with -fshort-wchar is not necessary
and leads to build failures when compiling against musl.
Cc: Milan P. Stanić
Signed-off-by: Heinrich Schuchardt
---
v2:
fix a build error with clang by adding -fno-lto for building
Hi All,
On 27/01/22 2:42 pm, Aswath Govindraju wrote:
> The following series of patches,
> - add support for MultiLink on Sierra SerDes
> - Also adds the required to configs, dt node changes
> to enable this on J721e common processor board.
>
> Notes:
> - Patches 1, 2, 3, 4, 5, 6, 7, 8, 13,
Add configs to enable booting ethfw core in j721e
Signed-off-by: Aswath Govindraju
---
configs/j721e_evm_a72_defconfig | 2 +-
include/configs/j721e_evm.h | 19 ++-
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/configs/j721e_evm_a72_defconfig
Add support for QSGMII multilink configuration.
Signed-off-by: Aswath Govindraju
---
.../arm/dts/k3-j721e-common-proc-board-u-boot.dtsi | 5 +
arch/arm/dts/k3-j721e-common-proc-board.dts| 14 +++---
arch/arm/dts/k3-j721e-r5-common-proc-board.dts | 12 ++--
3
In some cases, a single SerDes instance can be shared between two different
processors, each using a separate link. In these cases, the SerDes
configuration is done in an earlier boot stage. Therefore, add support to
skip reconfiguring, if it is was already configured beforehand.
Signed-off-by:
From: Swapnil Jakhade
Add register sequences for PCIe + QSGMII PHY multilink configuration.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 378 ++-
1 file changed, 377 insertions(+), 1 deletion(-)
diff --git
From: Swapnil Jakhade
Add support for multilink configuration of Sierra PHY. Currently,
maximum two links are supported.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 153 +--
1 file changed, 145
From: Swapnil Jakhade
Add single link PCIe register configurations for no SSC and internal
SSC. Also, add missing PMA lane registers for external SSC.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 218 ++-
1
From: Swapnil Jakhade
Check if PMA cmn_ready is set indicating the startup process is complete.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 35
1 file changed, 35 insertions(+)
diff --git
From: Swapnil Jakhade
PIPE phy status is used to communicate the completion of several PHY
functions. Check if PHY is ready for operation while configured for
PIPE mode during startup.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
From: Swapnil Jakhade
Add PHY PCS common register configuration sequences for single link.
Update single link PCIe register sequence accordingly.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 38
1 file
From: Swapnil Jakhade
No functional change. Rename some regmap variables as mentioned in Sierra
register description documentation.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 12 ++--
1 file changed, 6 insertions(+),
From: Swapnil Jakhade
Add support to get SSC type from DT.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
From: Swapnil Jakhade
Sierra driver currently supports single link configurations only. Prepare
driver to support multilink multiprotocol configurations along with
different SSC modes.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
From: Swapnil Jakhade
Add binding to specify Spread Spectrum Clocking mode used
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
include/dt-bindings/phy/phy-cadence.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/dt-bindings/phy/phy-cadence.h
The PLL_CMNLC clocks are modelled as a child clock device of seirra. In the
function device_probe, the corresponding clocks are probed before calling
the device's probe. The PLL_CMNLC mux clock can only be created after the
device's probe. Therefore, move assigned-clocks and assigned-clock-parents
Add support for probing, initializing and powering, SerDes0 instance.
Signed-off-by: Aswath Govindraju
---
board/ti/j721e/evm.c | 37 +
1 file changed, 37 insertions(+)
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index 077d83420c9c..ad85b9d50115
Fix the condition for setting P_ENABLE_FORCE bit, by syncing with the
driver in kernel.
Signed-off-by: Aswath Govindraju
---
drivers/phy/ti/phy-j721e-wiz.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index
Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has
two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from
pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as a clock so that it's
possible to select one of these two inputs from device tree.
Signed-off-by: Aswath
Add a driver of type UCLASS_PHY for each of the link nodes in the serdes
instance.
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 116 +++
1 file changed, 75 insertions(+), 41 deletions(-)
diff --git
From: Kishon Vijay Abraham I
Add missing clk_disable_unprepare() in cdns_sierra_phy_remove().
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
From: Kishon Vijay Abraham I
Instead of having separate structure members for each input clock, add
an array for the input clocks within "struct cdns_sierra_phy". This is
in preparation for adding more input clocks required for supporting
additional clock combination.
Signed-off-by: Kishon
From: Kishon Vijay Abraham I
No functional change. Group devm_reset_control_get() and
devm_reset_control_get_optional() to a separate function.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 19 +++
1 file
From: Kishon Vijay Abraham I
Commit 39b823381d9d ("phy: cadence: Add driver for Sierra PHY")
de-asserts PHY_RESET even before the configurations are loaded in
phy_init(). However PHY_RESET should be de-asserted only after
all the configurations has been initialized, instead of de-asserting
in
From: Kishon Vijay Abraham I
No functional change. Group all devm_clk_get_optional() to a
separate function.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 57 +++-
1 file changed, 35 insertions(+), 22
From: Kishon Vijay Abraham I
Cadence Sierra PHY driver registers PHY using devm_phy_create()
for all sub-nodes of Sierra device tree node. However Sierra device
tree node can have sub-nodes for the various clocks in addtion to the
PHY. Use devm_phy_create() only for nodes with name "phy" (or
From: Sanket Parmar
Updated values of USB3 related Sierra PHY registers.
This change fixes USB3 device disconnect issue observed
while enternig U1/U2 state.
Signed-off-by: Sanket Parmar
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 27
The following series of patches add support for PCIe + QSGMII multilink
configuration on J721e EVM. The PHY lanes are configured in U-Boot and,
PCIe driver in Kernel and QSGMII driver in the ethernet firmware use them.
Notes:
- Patches 1 -8 and 13 - 22 are ported from upstream kernel
v5.17-rc1
On Fri, Jan 28, 2022 at 08:30:12AM +0100, Heinrich Schuchardt wrote:
> On 1/27/22 23:36, Ilias Apalodimas wrote:
> > A mix of signatures and hashes in db doesn't always work as intended.
> > Currently if the digest algorithm is not supported we stop walking the
> > security database and reject the
93 matches
Mail list logo
