On 06.04.22 11:39, Pali Rohár wrote:
CONFIG_ETHPRIME defines primary ethernet device and env variable $ethact
stores currently active ethernet device.
So there is no point to set ethact= in default environment. Instead set
CONFIG_ETHPRIME properly.
Signed-off-by: Pali Rohár
---
Hi Ramon,
On 27.04.22 12:41, Marek Behún wrote:
From: Marek Behún
Hello Stefan,
here come some refactors, cleanups and fixed for the mvneta driver.
Ramon, you've already reviewed those patches. Thanks for this. The
patches are assigned to me in patchwork, which makes perhaps sense,
as some
On 29.04.22 13:53, Pali Rohár wrote:
This is A385 register.
Signed-off-by: Pali Rohár
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
board/CZ.NIC/turris_omnia/turris_omnia.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
On 29.04.22 17:49, Josef Schlehofer wrote:
This command is useful in U-boot scripts and it is being used by
OpenWrt bootscript for this board [1]. Otherwise shell scripting
commands are enabled by default in cmd/Kconfig.
[1]
On 02.05.22 05:16, Chris Packham wrote:
MPP55 is used as a reset connected to the L3 switch chip. This doesn't
matter for u-boot as it doesn't use the L3 switch but it is useful to
be able to toggle the switch in/out of reset for the OS.
Signed-off-by: Chris Packham
Reviewed-by: Stefan Roese
lib/charset.c is not optional for
EFI_APP || EFI_LOADER || UFS || UT_UNICODE.
These must select CONFIG_CHARSET.
Fixes: 726cd9836db0 ("efi: Make unicode printf available to the app")
Signed-off-by: Heinrich Schuchardt
---
drivers/ufs/Kconfig| 1 +
lib/Kconfig| 5 -
Hello Eugen,
On 29.04.22 16:22, Eugen Hristev wrote:
> 24aa025e48 is a variant of 24aa02e48 that has a page size of 16 bytes.
>
> Signed-off-by: Eugen Hristev
> ---
> drivers/misc/i2c_eeprom.c | 8
> 1 file changed, 8 insertions(+)
Reviewed-by: Heiko Schocher
bye,
Heiko
--
DENX
MPP55 is used as a reset connected to the L3 switch chip. This doesn't
matter for u-boot as it doesn't use the L3 switch but it is useful to
be able to toggle the switch in/out of reset for the OS.
Signed-off-by: Chris Packham
---
I sent this out a while back but it was part of a series that has
On 4/28/22 10:09, Masahisa Kojima wrote:
This commit adds the distro_boot entries into the bootmenu.
The bootmenu read the "boot_targets" U-Boot environment variable
and enumerate it.
User can select the distro boot entry, then bootmenu executes
"run bootcmd_xxx" command.
The bootmenu also
On 4/28/22 10:09, Masahisa Kojima wrote:
This commit adds the UEFI related menu entries
into the bootmenu.
User can select which UEFI "Boot" option to execute
from bootmenu, then bootmenu sets the "BootNext" UEFI
variable and invoke efi bootmgr. The efi bootmgr
will handle the "BootNext"
* correct output for timeout > 99 s
* don't use spaces to advance to the output column
Signed-off-by: Heinrich Schuchardt
---
cmd/bootmenu.c | 20 +++-
1 file changed, 7 insertions(+), 13 deletions(-)
diff --git a/cmd/bootmenu.c b/cmd/bootmenu.c
index d573487272..fe35607472
On 4/29/22 21:51, Heinrich Schuchardt wrote:
On 4/28/22 10:09, Masahisa Kojima wrote:
This is a preparation for succeeding addition of uefi boot
and distro boot menu entries into bootmenu.
The bootmenu_entry title is updated to u16 string because
uefi use u16 string. This commit also factors
On 4/28/22 10:09, Masahisa Kojima wrote:
From: AKASHI Takahiro
This function will be used in the next commit where some behavior
of EFI boot manager will be expanded.
Signed-off-by: AKASHI Takahiro
Reviewed-by: Ilias Apalodimas
Reviewed-by: Heinrich Schuchardt
---
No changes from
On Sun, 1 May 2022 16:52:31 +0200
Pali Rohár wrote:
> On Friday 08 April 2022 11:00:24 Pali Rohár wrote:
> > On Wednesday 06 April 2022 21:31:18 Marek Behún wrote:
> > > On Wed, 6 Apr 2022 11:39:34 +0200
> > > Pali Rohár wrote:
> > >
> > > > U-Boot for Turris Omnia is always compiled with
On Sun, May 1, 2022 at 7:43 PM Marek Vasut wrote:
>
> Long TFTP transfers lead to a wall of # characters on UART, which in
> the end may slow down the transfer itself. Use CONFIG_TFTP_TSIZE to
> print progress in fewer # characters.
>
> Signed-off-by: Marek Vasut
> Cc: Patrick Delaunay
> Cc:
On Sun, May 1, 2022 at 7:43 PM Marek Vasut wrote:
>
> The DHCOM does ship with KS8851 with 1.5 kiB packet buffer. The DHSOM
> may be extended with other MAC options connected to FMC2 bus, like the
> DM9000, wih similar limitations. Use default CONFIG_TFTP_BLOCKSIZE of
> 1468 Bytes instead of 1536
Effective page number mask for MAS2 register is stored in macro MAS2_EPN.
Fixes: 2146cf56821c ("Reworked FSL Book-E TLB macros to be more readable")
Signed-off-by: Pali Rohár
---
arch/powerpc/include/asm/mmu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Replace discuss with discard, that is what happens with packet with
incorrect checksum. Fix the typo.
Fixes: 4b37fd146bb ("Convert CONFIG_UDP_CHECKSUM to Kconfig")
Signed-off-by: Marek Vasut
Cc: Ramon Fried
Cc: Simon Glass
---
net/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Long TFTP transfers lead to a wall of # characters on UART, which in
the end may slow down the transfer itself. Use CONFIG_TFTP_TSIZE to
print progress in fewer # characters.
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice Chotard
Cc: Ramon Fried
---
The DHCOM does ship with KS8851 with 1.5 kiB packet buffer. The DHSOM
may be extended with other MAC options connected to FMC2 bus, like the
DM9000, wih similar limitations. Use default CONFIG_TFTP_BLOCKSIZE of
1468 Bytes instead of 1536 Bytes, which always avoids overflowing the
packet buffers of
On Sat, Apr 30, 2022 at 01:08:43AM +0100, Andre Przywara wrote:
> On Fri, 29 Apr 2022 14:14:19 -0400
> Tom Rini wrote:
>
> Hi,
>
> > On Fri, Apr 29, 2022 at 06:05:03PM +0200, Mark Kettenis wrote:
> > > > Date: Fri, 29 Apr 2022 11:31:00 -0400
> > > > From: Tom Rini
> > > >
> > > > On Fri, Apr
On Fri, Apr 29, 2022 at 07:03:16PM +0200, Heinrich Schuchardt wrote:
> Dear Tom,
>
> The following changes since commit 8b2b125e95c44bb007b4573945f4aedb8a56222c:
>
> Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx
> (2022-04-27 09:19:41 -0400)
>
> are available in the Git
On Sun, May 01, 2022 at 05:33:19PM +0200, Pali Rohár wrote:
> On Sunday 01 May 2022 11:14:21 Tom Rini wrote:
> > On Sun, May 01, 2022 at 04:44:16PM +0200, Pali Rohár wrote:
> > > On Sunday 01 May 2022 10:39:39 Tom Rini wrote:
> > > > On Sun, May 01, 2022 at 04:23:52PM +0200, Pali Rohár wrote:
> >
Header file asm/fsl_law.h already provides correct definition for second
and third PCIe controller (LAW_TRGT_IF_PCIE_2 and LAW_TRGT_IF_PCIE_3). But
is missing definition for the first PCIe controller (LAW_TRGT_IF_PCIE_1).
Note that existing definition for LAW_TRGT_IF_PCIE_2 and LAW_TRGT_IF_PCIE_3
On 4/28/22 10:09, Masahisa Kojima wrote:
To make user aware of the menu entry selection, menu always
appears regardless of the number of entry.
Signed-off-by: Masahisa Kojima
Reviewed-by: Heinrich Schuchardt
---
No changes since v4
Newly created in v4
common/menu.c | 2 +-
1 file
On Sunday 01 May 2022 11:14:21 Tom Rini wrote:
> On Sun, May 01, 2022 at 04:44:16PM +0200, Pali Rohár wrote:
> > On Sunday 01 May 2022 10:39:39 Tom Rini wrote:
> > > On Sun, May 01, 2022 at 04:23:52PM +0200, Pali Rohár wrote:
> > >
> > > > This reverts commit
On Friday 08 April 2022 00:18:48 Maciej W. Rozycki wrote:
> On Thu, 7 Apr 2022, Stefan Roese wrote:
>
> > > Hello! What do you think about this change? I think it is good
> > > compromise between enable this workaround for all builds on all boards
> > > and enable it only based on device id. Or
On Sun, May 1, 2022 at 4:48 AM Peng Fan (OSS) wrote:
>
>
>
> On 2022/5/1 0:14, Adam Ford wrote:
> > Certain platforms have the UART clocks exposed through the CCF.
> > When they are, it's possible to enable and query the clock(s)
> > for a given UART. Add support getting, enabling, and querying
>
On Sun, May 01, 2022 at 04:44:16PM +0200, Pali Rohár wrote:
> On Sunday 01 May 2022 10:39:39 Tom Rini wrote:
> > On Sun, May 01, 2022 at 04:23:52PM +0200, Pali Rohár wrote:
> >
> > > This reverts commit c7fad78ec0ee41b72a58bebb61959570eb937ab1.
> > >
> > > This commit made configuration,
On Wednesday 02 March 2022 12:47:50 Pali Rohár wrote:
> Some mPCIe cards are broken and their PIN 43 incorrectly that card is
> mSATA. U-Boot SPL on Turris Omnia is using PIN 43 for configuring PCIe
> vs SATA functionality on SerDes. Allow to configure functionality via
> additional env variable
On Friday 08 April 2022 11:00:24 Pali Rohár wrote:
> On Wednesday 06 April 2022 21:31:18 Marek Behún wrote:
> > On Wed, 6 Apr 2022 11:39:34 +0200
> > Pali Rohár wrote:
> >
> > > U-Boot for Turris Omnia is always compiled with MMC, SCSI and USB support,
> > > so always enable macros for booting
On Sunday 01 May 2022 10:39:39 Tom Rini wrote:
> On Sun, May 01, 2022 at 04:23:52PM +0200, Pali Rohár wrote:
>
> > This reverts commit c7fad78ec0ee41b72a58bebb61959570eb937ab1.
> >
> > This commit made configuration, understanding, maintenance, debugging and
> > future development of the
On Sunday 01 May 2022 10:38:31 Tom Rini wrote:
> On Sun, May 01, 2022 at 04:23:53PM +0200, Pali Rohár wrote:
>
> > This reverts commit 53fc71df0fce21d403400a9bc1532e08107c.
> >
> > These macros and their values are required for configuring CPLD memory
> > mapping in LBC. So revert them back.
On Sun, May 01, 2022 at 04:23:52PM +0200, Pali Rohár wrote:
> This reverts commit c7fad78ec0ee41b72a58bebb61959570eb937ab1.
>
> This commit made configuration, understanding, maintenance, debugging and
> future development of the powerpc/mpc85xx Local Bus Controller on P1/P2
> boards impossible.
On Sun, May 01, 2022 at 04:23:53PM +0200, Pali Rohár wrote:
> This reverts commit 53fc71df0fce21d403400a9bc1532e08107c.
>
> These macros and their values are required for configuring CPLD memory
> mapping in LBC. So revert them back.
>
> Signed-off-by: Pali Rohár
> ---
>
P1020RDB-PD has NAND with large page. All other P1/P2 RDB boards have NAND
with small page. According to P1/P2 RM documentation, for NAND with large
page it is needed to use 256 kB mapping and for small page just 32 kB.
Currenly in p1_p2_rdb_pc board code there is a mix of 32 kB and 1 MB
settings
This reverts commit c7fad78ec0ee41b72a58bebb61959570eb937ab1.
This commit made configuration, understanding, maintenance, debugging and
future development of the powerpc/mpc85xx Local Bus Controller on P1/P2
boards impossible.
All preliminary Base and Option registers depends on other code and C
This change allows to understand how are Preliminary Base and Option
registers configured and later fix improper configuration.
Signed-off-by: Pali Rohár
---
include/configs/P2041RDB.h | 7 ---
include/configs/corenet_ds.h | 8 +---
include/configs/p1_p2_rdb_pc.h | 11
FLASH NOR on P1020RDB-PD has size of 64 MB. On all other P1/P2 RDB boards
it has only size of 16 MB. So fix this size in TLB, LAW and LBC OR
registers.
Signed-off-by: Pali Rohár
---
board/freescale/p1_p2_rdb_pc/law.c | 4
board/freescale/p1_p2_rdb_pc/tlb.c | 6 ++
This reverts commit 53fc71df0fce21d403400a9bc1532e08107c.
These macros and their values are required for configuring CPLD memory
mapping in LBC. So revert them back.
Signed-off-by: Pali Rohár
---
include/configs/p1_p2_rdb_pc.h | 3 +++
1 file changed, 3 insertions(+)
diff --git
Per Freescale P1021RDB Combo board CPLD Specification V4.2, CPLD memory
space on all these P1/P2 RDB-PC boards, which use Lattice FPGA for CPLD
implementation, is only 128 kB long.
So decrease mapping size from 1 MB to 128 kB.
Note that E500 core, which is on P1/P2 boards does not support Book-E
On LBC (Local Bus Controller) are connected memory peripherals (NOR,
NAND, CPLD). Fix size mappings of all these peripherals. Size needs to
be correctly set in TLB, LAW and LBC OR registers. Use named macros for
human readable configuration.
Pali Rohár (6):
Revert "Convert CONFIG_SYS_BR0_PRELIM
On Sat, Apr 30, 2022 at 03:48:04PM +0200, Marek Behún wrote:
> On Sat, 30 Apr 2022 21:31:15 +0800
> Weijie Gao wrote:
>
> > On Fri, 2022-04-29 at 17:13 +0200, Marek Behún wrote:
> > > On Fri, 29 Apr 2022 15:59:44 +0800
> > > Weijie Gao wrote:
> > >
> > > > On Fri, 2022-04-29 at 08:15 +0200,
SoM revision 1.9 has replaced the ar8035 phy address 0 with an adin1300
at address 1. Because early SoMs had a hardware flaw, the ar8035 can
also appear at address 4 - making it a total of 3 phy nodes in the DTB.
To avoid confusing Linux with probe errors, fixup the dtb to only enable
the phy
Since SoMs revision 1.9 the ar8038 phy has been replaced by adin1300.
Enable the driver so that the new SoMs have functional networking.
Signed-off-by: Josua Mayer
---
configs/mx6cuboxi_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/mx6cuboxi_defconfig
The Cubox has an unstable phy address - which can appear at either
address 0 (intended) or 4 (unintended).
SoM revision 1.9 has replaced the ar8035 phy with an adin1300, which
will always appear at address 1.
Change the reg property of the phy node to the magic value 0x,
which indicates
The ADIN1300 supports generating certain clocks on its GP_CLK pin, as
well as providing the reference clock on CLK25_REF.
Add support for selecting the clock via device-tree properties.
This patch is based on just submitted patches to Linux [1] [2].
[1]
The adin_get_phy_mode_override function does not compile, because it is
missing both declaration and implementation of
phy_get_interface_by_name.
Remove the whole function for now, since the missing implementation is
not included in mainline Linux - and thus can not be copied.
Signed-off-by:
As of Revision 1.9 the SolidRun i.MX6 SoMs ship with a new PHY - an
ADIN1300 at address 1. This patchset carries many small parts to
facilitate proper operation of the ethernet port in U-Boot as well as
Linux:
1. Fix a compile error in the recently phy driver
2. Add support for configuring the
Do board reset via CPLD's system reset register.
Signed-off-by: Pali Rohár
---
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index
CPLD's system reset register on P1/P2 RDB boards is not autocleared after
flipping it. If this register is set to one then CPLD triggers reset of CPU
in few ms.
This means that trying to reset board via CPLD system reset register cause
reboot loop. To prevent this reboot loop, the only workaround
If watchdog timer was already set to non-disabled value then it means that
watchdog timer was already activated, has already expired and caused CPU
reset. If this happened then due to CPLD firmware bug, writing to wd_cfg
register has no effect and therefore it is not possible to reactivate
TDM function is supported only on P1010. P2020 does not have PMUXCR_TDM_ENA
register, so do not enable it.
Signed-off-by: Pali Rohár
---
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
> Date: Sun, 1 May 2022 01:59:21 +0100
> From: Andre Przywara
Hi Andre,
> On Fri, 29 Apr 2022 21:38:58 -0500
> Samuel Holland wrote:
>
> Hi Samuel,
>
> > On 4/29/22 7:08 PM, Andre Przywara wrote:
> > > On Fri, 29 Apr 2022 14:14:19 -0400
> > > Tom Rini wrote:
> > >
> > > Hi,
> > >
> > >>
On 2022/5/1 0:14, Adam Ford wrote:
Certain platforms have the UART clocks exposed through the CCF.
When they are, it's possible to enable and query the clock(s)
for a given UART. Add support getting, enabling, and querying
the clocks.
Signed-off-by: Adam Ford
diff --git
On 2022/4/30 21:49, Adam Ford wrote:
On Fri, Apr 29, 2022 at 2:20 AM Peng Fan (OSS) wrote:
From: Peng Fan
Since the power domain driver default select CONFIG_CLK, so we will
meet lots failures without CLK_IMX8MQ, so default select it.
There is a related patch [1] that I submitted for
If memory allocation fails, write an error message.
Signed-off-by: Heinrich Schuchardt
---
lib/efi_selftest/efi_selftest_tcg2.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/lib/efi_selftest/efi_selftest_tcg2.c
b/lib/efi_selftest/efi_selftest_tcg2.c
index
* fix typo %s/give/given/
* don't use void * in pointer arithmetic
Signed-off-by: Heinrich Schuchardt
---
lib/efi_selftest/efi_selftest_unaligned.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/lib/efi_selftest/efi_selftest_unaligned.c
The unit test has not been built since CPU_V7 was rename CPU_V7A.
Fixes: acf1500138bb ("arm: v7: Kconfig: Rename CPU_V7 as CPU_V7A")
Signed-off-by: Heinrich Schuchardt
---
lib/efi_selftest/Makefile | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/lib/efi_selftest/Makefile
Dear Han and Fabio
On Thu, Apr 28, 2022 at 7:01 AM Michael Nazzareno Trimarchi
wrote:
>
> Hi
>
> On Thu, Apr 28, 2022 at 2:27 AM Han Xu wrote:
> >
> >
> >
> > > -Original Message-
> > > From: Michael Trimarchi
> > > Sent: Wednesday, April 27, 2022 12:50 AM
> > > To: Han Xu ;
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