On 11/01/2024 08:09, Michal Simek wrote:
>
>
> On 1/10/24 22:27, Krzysztof Kozlowski wrote:
>> On 10/01/2024 14:35, Michal Simek wrote:
>>> Move cells to board dtsi files from generic zynqmp.dtsi. Changes are
>>> related to qspi, spi, nand, i2c and ethernet nodes.
>>>
>>> All errors are
Hi Heinrich,
heinrich.schucha...@canonical.com wrote on Thu, 11 Jan 2024 08:31:55
+0100:
> mtd dump beyond 4 GiB will show incorrect results.
>
> Multiplying two u32 will yield a u32. Add a missing cast.
Good point, thanks for the fix.
Reviewed-by: Miquel Raynal
Thanks,
Miquèl
First of all I think this should be more RFC.
On 1/11/24 08:10, Venkatesh Yadav Abbarapu wrote:
Usb5744 & usb2244 are Microchip based usbhub and usb-2.0 based SD
controller devices. Integrate these devices into dwc3 driver to bind and
probe the respective drivers to get detected by usb
mtd dump beyond 4 GiB will show incorrect results.
Multiplying two u32 will yield a u32. Add a missing cast.
Fixes: 5db66b3aee6f ("cmd: mtd: add 'mtd' command")
Addresses-Coverity-ID: 477205 ("Unintentional integer overflow")
Signed-off-by: Heinrich Schuchardt
---
cmd/mtd.c | 4 ++--
1 file
On Thu, 11 Jan 2024 at 08:34, Heinrich Schuchardt
wrote:
>
> A SMBIOS 3 entry point has a different length than an SMBIOS 2.1 entry
> point.
>
> Fixes: 70924294f375 ("smbios: Use SMBIOS 3.0 to support an address above 4GB")
> Fixes: 1c5f6fa3883d ("smbios: Drop support for SMBIOS2 tables")
>
Usb5744 & usb2244 are Microchip based usbhub and usb-2.0 based SD
controller devices. Integrate these devices into dwc3 driver to bind and
probe the respective drivers to get detected by usb controller.
Signed-off-by: T Karthik Reddy
Signed-off-by: Venkatesh Yadav Abbarapu
---
On 1/10/24 22:27, Krzysztof Kozlowski wrote:
On 10/01/2024 14:35, Michal Simek wrote:
Move cells to board dtsi files from generic zynqmp.dtsi. Changes are
related to qspi, spi, nand, i2c and ethernet nodes.
All errors are generated when dtbs are compiled with W=1.
I don't see any errors
A SMBIOS 3 entry point has a different length than an SMBIOS 2.1 entry
point.
Fixes: 70924294f375 ("smbios: Use SMBIOS 3.0 to support an address above 4GB")
Fixes: 1c5f6fa3883d ("smbios: Drop support for SMBIOS2 tables")
Addresses-Coverity-ID: 477212 ("Wrong sizeof argument")
Signed-off-by:
Add a test for reset commands which performs resetting of CPU, It does
COLD reset by default and WARM reset with -w option.
Signed-off-by: Love Kumar
---
test/py/tests/test_reset.py | 50 +
1 file changed, 50 insertions(+)
create mode 100644
This commit stores the firmware version into the array
of fmp_state structure to support the fmp versioning
for multi bank update. The index of the array is identified
by the bank index.
This modification keeps the backward compatibility with
the existing versioning feature.
Signed-off-by:
The capsule update uses the DFU framework for updating
storage. fwu_get_image_index() currently returns the
image_index calculated by (dfu_alt_num + 1), but this is
different from the image_index in UEFI terminology.
Since capsule update implementation calls dfu_write_by_alt
function, it is
The current FMP versioning does not work when CONFIG_FWU_MULTI_BANK_UPDATE
is enabled. This series aims to support FMP versioning
for FWU multi bank update.
[Changelog]
v2 -> v3
- add comment of ignoring GetVariable error when set FmpState variable
v1 -> v2
- update fwu_get_image_index()
Hi.
2024년 1월 10일 (수) 02:49, Tom Rini 님이 작성:
> On Tue, Jan 09, 2024 at 10:55:16AM +0900, Minkyu Kang wrote:
>
> > Dear Tom,
> >
> > The following changes since commit
> 2f0282922b2c458eea7f85c500a948a587437b63:
> >
> > Prepare v2024.01-rc4 (2023-12-04 13:46:56 -0500)
> >
> > are available in
Hi Ilias,
On Thu, 11 Jan 2024 at 10:53, Masahisa Kojima
wrote:
>
> On Wed, 10 Jan 2024 at 18:10, Ilias Apalodimas
> wrote:
> >
> > On Wed, 10 Jan 2024 at 02:53, Masahisa Kojima
> > wrote:
> > >
> > > On Tue, 9 Jan 2024 at 22:02, Ilias Apalodimas
> > > wrote:
> > > >
> > > > On Tue, 9 Jan 2024
I think there is no particular SW support needed for FIELD_RETURN on 8MN.
From what you described, you have moved the part from closed to FIELD_RETURN.
So are you
able to boot into SPL without signature?
Best regards,
Ye Li
> -Original Message-
> From: Peng Fan (OSS)
> Sent:
+Ye
在 1/9/2024 4:52 PM, Thomas Schaefer 写道:
Hi all,
We are trying to enable FIELD RETURN on the NXP i.MX8MNano LPD4 EVK board.
We enabled Secure Boot in u-boot in the first step. After checking proper
execution of a signed bootloader image we closed the board blowing the
SEC_CONFIG fuse.
Add support for WinLink E850-96 board [1]. It's based on Exynos850 SoC
and follows 96boards specification, so it's compatible with 96boards
mezzanine boards [2]. This patch enables next features:
* Serial console
* USI
* PMU (muxing AP UART path)
* Pinctrl
* Clocks
* Timer (ARMv8
Samsung Exynos850 is ARMv8-based mobile-oriented SoC. It features
Cortex-A55 CPU (8 cores) and it's built using 8nm process.
Add Exynos850 support by enabling next features:
* Import Exynos850 SoC dtsi files from Linux kernel
* Add Exynos850 MMU memory map
* Introduce ARCH_EXYNOS9 platform
Add next Samsung subsystems with Sam Protsenko as a maintainer:
- Samsung CCF Clock Framework
- Exynos850 SoC Support
- Samsung SoC Drivers
Signed-off-by: Sam Protsenko
---
Changes in v2:
- (none)
MAINTAINERS | 25 +
1 file changed, 25 insertions(+)
diff --git
Enable serial support for Exynos850 SoC by adding the corresponding
compatible string. No additional changes needed, the driver works as is
on Exynos850. Related USI and PMU configuration is enabled in separate
drivers. The only other dependencies are clock and pinctrl drivers,
which are already
Add pinctrl support for Exynos850 SoC. It was mostly extracted from
corresponding Linux kernel code [1]. Power down modes and external
interrupt data were removed while converting the code for U-Boot, but
everything else was kept almost unchanged.
[1]
Heavily influenced by its Linux kernel counterpart. It's implemented on
top of recently added Samsung CCF clock framework API. For now only UART
leaf clocks are implemented, along with all preceding clocks in CMU_TOP
and CMU_PERI. The UART baud clock is required in the serial driver, to
get its
PLL utilities code is only used by clk-exynos7420 driver at the moment.
Move it into clk-exynos7420 to make clk-pll.c file available for CCF PLL
clocks implementation, which is coming in the next patches.
Signed-off-by: Sam Protsenko
Reviewed-by: Chanho Park
---
Changes in v2:
- Added R-b tag
Heavily based on Linux kernel Samsung clock framework, with some changes
to accommodate the differences in U-Boot CCF implementation. It's also
quite minimal as compared to the Linux version.
Signed-off-by: Sam Protsenko
Reviewed-by: Chanho Park
---
Changes in v2:
- Corrected Thomas Abraham's
Add basic Power Management Unit (PMU) driver for Exynos SoCs. For now
it's only capable of changing UART path in PMU, which is needed for
E850-96 board. The driver's structure resembles the exynos-pmu driver
from Linux kernel, and although it's very basic and slim at the moment,
it can be easily
USIv2 IP-core is found on modern ARM64 Exynos SoCs (like Exynos850) and
provides selectable serial protocol (one of: UART, SPI, I2C). USIv2
registers usually reside in the same register map as a particular
underlying protocol it implements, but have some particular offset. E.g.
on Exynos850 the
Add bindings documentation and the header file for Exynos850 clock
controller. It was taken from Linux kernel [1,2].
[1] Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
[2] include/dt-bindings/clock/exynos850.h
Signed-off-by: Sam Protsenko
---
Changes in v2:
- (none)
Add USI bindings documentation and header file. Those are taken from
Linux kernel [1,2], but the documentation was reworked a bit to only
describe the compatibles that will be supported in U-Boot soon.
[1] Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml
[2]
Add bindings documentation for Exynos PMU hardware block. It was taken
from Linux kernel [1], but minimized and modified to reflect features
that will be actually supported in U-Boot soon. For example,
the "samsung,uart-debug-1" property is not available in Linux kernel
bindings and only present
Hi Heinrich,
On Wed, 10 Jan 2024 at 22:53, Heinrich Schuchardt wrote:
>
> On 26.12.23 07:28, Masahisa Kojima wrote:
> > Current efibootmgr auto-generates the boot option for all
> > disks and partitions installing EFI_SIMPLE_FILE_SYSTEM_PROTOCOL,
> > while EDK II reference implementation
Add Exynos850 SoC and WinLink's E850-96 board support. A short overview
of series additions and modifications:
* USI driver: configures UART block
* PMU driver: connects AP UART lines to uart1 pins)
* Exynos850 clock driver: generates UART clocks
* Exynos850 pinctrl driver: mux UART pins
Currently when using "W=1" with xilinx_zynqmp_r5_defconfig, getting
below warnings.
cc1.real: warning: ./arch/arm/mach-zynqmp-r5/include:
No such file or directory [-Wmissing-include-dirs]
Fix W=1 missing-include-dirs warnings by including the headers and
sys_r5_proto.h file which
On Tue, Dec 19, 2023 at 5:38 AM Chanho Park wrote:
>
[snip]
> > diff --git a/drivers/clk/exynos/clk-pll.c b/drivers/clk/exynos/clk-pll.c
> > new file mode 100644
> > index ..9e496ff83aaf
> > --- /dev/null
> > +++ b/drivers/clk/exynos/clk-pll.c
> > @@ -0,0 +1,167 @@
> > +//
On Wed, Dec 27, 2023 at 11:49 AM Simon Glass wrote:
>
> Hi Sam,
>
[snip]
>
> Just a few nits here
>
> Reviewed-by: Simon Glass
>
[snip]
> > +
> > +struct exynos_usi {
> > + struct udevice *dev;
>
> Can we drop this? It doesn't seem very useful and we try to avoid
> having bidirectional
On Wed, 10 Jan 2024 at 18:10, Ilias Apalodimas
wrote:
>
> On Wed, 10 Jan 2024 at 02:53, Masahisa Kojima
> wrote:
> >
> > On Tue, 9 Jan 2024 at 22:02, Ilias Apalodimas
> > wrote:
> > >
> > > On Tue, 9 Jan 2024 at 03:00, Masahisa Kojima
> > > wrote:
> > > >
> > > > Hi Ilias,
> > > >
> > > > On
On Wed, Dec 27, 2023 at 3:11 AM Minkyu Kang wrote:
>
> Hi
>
>
> 2023년 12월 13일 (수) 12:42, Sam Protsenko 님이 작성:
>>
[snip]
>> +
>> +/**
>> + * exynos_usi_set_sw_conf - Set USI block configuration mode
>> + * @usi: USI driver object
>> + * @mode: Mode index
>> + *
>> + * Select underlying serial
On Wed, Dec 27, 2023 at 3:12 AM Minkyu Kang wrote:
>
> Hi,
>
>
> 2023년 12월 13일 (수) 12:27, Sam Protsenko 님이 작성:
>>
>> Heavily based on Linux kernel Samsung clock framework, with some changes
>> to accommodate the differences in U-Boot CCF implementation. It's also
>> quite minimal as compared to
On Tue, Dec 19, 2023 at 5:32 AM Chanho Park wrote:
>
> > -Original Message-
> > From: U-Boot On Behalf Of Sam Protsenko
> > Sent: Wednesday, December 13, 2023 12:17 PM
> > To: Minkyu Kang ; Tom Rini ;
> > Lukasz Majewski ; Sean Anderson
> > Cc: Simon Glass ; Heinrich Schuchardt
> > ;
On 10/01/2024 14:35, Michal Simek wrote:
> Move cells to board dtsi files from generic zynqmp.dtsi. Changes are
> related to qspi, spi, nand, i2c and ethernet nodes.
>
> All errors are generated when dtbs are compiled with W=1.
>
I don't see any errors on some other platforms, like Samsung.
QEMU RISC-V supports multiple virtio devices, but only tries to boot to
the first one. Enable support for a second virtio device, that is useful
for instance to boot on a disk image + an installer. Ideally that should
be made dynamic, but that's a first step.
Signed-off-by: Aurelien Jarno
---
The difference between the StarFive VisionFive 2 1.2A and 1.3B boards is
handled dynamically by looking at the PCB version in the EEPROM in order
to have a single u-boot version for both versions of the board. While
the "model" property is correctly handled, the "compatible" one is
always the the
On 10/01/2024 18:08, Dragan Simic wrote:
> On 2024-01-09 12:51, Caleb Connolly wrote:
>> With the relatively new button API in U-Boot, it's now much easier to
>> model the common usecase of mapping arbitrary actions to different
>> buttons during boot - for example entering fastboot mode,
On 10/01/2024 16:41, Sean Anderson wrote:
On 1/10/24 04:23, Neil Armstrong wrote:
Hi Sean,
On 18/12/2023 10:47, Neil Armstrong via groups.io wrote:
Amlogic SoCs embeds an hardware clock measure block, port it
from Linux and implement it as a UCLK_CLK with only the dump
op and fail-only xlate.
The help for CONFIG_MTD explains that it needs to be enabled for various
things like NAND, etc to be available. It however then doesn't enforce
this dependency and so if you have none of these systems present you
still need to disable a number of options. Fix this by making places
that
This command is only useful on CFI and NOR type flashes and not others.
Update the dependency so that it's not enabled by default in other
cases. This will lead to a number of platforms no longer building this
command, where it was not useful.
Signed-off-by: Tom Rini
---
cmd/Kconfig | 2 +-
1
In order for our environment to be present on SPI flash we need to
depend not on the symbol for a SPI controller but rather that SPI flash
of some sort is present. Update the dependencies.
Signed-off-by: Tom Rini
---
env/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Rather than rely on someone selecting or implying this hidden symbol
that the command requires, select it explicitly.
Signed-off-by: Tom Rini
---
board/microchip/mpfs_icicle/Kconfig | 1 -
cmd/Kconfig | 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git
This specific bit logic is used to determine what NAND chip is present
on a board in order to then know what revision of the board we have and
so what DDR chips are present. We can only do this if we have a NAND
chip, and so we will have NAND_OMAP_GPMC enabled.
Signed-off-by: Tom Rini
---
On 19:31-20240110, Roger Quadros wrote:
>
>
[..]
> FYI. findfdt is still used in:
>
> am335x_baltos_defconfig:CONFIG_BOOTCOMMAND="run findfdt; run usbboot;run
> mmcboot;setenv mmcdev 1; setenv bootpart 1:2; run mmcboot;run nandboot;"
> am335x_boneblack_vboot_de
On 2024-01-09 12:51, Caleb Connolly wrote:
With the relatively new button API in U-Boot, it's now much easier to
model the common usecase of mapping arbitrary actions to different
buttons during boot - for example entering fastboot mode, setting some
additional kernel cmdline arguments, or
On 1/10/24 04:29, Ivan T. Ivanov wrote:
From: Dmitry Malkin
MBOX and Watchdog on RPi5/bcm2712 has a different base IO offsets.
s/has a/have a /
Find them via devicetree blob passed by bootloader.
Signed-off-by: Dmitry Malkin
Reviewed-by: Matthias Brugger
Signed-off-by: Ivan T. Ivanov
On 1/10/24 04:29, Ivan T. Ivanov wrote:
From: Dmitry Malkin
This includes:
* 1GB of RAM (from 4GB or 8GB total)
* AXI ranges (main peripherals)
When HDMI cable is plugged in at boot time firmware will
insert "simple-framebuffer" device into devicetree and will
shrink first memory region to
On 09/01/2024 21:15, Nishanth Menon wrote:
> We shouldn't need finfdt anymore. Drop the env script.
>
> Signed-off-by: Nishanth Menon
> ---
> Changes from V1: None.
>
> V1: https://lore.kernel.org/r/20240108173301.2692332-11...@ti.com
> include/env/ti/default_findfdt.env | 12
>
On Wed, Jan 10, 2024 at 06:06:45PM +0200, Roger Quadros wrote:
> +Lukasz & Mattijs
>
> On 10/01/2024 11:34, Roger Quadros wrote:
> >
> >
> > On 09/01/2024 22:00, Francesco Dolcini wrote:
> >> On Tue, Jan 09, 2024 at 02:54:00PM -0500, Tom Rini wrote:
> >>> On Tue, Jan 09, 2024 at 01:18:59PM
Existing gpio-gate-clock driver acts like a simple GPIO switch without any
effect on gated clock. Add actual clock actions into enable/disable ops and
implement get_rate op by passing gated clock if it is enabled.
Signed-off-by: Svyatoslav Ryhel
---
drivers/clk/clk-gpio.c | 40
Existing gpio-gate-clock driver acts like a simple GPIO switch without any
effect on gated clock. Add actual clock actions into enable/disable ops and
implement get_rate op by passing gated clock if it is enabled.
Testing current driver implementation shows that it is not fully capable
and lacks
+Lukasz & Mattijs
On 10/01/2024 11:34, Roger Quadros wrote:
>
>
> On 09/01/2024 22:00, Francesco Dolcini wrote:
>> On Tue, Jan 09, 2024 at 02:54:00PM -0500, Tom Rini wrote:
>>> On Tue, Jan 09, 2024 at 01:18:59PM -0600, Nishanth Menon wrote:
On 14:26-20240109, Roger Quadros wrote:
>
On 1/10/24 10:53, Svyatoslav wrote:
10 січня 2024 р. 17:45:57 GMT+02:00, Sean Anderson
написав(-ла):
On 12/16/23 10:37, Sean Anderson wrote:
On 12/16/23 03:48, Svyatoslav Ryhel wrote:
Existing gpio-gate-clock driver acts like a simple GPIO switch without any
effect on gated clock. Add
10 січня 2024 р. 17:45:57 GMT+02:00, Sean Anderson
написав(-ла):
>On 12/16/23 10:37, Sean Anderson wrote:
>> On 12/16/23 03:48, Svyatoslav Ryhel wrote:
>>> Existing gpio-gate-clock driver acts like a simple GPIO switch without any
>>> effect on gated clock. Add actual clock actions into
On Wed, Jan 10, 2024 at 03:47:24PM +0100, Stefan Roese wrote:
> Hi Tom,
>
> please pull this next batch of Marvell related patches:
>
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
On 12/16/23 10:37, Sean Anderson wrote:
On 12/16/23 03:48, Svyatoslav Ryhel wrote:
Existing gpio-gate-clock driver acts like a simple GPIO switch without any
effect on gated clock. Add actual clock actions into enable/disable ops and
implement get_rate op by passing gated clock if it is
On 1/10/24 04:23, Neil Armstrong wrote:
Hi Sean,
On 18/12/2023 10:47, Neil Armstrong via groups.io wrote:
Amlogic SoCs embeds an hardware clock measure block, port it
from Linux and implement it as a UCLK_CLK with only the dump
op and fail-only xlate.
Based on the Linux driver introduced in
On 10/01/2024 13:29, Ivan T. Ivanov wrote:
brcm,bcm2708-fb device provided by firmware on RPi5 uses
16 bits per pixel, so lets calculate framebuffer bytes
per pixel dynamically based on queried information.
Tested to work for RPi2b v1.2, RPi3b v1.3, RPi4b v1.1,
RPi2 Zero W, RPi5b v1.0.
On Wed, Jan 10, 2024 at 03:48:47PM +0100, Lukasz Majewski wrote:
> As the XEA now supports fitImage, the default envs shall reflect this
> as well.
>
> Moreover, some SPI-NOR layout re-organization has took place.
>
> Signed-off-by: Lukasz Majewski
> ---
>
> include/configs/xea.h | 45
From: Anatolij Gustschin
We load two boot image source descriptor structures from last
two sectors in the SPI NOR flash and determine the boot source
for loading the kernel/DTB images, then adjust the boot order for
loading image from eMMC boot0 or boot1 partition.
Signed-off-by: Anatolij
The boot0/1 feature uses simple CRC8 to check (in SPL) if
SPI-NOR content is not corrupted, hence the need to enable
it.
Signed-off-by: Lukasz Majewski
---
configs/imx28_xea_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/imx28_xea_defconfig b/configs/imx28_xea_defconfig
As the XEA now supports fitImage, the default envs shall reflect this
as well.
Moreover, some SPI-NOR layout re-organization has took place.
Signed-off-by: Lukasz Majewski
---
include/configs/xea.h | 45 ---
1 file changed, 25 insertions(+), 20
Hi Tom,
please pull this next batch of Marvell related patches:
- AC5: Use finer grained memory map (Chris)
- Espressobin: Misc improvements (Robert)
- eDPU: Support new board revision (Robert)
On 11/29/23 11:11, Robert Marko wrote:
There is a new eDPU revision that uses Marvell 88E6361 switch onboard.
We can rely on detecting the switch to enable and fixup the Linux DTS
so a single DTS can be used.
There is currently no support for the 88E6361 switch and thus no working
networking in
On 11/29/23 11:11, Robert Marko wrote:
Currently, Esspresobin switch is being setup directly in last_stage_init()
which makes it hard to add support for any other board to be setup.
So, lets just move the switch setup code to a separate function and call it
if compatible matches, there should
I think this isn't needed anymore after
https://lore.kernel.org/u-boot/CAC_iWjJ6=NjqwcFzVvV4DzMWy5nY_QAeD=vfqrrsjodlbvq...@mail.gmail.com/
On Wed, 3 Jan 2024 at 00:14, Raymond Mao wrote:
>
> Update the document and Kconfig to describe the behavior of board
> specific custom functions when
Hi Raymond
I think my r-b tag got lost across versions
On Wed, 3 Jan 2024 at 00:13, Raymond Mao wrote:
>
> Instead of expecting the bloblist total size to be the same as the
> pre-allocated buffer size, practically we are more interested in
> whether the pre-allocated buffer size is bigger than
On 11/29/23 11:11, Robert Marko wrote:
Currently, Esspresobin FDT is being fixed up directly in ft_board_setup()
which makes it hard to add support for any other board to be fixed up.
So, lets just move the FDT fixup code to a separate function and call it
if compatible matches, there should be
On 10/27/23 02:44, Chris Packham wrote:
The ATF implementation for AC5/AC5X ends up with bl31 living in some
internal SRAM. This is in the middle of the large MMIO region that we
were using. Adjust this to be finer grained blocks based on the address
map from the AC5X Family Control and
On 26.12.23 07:28, Masahisa Kojima wrote:
Current efibootmgr auto-generates the boot option for all
disks and partitions installing EFI_SIMPLE_FILE_SYSTEM_PROTOCOL,
while EDK II reference implementation auto-generates the boot option
for all devices installing EFI_BLOCK_IO_PROTOCOL with
Move cells to board dtsi files from generic zynqmp.dtsi. Changes are
related to qspi, spi, nand, i2c and ethernet nodes.
All errors are generated when dtbs are compiled with W=1.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-a2197-revA.dts | 4
Add brief documentation on how to build a bootable U-Boot image for the
phyGATE-Tauri-L.
Signed-off-by: Yannic Moog
---
board/phytec/phycore_imx8mm/MAINTAINERS | 2 +
doc/board/phytec/imx8mm-phygate-tauri-l.rst | 60 +
doc/board/phytec/index.rst
Add rst documentation files to the respective MAINTAINERS file for
PHYTEC boards.
Signed-off-by: Yannic Moog
---
board/phytec/phycore_imx8mm/MAINTAINERS | 1 +
board/phytec/phycore_imx8mp/MAINTAINERS | 1 +
2 files changed, 2 insertions(+)
diff --git a/board/phytec/phycore_imx8mm/MAINTAINERS
phyGATE-Tauri-L-iMX8MM is a Gateway based on the phycore-imx8mm SoM.
As a result, all the board code of the phycore-imx8mm is used.
Device tree synced with kernel v6.7.
Signed-off-by: Yannic Moog
---
arch/arm/dts/Makefile | 1 +
The config is minimal and mostly a copy from the phycore-imx8mm. SPI
(flash) is disabled as it is not populated by default.
Also add documentation for the phyGATE-Tauri-L board. While at it, add
the other PHYTEC doc files to MAINTAINERS; they were missing for
existing phycore-imx8m{m,p} doc.
---
On January 10, 2024 thus sayeth Bhavya Kapoor:
>
> On 08/01/24 7:35 pm, Bryan Brattlof wrote:
> > Hi Bhavya!
> >
> > On January 8, 2024 thus sayeth Bhavya Kapoor:
> > > This Series adds Itap Delay Value for DDR52 speed mode for eMMC in
> > > J7200 SoC and for DDR50 speed mode for MMCSD in
Sorry, my e-mail client is lagging and I sent two replies.
On Wed, Jan 10, 2024 at 08:03:39AM +, Alexey Romanov wrote:
> Hi,
>
> On Tue, Jan 09, 2024 at 10:45:46AM -0500, Sean Anderson wrote:
> > On 1/9/24 05:27, Alexey Romanov wrote:
> > > Hello Sean!
> > >
> > > Thanks for you reply.
> >
Hi,
On Tue, Jan 09, 2024 at 10:45:46AM -0500, Sean Anderson wrote:
> On 1/9/24 05:27, Alexey Romanov wrote:
> > Hello Sean!
> >
> > Thanks for you reply.
> >
> > On Thu, Dec 28, 2023 at 11:45:04AM -0500, Sean Anderson wrote:
> >> On 12/28/23 10:25, Alexey Romanov wrote:
> >> > Currently,
On 08/01/24 7:35 pm, Bryan Brattlof wrote:
Hi Bhavya!
On January 8, 2024 thus sayeth Bhavya Kapoor:
This Series adds Itap Delay Value for DDR52 speed mode for eMMC in
J7200 SoC and for DDR50 speed mode for MMCSD in J721s2 SoC.
Bhavya Kapoor (2):
arm: dts: k3-j7200-main: Add Itap Delay
Add brief documentation on how to build a bootable U-Boot image for the
phyGATE-Tauri-L.
Signed-off-by: Yannic Moog
---
doc/board/phytec/imx8mm-phygate-tauri-l.rst | 60 +
doc/board/phytec/index.rst | 1 +
2 files changed, 61 insertions(+)
diff
phyGATE-Tauri-L-iMX8MM is a Gateway based on the phycore-imx8mm SoM.
As a result, all the board code of the phycore-imx8mm is used.
Device tree synced with kernel v6.7.
Signed-off-by: Yannic Moog
---
arch/arm/dts/Makefile | 1 +
The config is minimal and mostly a copy from the phycore-imx8mm. TI PHY
and SPI (flash) are disabled as they are not populated by default.
---
Yannic Moog (2):
Add support for phyGATE-Tauri-L-iMX8MM
doc: board: phytec: Add phyGATE-Tauri board documentation
arch/arm/dts/Makefile
On Wed, 10 Jan 2024 at 18:01, Fabio Estevam wrote:
>
> On Wed, Jan 10, 2024 at 7:37 AM Sumit Garg wrote:
>
> > History
> > ---
> >
> > -U-Boot configuration was previous done using CONFIG options in the board
> > +U-Boot configuration was previous done using Kconfig options in the board
>
Borrow SD quirks from vendor Linux driver.
"BCM2712 unfortunately carries with it a perennial bug with the SD
controller register interface present on previous chips (2711/2709/2708).
Accesses must be dword-sized and a read-modify-write cycle to the 32-bit
registers containing the COMMAND,
Remove already disabled node. GPIO connections are handled by pmufw that's
why there is no reason to have it described for non secure firmware.
If someone wants to handle it from OS revert this patch and also update
PMUFW configuration and pinctrl setting for these GPIO pins.
Signed-off-by:
On Wed, Jan 10, 2024 at 7:37 AM Sumit Garg wrote:
> History
> ---
>
> -U-Boot configuration was previous done using CONFIG options in the board
> +U-Boot configuration was previous done using Kconfig options in the board
> config file. This eventually got out of hand with nearly 10,000
brcm,bcm2708-fb device provided by firmware on RPi5 uses
16 bits per pixel, so lets calculate framebuffer bytes
per pixel dynamically based on queried information.
Tested to work for RPi2b v1.2, RPi3b v1.3, RPi4b v1.1,
RPi2 Zero W, RPi5b v1.0.
Signed-off-by: Ivan T. Ivanov
---
RPi5 have "brcm,bcm2712-sdhci" controller which is
handled by "sdhci-bcmstb" driver, so enable it.
Signed-off-by: Ivan T. Ivanov
---
configs/rpi_arm64_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig
index
Firmware on RPi5 return error on board revision query
through firmware interface, but on the other hand it fills
"linux,revision" in "system" node, so use it to detect board
revision.
system {
linux,revision = <0xc04170>;
linux,serial = <0x6cf44e80
From: Dmitry Malkin
MBOX and Watchdog on RPi5/bcm2712 has a different base IO offsets.
Find them via devicetree blob passed by bootloader.
Signed-off-by: Dmitry Malkin
Reviewed-by: Matthias Brugger
Signed-off-by: Ivan T. Ivanov
---
arch/arm/mach-bcm283x/include/mach/base.h | 5 ++-
From: Dmitry Malkin
This includes:
* 1GB of RAM (from 4GB or 8GB total)
* AXI ranges (main peripherals)
When HDMI cable is plugged in at boot time firmware will
insert "simple-framebuffer" device into devicetree and will
shrink first memory region to 0x3f80UL. Board setup then
will properly
Hi,
These patches are slight update for patches posted earlier here[1].
They are adding basic support for RPi5 and are based on v2 series
from Dmitry Malkin[2].
What changed:
* Initial memory map now includes whole first 1GB of DRAM. At runtime,
the firmware will adjust this size depending on
Hi Paul,
On Fri, Jan 5, 2024 at 4:19 PM Fabio Estevam wrote:
> > I tried to investigate this by U-boot sandbox. But it seems to me that I
> > cannot reproduce this issue.
> > I put a file on localhost apache server and tried to download it from
> > localhost.
> > I might need a more
Hi Kever,
On Tue, Jan 9, 2024 at 10:55 AM Kever Yang wrote:
>
> Hi Shantur, Tom,
>
> On 2023/12/10 04:45, Tom Rini wrote:
> > On Sat, Dec 09, 2023 at 07:49:04PM +, Shantur Rathore wrote:
> >> On Sat, Dec 9, 2023 at 7:18 PM Tom Rini wrote:
> >>> On Fri, Dec 08, 2023 at 10:52:02AM +,
On 10/01/2024 11:02, MD Danish Anwar wrote:
>
>
> On 10/01/24 2:24 pm, Roger Quadros wrote:
>> On 10/01/2024 08:50, MD Danish Anwar wrote:
>>> Hi Roger,
>>>
>>> On 27/12/23 3:49 pm, MD Danish Anwar wrote:
On 20/12/23 4:10 pm, Roger Quadros wrote:
>
>
> On 19/12/2023 12:34, MD
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