Hi,
> >> arch/arm/cpu/armv7/lowlevel_init.S:.pushsection .text.s_init, "ax"
> >> arch/arm/cpu/armv7/lowlevel_init.S:WEAK(s_init)
> >> arch/arm/cpu/armv7/lowlevel_init.S:ENDPROC(s_init)
> >> arch/arm/cpu/armv7/lowlevel_init.S: bl s_init
> >>
> >> Maybe such a default lowlevel_init for armv
Hi,
> -Original Message-
> From: Marek Vasut
> Sent: Wednesday, September 25, 2024 8:51 PM
> To: Chee, Tien Fong ; u-boot@lists.denx.de
> Cc: Simon Goldschmidt ; Meng, Tingting
> ; Yuslaimi, Alif Zakuan
> ; Hea, Kok Kiang
>
> Subject: Re: [PATCH v1 08/20] arm: dts: agilex5: Enable XGMAC
Document the procedure to enable Ethernet Boot on AM62x SoC.
Signed-off-by: Chintan Vankar
---
This patch is based on commit '4386ab9118e7' of origin/next branch of
U-Boot.
doc/board/ti/am62x_sk.rst | 196 ++
1 file changed, 196 insertions(+)
diff --git a/
Add support for parallel memories in zynq_qspi.c driver. In case of
parallel memories STRIPE bit is set and sent to the qspi ip, which will
send data bits to both the flashes in parallel. However for few commands
we should not use stripe, instead send same data to both the flashes.
Those commands a
Enable the SPI_ADVANCE config option for all xilinx platforms, as
this is required for parallel-memories.
Signed-off-by: Venkatesh Yadav Abbarapu
---
configs/xilinx_versal_net_virt_defconfig | 5 +++--
configs/xilinx_versal_virt_defconfig | 5 +++--
configs/xilinx_zynq_virt_defconfig
Add support for parallel memories in zynqmp_gqspi.c driver. In case of
parallel memories STRIPE bit is set and sent to the qspi ip, which will
send data bits to both the flashes in parallel. However for few commands
we should not use stripe, instead send same data to both the flashes.
Those command
Read chipselect properties from DT which are populated using 'reg'
property and save it in plat->cs[] array for later use.
Also read multi chipselect capability which is used for
parallel-memories and return errors if they are passed on using DT but
driver is not capable of handling it.
Signed-of
From: Ashok Reddy Soma
Add support for parallel memories flash configuration in read status
register and read flag status register functions.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Venkatesh Yadav Abbarapu
---
drivers/mtd/spi/spi-nor-core.c | 50 --
1 f
This series adds support for Xilinx qspi parallel and
stacked memeories.
In parallel mode, the current implementation assumes that a maximum
of two flashes are connected. The QSPI controller splits the data
evenly between both the flashes so, both the flashes that are connected
in parallel mode sh
From: Ashok Reddy Soma
Add support for parallel memories and stacked memories configuration
in read_bar and write_bar functions.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Venkatesh Yadav Abbarapu
---
drivers/mtd/spi/spi-nor-core.c | 55 +-
1 file changed,
In parallel mode, the current implementation assumes that a maximum of
two flashes are connected. The QSPI controller splits the data evenly
between both the flashes so, both the flashes that are connected in
parallel mode should be identical.
During each operation SPI-NOR sets 0th bit for CS0 & 1s
By default flash lock option is enabled, enable this option only
when it is required. By disabling the lock config will save some
amount of memory.
Signed-off-by: Venkatesh Yadav Abbarapu
---
configs/mx6sabresd_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/mx6sabresd_defc
On Wed, Sep 25, 2024 at 02:55:37PM +0200, Simon Glass wrote:
> Use spl_get_image_pos() to obtain the image position to jump to. Add
> the symbols used for VPL so that the correct image can be loaded.
>
> Use the functions provided for accessing these symbols and add a few
> comments too.
>
> Sign
On Wed, Sep 25, 2024 at 02:55:32PM +0200, Simon Glass wrote:
> Mark the lz4 decompression code as needed by relocation. This is used to
> decompress the next-phase image.
>
> Drop the 'safe' versions from SPL as they are not needed. Change the
> static array to a local one, to avoid link errors w
On Wed, Sep 25, 2024 at 02:55:30PM +0200, Simon Glass wrote:
> Add a linker symbol which can be used to mark relocation code, so it can
> be collected by the linker and copied into a suitable place and executed
> when needed.
>
> Signed-off-by: Simon Glass
> ---
>
> include/asm-generic/section
On Wed, Sep 25, 2024 at 02:55:27PM +0200, Simon Glass wrote:
> This is a block length, so typicaly 512 bytes. Reduce the size to
> 16 bits to save space, before more fields are added in future work.
>
> Signed-off-by: Simon Glass
> ---
>
> include/spl.h | 2 +-
> 1 file changed, 1 insertion(+)
On Tue, Sep 24, 2024 at 12:24:16PM +0200, Quentin Schulz wrote:
> Hi Chris,
>
> On 9/23/24 7:36 PM, Chris Morgan wrote:
> > On Mon, Sep 23, 2024 at 01:21:01PM +0200, Quentin Schulz wrote:
> > > Hi Chris,
> > >
> > > On 9/19/24 4:00 PM, Chris Morgan wrote:
> > > > From: Chris Morgan
> > > >
> >
On Tue, Sep 24, 2024 at 11:19:49AM +0200, Quentin Schulz wrote:
> Hi Chris,
>
> On 9/23/24 7:38 PM, Chris Morgan wrote:
> > On Mon, Sep 23, 2024 at 01:24:34PM +0200, Quentin Schulz wrote:
> > > Hi Chris,
> > >
> > > On 9/19/24 4:00 PM, Chris Morgan wrote:
> > > > From: Chris Morgan
> > > >
> >
First of all a huge thank you for the time you spend in reviewing the
patches so far. This is highly appreciate!!
On Fri, Sep 13, 2024 at 1:11 AM Marek Vasut wrote:
[...]
> Is there any chance to upstream these DTs to Linux first , and then let
> them all trickle into U-Boot through dts/upstream
Linux DTS compatible MDIO bitbanging driver.
Both clause 22 and clause 45 MDIO supported and validated.
Heavily based on the Linux drivers (more or less the same code base).
Signed-off-by: Markus Gothe
---
drivers/net/Kconfig | 6 +
drivers/net/Makefile | 1 +
drivers/net/mdio_gpi
On 9/25/24 3:04 PM, Svyatoslav Ryhel wrote:
ср, 25 вер. 2024 р. о 15:48 Marek Vasut пише:
On 9/25/24 12:18 PM, Svyatoslav Ryhel wrote:
[...]
Hello there!
I was digging this when I had some free time and found that with
patches from Marek the only difference is that function
i2c_get_chip_for
On 2024-09-25 12:18, Svyatoslav Ryhel wrote:
> Hello there!
> I was digging this when I had some free time and found that with
> patches from Marek the only difference is that function
> i2c_get_chip_for_busnum is not called for PMIC's main i2c address
> which results in issues with i2c you have se
ср, 25 вер. 2024 р. о 15:48 Marek Vasut пише:
>
> On 9/25/24 12:18 PM, Svyatoslav Ryhel wrote:
>
> [...]
>
> > Hello there!
> > I was digging this when I had some free time and found that with
> > patches from Marek the only difference is that function
> > i2c_get_chip_for_busnum is not called for
This series includes a way to deal with multiple XPL phases being
built to run from the same region of SRAM. This is useful because it may
not be possible to fit all the different phases in different parts of
the SRAM. Also it is a pain to have to build them with different values
for CONFIG_TEXT_
On 9/26/24 12:49 AM, Lothar Rubusch wrote:
Hi,
First of all a huge thank you for the time you spend in reviewing the
patches so far. This is highly appreciate!!
On Fri, Sep 13, 2024 at 1:11 AM Marek Vasut wrote:
[...]
Is there any chance to upstream these DTs to Linux first , and then let
t
On Wed, 25 Sep 2024 00:08:23 +0200, Marek Vasut wrote:
> U-Boot is currently unable to automatically enable regulators which
> contain DT property regulator-always-on or regulator-boot-on. There
> is an ongoing work to add this functionality to regulator core code,
> but until the proper solution
Hi,
On 6/19/24 08:35, Patrice CHOTARD wrote:
On 6/19/24 00:57, Marek Vasut wrote:
Update the TAMP_SMCR BKP..PROT fields to put first 10 registers
into protection zone 1 and next 5 into zone 2. This fixes use of
boot counter which is often in zone 3 and has to be updated from
Linux, which runs
On 9/25/24 19:37, Patrick DELAUNAY wrote:
Hi Marek,
On 7/8/24 13:43, Marek Vasut wrote:
Do not apply bitwise AND to register value and expected value, only
apply bitwise AND to register value and mask, and only then compare
the result with expected value that the function polls for.
Fixes: b
On 9/25/24 7:50 PM, Patrick DELAUNAY wrote:
Hi Marek,
Hi,
diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c b/arch/arm/
mach-stm32mp/stm32mp1/stm32mp15x.c
index f096fe538d8..ca202bec8ee 100644
--- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c
+++ b/arch/arm/mach-stm32mp/stm32mp1/stm32
Hi Marek,
On 9/25/24 19:04, Marek Vasut wrote:
On 6/19/24 8:35 AM, Patrice CHOTARD wrote:
On 6/19/24 00:57, Marek Vasut wrote:
Update the TAMP_SMCR BKP..PROT fields to put first 10 registers
into protection zone 1 and next 5 into zone 2. This fixes use of
boot counter which is often in zone
On Wed, Sep 25, 2024 at 02:50:45PM +0200, Simon Glass wrote:
> Hi Heinrich,
>
> On Sun, 22 Sept 2024 at 11:02, Heinrich Schuchardt wrote:
> >
> > On 9/19/24 17:14, Simon Glass wrote:
> > > Move this section of the README into doc/ with some minor updates to
> > > mention SPL and user lower-case h
On Wed, Sep 25, 2024 at 02:50:08PM +0200, Simon Glass wrote:
> Hi Tom,
>
> On Mon, 23 Sept 2024 at 22:36, Tom Rini wrote:
> >
> > On Fri, Sep 20, 2024 at 08:01:35AM +0200, Simon Glass wrote:
> >
> > > Labgrid provides access to a hardware lab in an automated way. It is
> > > possible to boot U-Bo
Hi Marek,
On 7/8/24 13:43, Marek Vasut wrote:
Do not apply bitwise AND to register value and expected value, only
apply bitwise AND to register value and mask, and only then compare
the result with expected value that the function polls for.
Fixes: b49105320a5b ("stm32mp: psci: Implement PSCI s
On Wed, 24 Jul 2024 22:47:10 +, Jonas Karlman wrote:
> On some boards a PMIC regulator is flagged with regulator-on-in-suspend
> and does not define any suspend or max microvolt, e.g. on Radxa ROCK 3A:
>
> vcc_ddr: DCDC_REG3 {
> regulator-name = "vcc_ddr";
> regulator-always-on;
On Wed, Sep 25, 2024 at 11:47:40AM +0200, Simon Glass wrote:
> Add this new board, to support testing the relocating SPL loader.
>
> Signed-off-by: Simon Glass
> ---
>
> bin/travis-ci/conf.qemu_arm64_tpl_na | 29
> 1 file changed, 29 insertions(+)
> create mode 10
On Thu, Sep 19, 2024 at 04:13:01PM +0200, Simon Glass wrote:
> Hi Tom,
>
> On Wed, 18 Sept 2024 at 00:19, Tom Rini wrote:
> >
> > On Tue, Sep 17, 2024 at 05:52:09AM +0200, Simon Glass wrote:
> > > Hi Tom,
> > >
> > > On Mon, 16 Sept 2024 at 18:34, Tom Rini wrote:
> > > >
> > > > On Mon, Sep 16,
On Wed, Sep 25, 2024 at 02:52:04PM +0200, Simon Glass wrote:
> Hi Tom,
>
> On Fri, 20 Sept 2024 at 16:59, Tom Rini wrote:
> >
> > On Fri, Sep 20, 2024 at 09:25:29AM +0200, Simon Glass wrote:
> > > Hi Tom,
> > >
> > > On Thu, 19 Sept 2024 at 19:45, Tom Rini wrote:
> > > >
> > > > On Thu, Sep 19,
On Wed, Sep 25, 2024 at 02:49:56PM +0200, Simon Glass wrote:
> Hi Tom,
>
> On Mon, 23 Sept 2024 at 22:35, Tom Rini wrote:
> >
> > On Fri, Sep 20, 2024 at 08:01:36AM +0200, Simon Glass wrote:
> >
> >
> > > When Labgrid is used, it can get U-Boot ready for running tests. It
> > > prints a message w
source.denx.de/u-boot/custodians/u-boot-microblaze into next
> (2024-09-23 08:11:01 -0600)
>
> are available in the Git repository at:
>
> https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git
> tags/u-boot-imx-next-20240925
>
> for you to fetch changes up to 99abeaa64
On 9/11/24 1:05 PM, Marek Vasut wrote:
On 8/30/24 3:36 PM, Jagan Teki wrote:
On Sun, Aug 25, 2024 at 5:58 AM Marek Vasut wrote:
On 5/24/24 6:05 PM, Jagan Teki wrote:
On Mon, Mar 4, 2024 at 9:46 PM Marek Vasut wrote:
Some Winbond SPI NORs have special SR3 register which is
used among other
On 7/8/24 1:43 PM, Marek Vasut wrote:
Do not apply bitwise AND to register value and expected value, only
apply bitwise AND to register value and mask, and only then compare
the result with expected value that the function polls for.
Fixes: b49105320a5b ("stm32mp: psci: Implement PSCI system sus
On 6/19/24 8:35 AM, Patrice CHOTARD wrote:
On 6/19/24 00:57, Marek Vasut wrote:
Update the TAMP_SMCR BKP..PROT fields to put first 10 registers
into protection zone 1 and next 5 into zone 2. This fixes use of
boot counter which is often in zone 3 and has to be updated from
Linux, which runs in
On 9/25/24 3:49 PM, Fabio Estevam wrote:
Hi Marek,
On Tue, Sep 24, 2024 at 9:12 PM Marek Vasut wrote:
Add support for DH electronics i.MX8MP DHCOM SoM on DRC02 carrier board.
This system is populated with two ethernet ports, two CANs, RS485 and RS232,
USB, capacitive buttons and an OLED displ
Add support for DH electronics i.MX8MP DHCOM SoM on DRC02 carrier board.
This system is populated with two ethernet ports, two CANs, RS485 and RS232,
USB, capacitive buttons and an OLED display.
Matching Linux kernel patch has been posted:
https://lore.kernel.org/imx/20240925160343.84388-2-ma...@d
Update simple-framebuffer device-tree node by enumerating framebuffer
related information in existing simple-framebuffer node in Linux
device-tree file and enabling it.
In case there is no simple-framebuffer stub detected in Linux kernel
device-tree and video is still active, then update the devic
This series fixes some compilation issues related to FDT_SIMPLEFB
and VIDEO and along with that enables support for dynamic simplefb
node enablement for AM62x platform.
Devarsh Thakkar (3):
boot/Kconfig: Add Video Kconfig as dependency for FDT_SIMPLEFB
boot: fdt_simplefb: Remove conditional co
CONFIG_VIDEO conditional compilation checks are no longer needed since
FDT_SIMPLEFB Kconfig now depends on VIDEO Kconfig.
Signed-off-by: Devarsh Thakkar
Reviewed-by: Mattijs Korpershoek
---
boot/fdt_simplefb.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/boot/fdt_simplefb.c b/boot/fdt_s
The fdt_simplefb.c APIs rely on video-uclass APIs and structures to
fill/update framebuffer information, so compile it only when VIDEO
Kconfig is enabled, as otherwise below warning can be seen if VIDEO
Kconfig is disabled:
"boot/fdt_simplefb.c:96:12: warning: fdt_simplefb_enable_existing_node
def
On Fri, 20 Sept 2024 at 16:59, Simon Glass wrote:
> On Fri, 20 Sept 2024 at 12:29, Patrick Rudolph
> wrote:
> > On Fri, Sep 20, 2024 at 11:37 AM Simon Glass wrote:
> > > On Fri, 20 Sept 2024 at 09:54, Patrick Rudolph
> > > wrote:
> > > >
> > > > On Thu, Sep 19, 2024 at 4:10 PM Simon Glass wrot
Hi Marek,
On Tue, Sep 24, 2024 at 9:12 PM Marek Vasut wrote:
>
> Add support for DH electronics i.MX8MP DHCOM SoM on DRC02 carrier board.
> This system is populated with two ethernet ports, two CANs, RS485 and RS232,
> USB, capacitive buttons and an OLED display.
The patch looks good. Only one s
On 9/25/24 8:13 AM, Chee, Tien Fong wrote:
Hi,
-Original Message-
From: Marek Vasut
Sent: Wednesday, September 25, 2024 2:36 AM
To: Chee, Tien Fong ; u-boot@lists.denx.de
Cc: Simon Goldschmidt ; Meng, Tingting
; Yuslaimi, Alif Zakuan
; Hea, Kok Kiang
Subject: Re: [PATCH v1 08/20] arm:
On 9/25/24 8:06 AM, Chee, Tien Fong wrote:
Hi,
Add a new .data section for preserving the original state of the
.data section of SoC64 SPL. This new .data section is required to
make SPL reentrant after warm reset.
Where is the linker script copied from ? What is the original file
name and pat
On 9/25/24 7:40 AM, Chee, Tien Fong wrote:
Hi,
arch/arm/cpu/armv7/lowlevel_init.S:.pushsection .text.s_init, "ax"
arch/arm/cpu/armv7/lowlevel_init.S:WEAK(s_init)
arch/arm/cpu/armv7/lowlevel_init.S:ENDPROC(s_init)
arch/arm/cpu/armv7/lowlevel_init.S: bl s_init
Maybe such a default lowle
Hi Simon,
On Wed, 25 Sept 2024 at 15:48, Simon Glass wrote:
>
> Hi Ilias,
>
> On Mon, 23 Sept 2024 at 11:49, Ilias Apalodimas
> wrote:
> >
> > Hi Simon,
> >
> > On Fri, 20 Sept 2024 at 10:25, Simon Glass wrote:
> > >
> > > Separate BSS is current mandatory on armv8 but this is not useful for
>
Add this to CI. This relies on a u-boot-test-hooks update
Signed-off-by: Simon Glass
---
.azure-pipelines.yml | 3 +++
.gitlab-ci.yml | 6 ++
2 files changed, 9 insertions(+)
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index 93111eb6127..51c4346ce64 100644
--- a/.azure-p
Move SPL to start in the RAM region, using the relocating loader to copy
it there and run from there.
Add a simple test to make sure this works as expected.
Signed-off-by: Simon Glass
---
arch/arm/dts/qemu-arm64.dts | 1 -
board/emulation/qemu-arm/xpl.c | 15 +++
configs/qe
Collect the relocation code in one place so that it can be used by the
SPL relocating-loader.
Signed-off-by: Simon Glass
---
arch/arm/cpu/armv8/u-boot-spl.lds | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds
b/arch/arm/cpu/armv8/u-boot-spl.lds
index
Mark the lz4 decompression code as needed by relocation. This is used to
decompress the next-phase image.
Drop the 'safe' versions from SPL as they are not needed. Change the
static array to a local one, to avoid link errors when trying to access
the data.
Signed-off-by: Simon Glass
---
lib/lz
Add some debugging here so it is easier to see what is going on.
Signed-off-by: Simon Glass
---
common/spl/spl.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 878036210c4..75fa1a854d9 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -2
We want to be able to test the relocating XPL loader. Add a new build
for ARM QEMU which supports booting from TPL into SPL
This builds an image containing TPL, SPL and U-Boot proper. To run it:
qemu-system-aarch64 -machine virt -nographic -cpu cortex-a57 \
-bios image.bin
Signed-off-by
This is only "U-Boot" when in SPL. For earlier phases it should use the
correct value, so update this.
Signed-off-by: Simon Glass
---
common/spl/spl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 623e486c210..2466b98f5a8 100644
--
Indicate that these boards can be supported, so a new 'TPL' board can be
added.
Signed-off-by: Simon Glass
---
arch/arm/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 656f588a97c..dfc735237aa 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/K
Use spl_get_image_pos() to obtain the image position to jump to. Add
the symbols used for VPL so that the correct image can be loaded.
Use the functions provided for accessing these symbols and add a few
comments too.
Signed-off-by: Simon Glass
---
common/spl/spl.c | 22 --
Binman provides the exact size of the SPL image being loaded, so show
how to fill this in. The code is not used, since it does provide a size
increase.
Signed-off-by: Simon Glass
---
common/spl/spl.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 2
This is fairly easy to use. The SPL loader sets up some fields in the
spl_image_info struct and calls spl_reloc_prepare(). When SPL is ready
to do the jump it must call spl_reloc_jump() instead of jump_to_image().
Add this logic.
Signed-off-by: Simon Glass
---
common/spl/spl.c | 12 +++
When one XPL phase wants to jump to the next, the next phase must be
loaded into its required address. This means that the TEXT_BASE for the
two phases must be different and there cannot be any memory overlap
between the phases. It also can mean that phases need to be moved
around to accommodate an
This function will be used by the relocating jumper too, so add a
typedef to the header file to avoid mismatches.
Signed-off-by: Simon Glass
---
common/spl/spl.c | 3 +--
include/spl.h| 3 +++
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/common/spl/spl.c b/common/spl/spl.c
Mark these functions as needed by relocation. This is used to copy data
while relocating the next-phase image.
Drop the 'safe' versions from SPL as they are not needed. Change the
static array to a local one, to avoid link errors when trying to access
the data.
Signed-off-by: Simon Glass
---
l
Mark the crc8 code as needed by relocation. This is used as a simple
check against corruption of the code when copying.
Signed-off-by: Simon Glass
---
lib/crc8.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/lib/crc8.c b/lib/crc8.c
index 811e19917b4..bbb229c3892 10064
Update the build rule so that hash algorithms are only included in an
SPL build if they are requested. This helps to reduce code size.
Signed-off-by: Simon Glass
---
lib/Makefile | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/lib/Makefile b/lib/Makefile
index 9478257e
Add a linker symbol which can be used to mark relocation code, so it can
be collected by the linker and copied into a suitable place and executed
when needed.
Signed-off-by: Simon Glass
---
include/asm-generic/sections.h | 16
1 file changed, 16 insertions(+)
diff --git a/incl
Provide a field in struct spl_load_info to indicate the phase of the
image which should be loaded. This is needed by VBE, which can load
images in various phases.
Set the phase to none by default.
Signed-off-by: Simon Glass
---
include/spl.h | 23 +++
1 file changed, 23 ins
This is a block length, so typicaly 512 bytes. Reduce the size to
16 bits to save space, before more fields are added in future work.
Signed-off-by: Simon Glass
---
include/spl.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/spl.h b/include/spl.h
index d90eed956af.
Hi Ilias,
On Mon, 23 Sept 2024 at 12:03, Ilias Apalodimas
wrote:
>
> On Fri, 20 Sept 2024 at 19:03, Simon Glass wrote:
> >
> > Hi Ilias,
> >
> > On Fri, 20 Sept 2024 at 14:10, Ilias Apalodimas
> > wrote:
> > >
> > > Hi Simon
> > >
> > > A few more comments after looking into this a bit more
> >
Hi Heinrich,
On Wed, 25 Sept 2024 at 13:55, Heinrich Schuchardt wrote:
>
> On 25.09.24 12:44, Simon Glass wrote:
> > With sandbox_spl we want to use the file-based boot in CI, so that this
> > flow is tested. The recent UPL change enabled booting via that method,
> > thus overriding the file-base
Hi Sughosh,
On Fri, 20 Sept 2024 at 13:38, Sughosh Ganu wrote:
>
> On Fri, 20 Sept 2024 at 14:51, Ilias Apalodimas
> wrote:
> >
> > Hi Sughosh,
> >
> > On Tue, 17 Sept 2024 at 15:33, Sughosh Ganu wrote:
> > >
> > > On Sat, 14 Sept 2024 at 20:38, Heinrich Schuchardt
> > > wrote:
> > > >
> > >
Hi Tom,
On Fri, 20 Sept 2024 at 16:59, Tom Rini wrote:
>
> On Fri, Sep 20, 2024 at 09:25:29AM +0200, Simon Glass wrote:
> > Hi Tom,
> >
> > On Thu, 19 Sept 2024 at 19:45, Tom Rini wrote:
> > >
> > > On Thu, Sep 19, 2024 at 04:10:12PM +0200, Simon Glass wrote:
> > > > Hi Tom,
> > > >
> > > > On T
Hi Heinrich,
On Mon, 23 Sept 2024 at 14:15, Heinrich Schuchardt wrote:
>
> On 19.09.24 16:13, Simon Glass wrote:
> > Hi Heinrich,
> >
> > On Sat, 14 Sept 2024 at 09:40, Heinrich Schuchardt
> > wrote:
> >>
> >> On 02.09.24 00:22, Simon Glass wrote:
> >>> From my inspection none of the users ne
Hi Heinrich,
On Sun, 22 Sept 2024 at 11:02, Heinrich Schuchardt wrote:
>
> On 9/19/24 17:14, Simon Glass wrote:
> > Move this section of the README into doc/ with some minor updates to
> > mention SPL and user lower-case hex.
> >
> > Signed-off-by: Simon Glass
> > ---
> >
> > README
Hi Tom,
On Fri, 20 Sept 2024 at 18:40, Tom Rini wrote:
>
> On Fri, Sep 20, 2024 at 06:04:05PM +0200, Simon Glass wrote:
> > Hi Tom,
> >
> > On Fri, 20 Sept 2024 at 17:01, Tom Rini wrote:
> > >
> > > On Fri, Sep 20, 2024 at 09:25:53AM +0200, Simon Glass wrote:
> > > > Hi Tom,
> > > >
> > > > On F
Hi Heinrich,
On Sun, 22 Sept 2024 at 15:43, Heinrich Schuchardt
wrote:
>
> On 20.09.24 17:58, Simon Glass wrote:
> > Hi Ilias,
> >
> > On Fri, 20 Sept 2024 at 09:37, Ilias Apalodimas
> > wrote:
> >>
> >> Hi Simon,
> >>
> >> On Fri, 20 Sept 2024 at 10:25, Simon Glass wrote:
> >>>
> >>> Hi Ilias,
Hi Tom,
On Mon, 23 Sept 2024 at 22:35, Tom Rini wrote:
>
> On Fri, Sep 20, 2024 at 08:01:39AM +0200, Simon Glass wrote:
>
> > Sometimes we know that the board is already running the right software,
> > so provide an option to allow running of tests directly, without first
> > resetting the board.
Hi Tom,
On Mon, 23 Sept 2024 at 22:36, Tom Rini wrote:
>
> On Fri, Sep 20, 2024 at 08:01:35AM +0200, Simon Glass wrote:
>
> > Labgrid provides access to a hardware lab in an automated way. It is
> > possible to boot U-Boot on boards in the lab without physically touching
> > them. It relies on re
Hi Tom,
On Mon, 23 Sept 2024 at 22:35, Tom Rini wrote:
>
> On Fri, Sep 20, 2024 at 08:01:36AM +0200, Simon Glass wrote:
>
>
> > When Labgrid is used, it can get U-Boot ready for running tests. It
> > prints a message when it has done so.
> >
> > Add logic to detect this message and accept it.
> >
Hi Tom,
On Mon, 23 Sept 2024 at 22:35, Tom Rini wrote:
>
> On Thu, Sep 19, 2024 at 04:13:57PM +0200, Simon Glass wrote:
> > Hi Tom,
> >
> > On Wed, 31 Jul 2024 at 19:17, Tom Rini wrote:
> > >
> > > On Wed, Jul 31, 2024 at 08:39:30AM -0600, Simon Glass wrote:
> > > > Hi Tom,
> > > >
> > > > On Mo
On 9/25/24 12:18 PM, Svyatoslav Ryhel wrote:
[...]
Hello there!
I was digging this when I had some free time and found that with
patches from Marek the only difference is that function
i2c_get_chip_for_busnum is not called for PMIC's main i2c address
Is it possible this is called earlier, bef
Hi,
On Fri, 20 Sept 2024 at 18:49, Tom Rini wrote:
>
> On Fri, Sep 20, 2024 at 07:40:35PM +0300, Svyatoslav Ryhel wrote:
> > пн, 16 вер. 2024 р. о 19:28 Tom Rini пише:
> > >
> > > On Wed, Sep 11, 2024 at 07:00:56PM -0600, Simon Glass wrote:
> > > > Hi Marek,
> > > >
> > > > On Fri, 28 Jun 2024 a
ср, 25 вер. 2024 р. о 02:44 Tom Rini пише:
>
> On Fri, Sep 20, 2024 at 10:48:56AM -0600, Tom Rini wrote:
> > On Fri, Sep 20, 2024 at 07:40:35PM +0300, Svyatoslav Ryhel wrote:
> > > пн, 16 вер. 2024 р. о 19:28 Tom Rini пише:
> > > >
> > > > On Wed, Sep 11, 2024 at 07:00:56PM -0600, Simon Glass wro
Hi Heinrich,
On Mon, 23 Sept 2024 at 14:36, Heinrich Schuchardt wrote:
>
> On 12.09.24 02:59, Simon Glass wrote:
> > Hi Sughosh,
> >
> > On Wed, 11 Sept 2024 at 00:50, Sughosh Ganu wrote:
> >>
> >> On Wed, 11 Sept 2024 at 00:14, Simon Glass wrote:
> >>>
> >>> Hi Sughosh,
> >>>
> >>> On Mon, 9 S
Hi Ilias,
On Mon, 23 Sept 2024 at 11:49, Ilias Apalodimas
wrote:
>
> Hi Simon,
>
> On Fri, 20 Sept 2024 at 10:25, Simon Glass wrote:
> >
> > Separate BSS is current mandatory on armv8 but this is not useful for
> > early boot phases. Add support for the combined BSS.
> >
> > Use an #ifdef to avo
Hi Tom,
On Tue, 24 Sept 2024 at 16:29, Tom Rini wrote:
>
> On Tue, Sep 24, 2024 at 03:17:15PM +0200, Patrick Rudolph wrote:
> > On Fri, Sep 20, 2024 at 5:59 PM Simon Glass wrote:
> > >
> > > Hi Patrick,
> > >
> > > On Fri, 20 Sept 2024 at 12:29, Patrick Rudolph
> > > wrote:
> > > >
> > > > On F
From: Oliver Gaskell
This adds support for using the GPIO pins on the SC5XX family of SoCs
from Analog Devices.
Co-developed-by: Nathan Barrett-Morrison
Signed-off-by: Nathan Barrett-Morrison
Co-developed-by: Ian Roberts
Signed-off-by: Ian Roberts
Signed-off-by: Vasileios Bimpikas
Signed-of
From: Oliver Gaskell
Co-developed-by: Greg Malysa
Signed-off-by: Greg Malysa
Co-developed-by: Ian Roberts
Signed-off-by: Ian Roberts
Co-developed-by: Angelo Dureghello
Signed-off-by: Angelo Dureghello
Signed-off-by: Vasileios Bimpikas
Signed-off-by: Utsav Agarwal
Signed-off-by: Arturs Art
From: Oliver Gaskell
This adds support for pin configuration on the Analog Devices SC5XX SoC
family. This commit is largely a port of the Linux driver, which has not
yet been submitted upstream.
Co-developed-by: Nathan Barrett-Morrison
Signed-off-by: Nathan Barrett-Morrison
Co-developed-by: Ia
This series adds all of the supported peripheral drivers for the sc5xx
series of SoCs from Analog Devices and other drivers that are used by
the evaluation kits, such as a GPIO expander used by the EZLITE carrier
boards.
This series is based on my earlier patch series:
"arm: Initial support for
From: Oliver Gaskell
Co-developed-by: Greg Malysa
Signed-off-by: Greg Malysa
Co-developed-by: Ian Roberts
Signed-off-by: Ian Roberts
Signed-off-by: Vasileios Bimpikas
Signed-off-by: Utsav Agarwal
Signed-off-by: Arturs Artamonovs
Signed-off-by: Nathan Barrett-Morrison
Signed-off-by: Oliver
From: Oliver Gaskell
This adds support for the ADI-specific SPI driver present in the ADI
SC5xx line of SoCs. This IP block is distinct from the QSPI/OSPI block
that uses the Cadence driver. Both may be used at once with appropriate
pin muxing configuration.
Co-developed-by: Greg Malysa
Signed-
From: Nathan Barrett-Morrison
This adds the ability to load ldr-formatted files to the SHARC
coprocessors using the rproc interface. Only a minimal subset
of rproc functionality is supported: loading and starting
the remote core.
Secure boot and signed ldr verification are not available
at this
From: Greg Malysa
Add a rudimentary MDMA driver for the Analog Devices SC5xx SoCs,
primarily intended for use with and tested against the QSPI/OSPI
IP included in the SoC.
Co-developed-by: Ian Roberts
Signed-off-by: Ian Roberts
Co-developed-by: Nathan Barrett-Morrison
Signed-off-by: Nathan Ba
From: Oliver Gaskell
Co-developed-by: Greg Malysa
Signed-off-by: Greg Malysa
Co-developed-by: Ian Roberts
Signed-off-by: Ian Roberts
Signed-off-by: Vasileios Bimpikas
Signed-off-by: Utsav Agarwal
Signed-off-by: Arturs Artamonovs
Signed-off-by: Nathan Barrett-Morrison
Signed-off-by: Oliver
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