On 08/06/2020 09:02, Maxime Ripard wrote:
> Hi,
>
> On Sat, Jun 06, 2020 at 09:58:13AM +, Heinrich Schuchardt wrote:
>> The current default of 0x400 for SYS_MALLOC_F_LEN is too small if any
>> additional drivers marked as DM_FLAG_PRE_RELOC are loaded before
>> relocation.
>>
>> CONFIG_RSA=y wh
On 03/06/2020 16:47, Heinrich Schuchardt wrote:
Hi Heinrich,
> On 03.06.20 01:46, André Przywara wrote:
>> On 02/06/2020 20:55, Tom Rini wrote:
>>
>> Hi,
>>
>>> On Tue, Jun 02, 2020 at 09:45:25PM +0200, Heinrich Schuchardt wrote:
>>>> On 6/2/20 5:5
On 02/06/2020 20:55, Tom Rini wrote:
Hi,
> On Tue, Jun 02, 2020 at 09:45:25PM +0200, Heinrich Schuchardt wrote:
>> On 6/2/20 5:51 PM, Tom Rini wrote:
>>> On Sun, May 31, 2020 at 10:43:00AM +, Heinrich Schuchardt wrote:
>>>
Booting pine64-lts_defconfig with either of CONFIG_RSA=y or CONFI
On 01/06/2020 14:56, Heinrich Schuchardt wrote:
> Provide accurate values of the manufacturer and the product name.
>
> PINE Microsystems Inc. is referred to on https://www.pine64.org/contact/.
While this patch looks alright, I wonder if we can just use the "model"
property in the DT's root node,
On 12/05/2020 16:09, Tom Rini wrote:
Hi,
> On Tue, May 12, 2020 at 03:53:55PM +0100, André Przywara wrote:
>> On 12/05/2020 15:25, Tom Rini wrote:
>>> On Tue, May 12, 2020 at 03:18:33PM +0100, André Przywara wrote:
>>>> On 09/05/2020 15:25, Amit Singh Tomar wrote:
On 12/05/2020 15:37, Amit Tomer wrote:
> Hi,
>
> On Tue, May 12, 2020 at 7:49 PM André Przywara wrote:
>>
>> On 09/05/2020 15:25, Amit Singh Tomar wrote:
>>> This patch adds node for ethernet controller found on Action Semi OWL
>>> S700 SoC.
>>&g
On 12/05/2020 15:25, Tom Rini wrote:
> On Tue, May 12, 2020 at 03:18:33PM +0100, André Przywara wrote:
>> On 09/05/2020 15:25, Amit Singh Tomar wrote:
>>> This patch adds node for ethernet controller found on Action Semi OWL
>>> S700 SoC.
>>>
>>> Since,
On 28/04/2020 18:57, Simon Glass wrote:
Hi,
sorry for the delay, found this, slightly mouldy already, in my draft
folder.
First, thanks for the review! I saw the Tom merged this already, but
wanted to come back to the DT hacks:
> Hi Andre,
>
> On Mon, 27 Apr 2020 at 12:18, Andre Przywara wrot
On 09/05/2020 15:25, Amit Singh Tomar wrote:
> This patch adds node for ethernet controller found on Action Semi OWL
> S700 SoC.
>
> Since, there is no upstream Linux binding exist for S700 ethernet
> controller, Changes are put in u-boot specific dtsi file.
But that should not be the S700 SoC .d
On 24/04/2020 15:51, Tom Rini wrote:
Hi Tom,
> On Tue, Apr 07, 2020 at 12:12:31PM +0100, Andre Przywara wrote:
>
>> Even though the PL011 UART driver claims to be DM compliant, it does not
>> really a good job with parsing DT nodes. U-Boot seems to adhere to a
>> non-standard binding, either req
On 17/04/2020 13:44, Tom Rini wrote:
> On Fri, Apr 17, 2020 at 01:34:36PM +0100, André Przywara wrote:
>> On 17/04/2020 13:11, Tom Rini wrote:
>>> On Fri, Apr 17, 2020 at 08:31:38PM +0900, Masahiro Yamada wrote:
>>>> On Fri, Apr 17, 2020 at 6:07 PM André Przywara
&g
On 17/04/2020 13:11, Tom Rini wrote:
> On Fri, Apr 17, 2020 at 08:31:38PM +0900, Masahiro Yamada wrote:
>> On Fri, Apr 17, 2020 at 6:07 PM André Przywara
>> wrote:
>>>
>>> On 17/04/2020 04:05, Tom Rini wrote:
>>>
>>> (adding Masahiro for Kconfig
On 17/04/2020 04:05, Tom Rini wrote:
(adding Masahiro for Kconfig)
> On Mon, Apr 06, 2020 at 05:58:19PM +0530, Amit Singh Tomar wrote:
>
>> This adds Cubieboard7[1] support based on Action Semi's S700 SoC[2], It's
>> Quad-core ARMv8 SoC
>> with Cortex-A53 cores. Peripheral like UART seems to be
On 05/04/2020 07:59, Manivannan Sadhasivam wrote:
> On Wed, Apr 01, 2020 at 12:49:26PM +0530, Amit Singh Tomar wrote:
>> This patch adds "actions,owl-uart" string to the owl uart driver. It
>> is also defined in Linux kernel.
>>
>> Reviewed-by: Andre Przywara
>> Signed-off-by: Amit Singh Tomar
>>
On 28/03/2020 14:32, Jagan Teki wrote:
> On Tue, Mar 3, 2020 at 8:37 PM Jonas Smedegaard wrote:
>>
>> commit 37304aaf60bf ("Convert CONFIG_USE_PREBOOT and CONFIG_PREBOOT to
>> Kconfig") intended to support CONFIG_PREBOOT, but
>> include/configs/sunxi-common.h hardcodes preboot as part of internall
On 26/03/2020 16:20, Simon Glass wrote:
Hi Simon,
> On Wed, 25 Mar 2020 at 08:47, Andre Przywara wrote:
>>
>> Even though the PL011 UART driver claims to be DM compliant, it does not
>> really a good job with parsing DT nodes. U-Boot seems to adhere to a
>> non-standard binding, either requiring
On 26/03/2020 02:38, Tom Rini wrote:
Hi,
> On Wed, Mar 25, 2020 at 02:46:56PM +, Andre Przywara wrote:
>
>> The U-Boot documentation explains that variables ending with "_r" hold
>> addresses in DRAM, while those without that ending point to flash/ROM.
>> The default variables for the Juno b
On 21/03/2020 17:30, Amit Singh Tomar wrote:
Hi Mani,
> This adds Cubieboard7[1] support based on Action Semi's S700 SoC[2], It's
> Quad-core ARMv8 SoC
> with Cortex-A53 cores. Peripheral like UART seems to be compatible with S900
> SoC(basic support
> for it is alreay present in u-boot).
I re
On 21/03/2020 17:30, Amit Singh Tomar wrote:
> This commit adds common arch support for Actions Semi Owl
> series SoCs and removes the Bubblegum96 board files.
>
> Signed-off-by: Amit Singh Tomar
Reviewed-by: Andre Przywara
Cheers,
Andre
> ---
> Changes since v7:
> * Removed S900 specif
On 21/03/2020 17:30, Amit Singh Tomar wrote:
> This patch adds basic support for Actions Semi based S700
> SoC, which is driven by common owl framework.
>
> Signed-off-by: Amit Singh Tomar
Reviewed-by: Andre Przywara
Cheers,
Andre
> ---
> Changes since v7:
> * Removed S700 include file.
On 18/03/2020 18:25, Amit Singh Tomar wrote:
Hi,
> This commit adds common arch support for Actions Semi Owl
> series SoCs and removes the Bubblegum96 board files.
>
> Signed-off-by: Amit Singh Tomar
> ---
> Chanes since v5:
> * No change.
> Chanes since v4:
> * No change.
> Cha
On 18/03/2020 18:25, Amit Singh Tomar wrote:
> The Cubieboard is a single board computer containing a
> Actions S700 SoC(with 4 ARMv8 Cortex-A53 cores).
>
> This patch adds respective defconfig alongwith .dts(copied
> from Linux v5.5-rc6 with hash "b3a987b0264d").
>
> Signed-off-by: Amit Singh To
On 18/03/2020 18:25, Amit Singh Tomar wrote:
> This patch moves some of the config options from bubblegum_96_defconfig
> to platform specific Kconfig file.
>
> Signed-off-by: Amit Singh Tomar
> ---
> Changes since v5:
> * Newly added patch, was not there in earlier versions.
> ---
> arch/
On 18/03/2020 18:25, Amit Singh Tomar wrote:
> This patch converts S900 clock driver to something common that can
> be used for other SoCs, for instance S700(few of clk registers are same).
>
> Signed-off-by: Amit Singh Tomar
Compared clk_s900.h vs clk_owl.h, and checked the actual clock driver,
On 18/03/2020 18:25, Amit Singh Tomar wrote:
> Synchronize device tree bindings with v5.5-rc6 tag with commit id
> "b3a987b0264d".
>
> Also, it removes older clock binding defined for S900 along with undocumented
> compatible string "actions,s900-serial" from serial driver and adapts clock
> drive
On 18/03/2020 18:25, Amit Singh Tomar wrote:
> This patch adds "actions,owl-uart" string to the owl uart driver. It
> is also defined in Linux kernel.
>
> Signed-off-by: Amit Singh Tomar
Reviewed-by: Andre Przywara
Thanks,
Andre
> ---
> Changes since v5:
> * Moved it to from 06/11 to 03
On 17/03/2020 13:12, Petr Štetiar wrote:
Hi,
> This reverts commit 4c78028737c3185f49f5691183aeac3478b5f699.
>
> bl31.bin file is mandatory for functional, usable and bootable binaries,
> thus it should be hard error if bl31.bin is missing. It doesn't matter
> if I'm building on autobuilder or l
On 07/03/2020 15:30, Amit Tomer wrote:
> Hi,
>
>> Both those include files do not exist yet. This breaks bisectability for
>> bubblegum_96.
>> So I would suggest you remove the s700 lines for now, and change the
>> s900 filename to match the existing one.
>> Then change CLK_UART to CLOCK_UART belo
Hi,
On 07/03/2020 06:42, Amit Singh Tomar wrote:
> This patch converts S900 clock driver to something common that can
> be used for other SoCs, for instance S700(few of clk registers are same).
>
> Signed-off-by: Amit Singh Tomar
> ---
> Changes since v3:
> * Fixed register spelling.
>
On 21/01/2020 08:20, Jagan Teki wrote:
Hi Jagan,
first: many thanks for merging those other patches of mine, much
appreciated!
> On Mon, Jan 6, 2020 at 6:59 AM Andre Przywara wrote:
>>
>> So far we were using the CONFIG_SUNXI_GEN_SUN6I symbol to select between
>> the two SPI controller generati
On 26/01/2020 02:28, Matthias Brugger wrote:
> On 24/01/2020 01:26, André Przywara wrote:
[ ... ]
>> Found the culprit, after following a lead started by an over-lunch
>> discussion: Colleagues pointed out the SError (interrupts) early in the
>> kernel could just show
On 25/01/2020 16:20, Tom Rini wrote:
Hi Tom,
thanks for having a look!
> On Tue, Jan 21, 2020 at 10:23:17AM +, Andre Przywara wrote:
>
>> From: Maxime Ripard
>>
>> This is needed when importing mainline DTs into U-Boot, as some started
>> using this /omit-if-no-ref/ tag, so won't compile
On 23/01/2020 19:37, Matthias Brugger wrote:
Hi,
> On 23/01/2020 12:29, Andre Przywara wrote:
>> On Wed, 22 Jan 2020 19:05:10 +0100
>> Matthias Brugger wrote:
>>
>> Hi,
>>
>> Matthias, many thanks for looking at this and giving it a try!
>>
>>> On 22/01/2020 18:34, Andre Przywara wrote:
On
On 27/12/2019 18:57, Heinrich Schuchardt wrote:
Hi Heinrich,
> On 11/25/19 2:32 AM, Andre Przywara wrote:
>> doc/README.drivers.eth seems like a good source for understanding
>> U-Boot's network subsystem, but is only talking about legacy network
>> drivers. This is particularly sad as proper doc
On 27/12/2019 16:41, Simon Glass wrote:
Hi Simon,
> On Sun, 24 Nov 2019 at 18:32, Andre Przywara wrote:
>>
>> doc/README.drivers.eth seems like a good source for understanding
>> U-Boot's network subsystem, but is only talking about legacy network
>> drivers. This is particularly sad as proper d
On 23/12/2019 18:42, Stefan Wahren wrote:
Hi Stefan,
> Am 20.12.19 um 20:29 schrieb Stefan Wahren:
>> Hi Andre,
>>
>> Am 18.12.19 um 12:59 schrieb Andre Przywara:
>>> From: Amit Singh Tomar
>>>
>>> The Broadcom GENET Ethernet MACs are used in several MIPS based SoCs
>>> and in the Broadcom 2711/
On 19/12/2019 00:55, Marek Vasut wrote:
Hi Marek,
> On 12/19/19 1:52 AM, Andre Przywara wrote:
>> According to commit 11aa6a32eb5f ("arm: cache: Implement cache range
>> check for v7"), which introduced check_cache_range(), this was meant
>> as a pure debugging feature, only to be compiled in whe
On Thu, 5 Sep 2019 14:26:41 +0200
Marek Vasut wrote:
Hi,
> On 9/5/19 2:54 AM, André Przywara wrote:
> > On 04/09/2019 18:56, Marek Vasut wrote:
> >> On 9/4/19 7:32 PM, Andre Przywara wrote:
> >>>> I have been avoiding this thread but today I attended a talk
On 04/09/2019 18:56, Marek Vasut wrote:
> On 9/4/19 7:32 PM, Andre Przywara wrote:
Hi Marek,
>>> I have been avoiding this thread but today I attended a talk on ATF
>>> and ARM's approach in general. ARM seems to be moving towards an
>>> approach of providing increasingly complex source code to a
is, the check is not reliable for some
>>> unknown reason, probably having to do with unpredictable memory
>>> access ordering.
>>>
>>> Patch was made with help from André Przywara, who noticed that
>>> my original idea about detection failing due t
On 17/07/2019 23:16, Jernej Skrabec wrote:
> Half DQ configuration seems to be very rare for H6 based boards/STBs,
> but exists nevertheless. Currently the only known product which needs
> this support is Tanix TX6 mini.
>
> This commit adds support for half DQ configuration. Code was tested
> for
On Fri, 2 Aug 2019 10:47:10 +0300
Oskari Lemmelä wrote:
Hi Oskari,
> On 2.8.2019 3.15, André Przywara wrote:
> > On 01/08/2019 20:50, Oskari Lemmela wrote:
> >
> > Hi,
> >
> >> enable config options for spi flash device and
> >> environment in spi
On 01/08/2019 21:07, Oskari Lemmela wrote:
Hi,
> Add a boot command to distro boot to support load FIT image
> from SPI flash.
I think I mentioned this before, but I have my reservations about
introducing this to *distro_bootcmd*. IIUC, this feature is explicitly
about providing easy support for
On 01/08/2019 20:50, Oskari Lemmela wrote:
Hi,
> enable config options for spi flash device and
> environment in spi flash.
First I am not sure if defining this unconditionally to put the
environment in SPI flash is a good idea. People might expect to be able
to (continue to) use an environment
On 13/07/2019 10:55, Jernej Škrabec wrote:
Hi,
> Dne torek, 02. julij 2019 ob 11:51:41 CEST je Andre Przywara napisal(a):
>> An updated version, with minor changes.
>> I realised that my comments about JEDEC values were still based on the
>> DDR3-1600 speed bin, so I updated those to match the DD
mpete against each other. They just
complement each other nicely, hence we use ATF and save us the burden of
having to reprogram something in U-Boot.
> On 6/29/19 8:49 PM, André Przywara wrote:
>> On 29/06/2019 16:02, Jagan Teki wrote:
>>> In terms of code maintenance and development f
On 29/06/2019 16:02, Jagan Teki wrote:
> In terms of code maintenance and development feasibility it is always
> a better approach to have out-of-tree code or binary to be part of
> in-house source tree.
I am not sure this is really true. If I get you right, you want to
mirror and sync the ATF sou
On 20/06/2019 19:01, Clément Péron wrote:
Hi Clément,
thanks for trying that!
...
> On Wed, 19 Jun 2019 at 12:03, Andre Przywara wrote:
>>
>> On Wed, 19 Jun 2019 10:57:14 +0200
>> Clément Péron wrote:
>>
>> Hi,
>>
>>> On Wed, 19 Jun 2019 at 03
On 18/06/2019 08:50, Jagan Teki wrote:
> On Thu, May 16, 2019 at 6:56 AM Andre Przywara wrote:
Hi,
>> this series enables USB support on the H6 boards. This is mostly just
>> adding some missing pieces here and there, the actual controller and PHY
>> are very similar to the previous ones, if not
On 18/06/2019 18:17, Jernej Škrabec wrote:
> Dne torek, 18. junij 2019 ob 19:13:16 CEST je Clément Péron napisal(a):
Hi,
>> On Thu, 16 May 2019 at 03:27, Andre Przywara wrote:
>>> The first USB controller on the H6 SoC shares a PHY with the OTG
>>> controller. Reportedly to avoid problems with t
On Tue, 18 Jun 2019 19:22:34 +0200
Clément Péron wrote:
Hi,
> On Tue, 18 Jun 2019 at 19:08, Clément Péron wrote:
> >
> > Hi Andre,
> >
> > On Tue, 18 Jun 2019 at 09:50, Jagan Teki
> > wrote:
> > >
> > > On Thu, May 16, 2019 at 6:56 AM Andre Przywara
> > > wrote:
> > > >
> > > > Hi,
> >
On 17/04/2019 12:28, Jagan Teki wrote:
> On Mon, Apr 15, 2019 at 1:52 PM Paul Kocialkowski
> wrote:
Hi,
>> Le vendredi 12 avril 2019 à 14:49 +0530, Jagan Teki a écrit :
>>> On Thu, Mar 14, 2019 at 4:08 PM Paul Kocialkowski
>>> wrote:
Recent Allwinner platforms (starting with the H3) only u
On 17/05/2019 19:41, André Przywara wrote:
> On 17/05/2019 19:15, Vasily Khoruzhick wrote:
>> On Wed, May 15, 2019 at 5:46 PM Andre Przywara
>> wrote:
>>>
>>> Since the beginning the upper USB port on Pine64 boards (Pine64+, SoPine
>>> baseboard, Pin
On 17/05/2019 19:15, Vasily Khoruzhick wrote:
> On Wed, May 15, 2019 at 5:46 PM Andre Przywara wrote:
>>
>> Since the beginning the upper USB port on Pine64 boards (Pine64+, SoPine
>> baseboard, Pine64-LTS, Pinebook) was not working under U-Boot.
>> This is due to the PHY for those pins being shar
On 29/04/2019 18:16, Jagan Teki wrote:
Hi,
> On Sun, Feb 10, 2019 at 9:49 PM Andre Przywara wrote:
>>
>> Hi, this is a resend of what I posted some weeks ago, just adding the
>> missing Signed-off-by: in patch 2/3, as pointed out by Philipp. I used
>> the opportunity to add his Reviewed-by: tags
On 17/04/2019 13:00, Jagan Teki wrote:
> On Mon, Apr 15, 2019 at 1:21 PM André Przywara wrote:
>>
>> On 15/04/2019 07:22, Jagan Teki wrote:
>>
>> Hi,
>>
>>> On Mon, Apr 15, 2019 at 11:40 AM Chen-Yu Tsai wrote:
>>>>
>>>> On Mon, A
On 15/04/2019 07:22, Jagan Teki wrote:
Hi,
> On Mon, Apr 15, 2019 at 11:40 AM Chen-Yu Tsai wrote:
>>
>> On Mon, Apr 15, 2019 at 2:07 PM Jagan Teki
>> wrote:
>>>
>>> On Sun, Feb 10, 2019 at 9:49 PM Andre Przywara
>>> wrote:
Hi, this is a resend of what I posted some weeks ago, just
On 14/04/2019 13:54, Anatolij Gustschin wrote:
> Hi André,
>
> On Sat, 13 Apr 2019 22:40:03 +0100
> André Przywara andre.przyw...@arm.com wrote:
> ...
>>> I've dropped all applied patches of this series now, some of them
>>> introduced dm video_ansi test erro
On 11/04/2019 13:09, Anatolij Gustschin wrote:
Hi Anatolij,
thanks for the heads up!
> On Tue, 9 Apr 2019 23:05:11 +0200
> Anatolij Gustschin ag...@denx.de wrote:
> ...
>>> drivers/video/vidconsole-uclass.c | 37
>>> +
>>> 1 file changed, 37 insertions(+)
On 30/03/2019 21:18, Simon Glass wrote:
> On Fri, 22 Mar 2019 at 19:32, Andre Przywara wrote:
Hi Simon,
many thanks for the review of all those patches, much appreciated!
>> So far arrows key pressed on an USB keyboard got translated to some
>> low ASCII control sequences (Ctrl+N, Ctrl+P). Some
On 31/03/2019 19:28, Alexander Graf wrote:
Hi Simon, Alex,
> On 31.03.19 04:18, Simon Glass wrote:
>> Hi Andre,
>>
>> On Fri, 22 Mar 2019 at 19:32, Andre Przywara wrote:
>>> The character set used by U-Boot's built-in fonts is the old "code
>>> page 437" (from the original IBM PC).
>>> However p
On 09/03/2019 01:03, Andre Przywara wrote:
Hi,
> The Pine64-LTS defconfig is missing the CONFIG_USB_OHCI_HCD symbol, as
> this was added during the same time as this defconfig was merged.
> USB 1.x devices like USB keyboards don't work due to this.
>
> Add the symbol to the defconfig as all the
On 17/03/2019 18:41, Oskari Lemmelä wrote:
> On 3/17/19 6:04 PM, Peter Robinson wrote:
>> On Sun, Mar 17, 2019 at 2:56 PM Oskari Lemmela
>> wrote:
>>> Fixes spurious timeouts which have been seen during testing
>>> SPI_SUNXI driver. The false timeouts disappear when number of
>>> bits reduced to 1
On 22/02/2019 08:06, Alexander Graf wrote:
>
>
> On 21.02.19 02:30, Andre Przywara wrote:
>> Even though we introduced FIT image support for the SPL to cover the
>> 64-bit SoCs, there is no technical limitation to those parts.
>>
>> Change the Makefile stanza to always create a FIT image if the
>
On 20/02/2019 16:14, Alexander Graf wrote:
> Commit 1416e2d2253 ("armv8: make SPL exception vectors optional") had a
> typo in it which effectively disabled exception handling in SPL code always.
Thanks for uncovering this embarrassing bug!
> Since nobody complained, I guess we may as well disabl
On 14/02/2019 08:36, Jagan Teki wrote:
> - drop unused macros.
> - use base instead of base_addr, for better code readability
Actually this part is now pretty pointless, since we use it only a few
times, and base_addr is actually more descriptive than just "base".
> - move .probe and .ofdata_to_p
On 14/02/2019 08:36, Jagan Teki wrote:
Hi,
> Add A31 spi controller support for existing sun4i_spi driver via driver
> data, this would simply add A31 register along with proper register bits
> via enum sets.
>
> Signed-off-by: Jagan Teki
> ---
> drivers/spi/Kconfig | 4 +-
> drivers/spi/
On 14/02/2019 08:36, Jagan Teki wrote:
> Allwinner support two different SPI controllers one for A10 and
> another for A31 with minimal changes in register offsets and
> respective register bits, but the logic for accessing the SPI
> master via SPI slave remains nearly similar.
>
> Add enum offset
On 14/02/2019 08:36, Jagan Teki wrote:
> Add CLK support to enable AHB and MOD SPI clocks on sun4i_spi driver.
>
> Note, that the code will enable and disable clock in claim and release
> calls to make proper clock and reset handling between claiming and
> releasing SPI bus.
That doesn't really e
On 14/02/2019 08:36, Jagan Teki wrote:
> To drain rx fifo the fifo need to poll till the fifo
> count become empty.
Thanks for the changes!
Just realised, the description is somewhat misleading: We are not
waiting for the FIFO count to become empty, but actually for the RX FIFO
to fill up. Can you
On 14/02/2019 16:36, Philipp Tomsich wrote:
>
>
>> On 14.02.2019, at 16:58, Michael Trimarchi
>> wrote:
>>
>> Set two rank timing and exit self-refresh timing seems not done
>> properly. We know use the same write that we are using
>> on H5 silicon. Tested was done in A33 allwinner cpu, dual ra
On 09/02/2019 13:14, Jagan Teki wrote:
> Enable SUN4I_SPI by default for ARCH_SUNXI, so that board
> that would require to enable DM_SPI that eventually enable
> the SUN4I_SPI driver.
>
> Signed-off-by: Jagan Teki
> ---
> drivers/spi/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --gi
On 09/02/2019 13:15, Jagan Teki wrote:
> Sopine has Winbond SPI flash, so enable the same to use
> flash on Sopine board.
>
> Signed-off-by: Jagan Teki
> ---
> arch/arm/dts/sun50i-a64-sopine-baseboard-u-boot.dtsi | 12
> configs/sopine_baseboard_defconfig | 4
On 09/02/2019 13:14, Jagan Teki wrote:
> - drop unused macros.
> - use base instead of base_addr, for better code readability
> - move .probe and .ofdata_to_platdata functions in required
> places to add platdata support in future.
> - use sentinel sun4i_spi_ids.
>
> Signed-off-by: Jagan Teki
>
On 09/02/2019 13:14, Jagan Teki wrote:
> Add CLK support to enable AHB and MOD SPI clocks on sun4i_spi driver.
>
> Note, that the code will enable and disable clock in claim and release
> calls to make proper clock and reset handling between claiming and
> releasing SPI bus.
>
> Signed-off-by: Ja
On 09/02/2019 13:14, Jagan Teki wrote:
> Add A31 spi controller support for existing sun4i_spi driver via driver
> data, this would simply add A31 register along with proper register bits
> via enum sets.
>
> Signed-off-by: Jagan Teki
> ---
> drivers/spi/Kconfig | 4 +-
> drivers/spi/sun4i_
On 09/02/2019 13:14, Jagan Teki wrote:
> Support fifo_depth via drvdata instead of macro definition, this would
> eventually reduce another macro definition for new SPI controller fifo
> depth support addition.
>
> Signed-off-by: Jagan Teki
Reviewed-by: Andre Przywara
Cheers,
Andre
> ---
> d
On 09/02/2019 13:14, Jagan Teki wrote:
> Update the existing register writes using setbits_le32 and
> clrbits_le32 in required places.
>
> Signed-off-by: Jagan Teki
> ---
> drivers/spi/sun4i_spi.c | 21 -
> 1 file changed, 8 insertions(+), 13 deletions(-)
>
> diff --git a/dr
On 09/02/2019 13:14, Jagan Teki wrote:
> Allwinner support two different SPI controllers one for A10 and
> another for A31 with minimal changes in register offsets and
> respective register bits, but the logic for accessing the SPI
> master via SPI slave remains nearly similar.
>
> Add enum offset
On 09/02/2019 13:14, Jagan Teki wrote:
> - Implement SPI AHB, MOD clocks via ccu_clk_gate for all
> supported Allwinner SoCs
> - Implement SPI resets via ccu_reset for all supported
> Allwinner SoCs.
>
> Signed-off-by: Jagan Teki
Reviewed-by: Andre Przywara
Cheers,
Andre.
> ---
> drivers
On Sat, 9 Feb 2019 18:44:51 +0530
Jagan Teki wrote:
Hi,
> To drain rx fifo the fifo need to poll till the fifo
> count become empty.
>
> The current code is using wait_for_bit logic on control
> register with exchange burst mode mask, which is not a
> proper way of waiting for draining fifo.
>
On 06/02/2019 12:46, Philipp Tomsich wrote:
> On 11.01.2019, at 01:31, Andre Przywara wrote:
Hi,
>>
>> The normal MMIO accessor macros (readX/writeX) guarantee a strong ordering,
>> even with normal memory accesses [1].
>> For some MMIO operations (framebuffers being a prominent example) this is
On 21/01/2019 10:31, Jagan Teki wrote:
> Enable DM_MMC for all Allwinner SoCs, this will eventually
> enable BLK.
>
> Also removed DM_MMC enablement in few parts of sunxi
> configurations.
>
> Signed-off-by: Jagan Teki
Reviewed-by: Andre Przywara
Cheers,
Andre
> ---
> arch/arm/Kconfig
On 21/01/2019 10:31, Jagan Teki wrote:
> Unlike other Allwinner SoC's, A80 comes with different ahb
> gate clock offset values and also has mmc common controller.
> So support them via driver data.
As mentioned in the fix I sent, this requires the clock and reset
support for CCU devices themselves
On 21/01/2019 10:31, Jagan Teki wrote:
> Unlike other Allwinner SoC's, H6 comes with different
> clock and reset control offset values. So support them
> via driver data.
Nit: It's just the mod clock offset we care about here, the rest is
already handled by the new clock driver.
>
> Cc: Jaehoon
On 21/01/2019 10:31, Jagan Teki wrote:
> Added H5, A64 compatible for mmc and emmc.
As mentioned, could be merged with the previous patch.
> Cc: Jaehoon Chung
> Signed-off-by: Jagan Teki
Reviewed-by: Andre Przywara
Cheers,
Andre
> ---
> drivers/mmc/sunxi_mmc.c | 8
> 1 file change
On 21/01/2019 10:31, Jagan Teki wrote:
> Add emmc compatible for A83T SoC.
You could merge this one with the next patch.
> Cc: Jaehoon Chung
> Signed-off-by: Jagan Teki
Reviewed-by: Andre Przywara
Cheers,
Andre.
> ---
> drivers/mmc/sunxi_mmc.c | 4
> 1 file changed, 4 insertions(+)
>
On 21/01/2019 10:31, Jagan Teki wrote:
> From: Andre Przywara
>
> Add the MMC clock gates and reset bits for all the Allwinner SoCs.
> This allows them to be used by the MMC driver.
>
> We don't advertise the mod clock yet, as this is still handled by the
> MMC driver.
>
> Signed-off-by: Andre
On 21/01/2019 10:31, Jagan Teki wrote:
> Now CLK and RESET driver for Allwinner SoC are available,
> so add the relevant operations on mmc sunxi driver.
>
> Cc: Jaehoon Chung
> Signed-off-by: Jagan Teki
> ---
> Changes for v3:
> - Grab changes for ML
>
> drivers/mmc/sunxi_mmc.c | 52 ++
On 20/01/2019 19:51, Priit Laes wrote:
Hi,
> On Sat, Jan 19, 2019 at 01:30:46AM +, Andre Przywara wrote:
>> This series enables the Allwinner MMC driver to drive all SoCs with its
>> DM_MMC variant. We use the gates clock and reset support from the new
>> clock driver, but keep the actual mod
On 19/01/2019 18:32, Vasily Khoruzhick wrote:
> On Fri, Jan 18, 2019 at 5:32 PM Andre Przywara wrote:
>>
>> This series enables the Allwinner MMC driver to drive all SoCs with its
>> DM_MMC variant. We use the gates clock and reset support from the new
>> clock driver, but keep the actual mod cloc
On 19/01/2019 05:50, Jagan Teki wrote:
> On Fri, Jan 18, 2019 at 11:18 PM Andre Przywara
> wrote:
>>
>> On Fri, 18 Jan 2019 22:11:36 +0530
>> Jagan Teki wrote:
>>
>> Hi,
>>
>>> On Fri, Jan 18, 2019 at 6:00 PM Andre Przywara
>>> wrote:
On Fri, 18 Jan 2019 07:17:41 -0500
Tom Rini
On Thu, 17 Jan 2019 20:45:44 +0530
Manivannan Sadhasivam wrote:
Hi,
> On Tue, Jan 15, 2019 at 12:43:36AM +0000, André Przywara wrote:
> > On 14/01/2019 12:41, Amit Singh Tomar wrote:
> >
> > Hi,
> >
> > > CMU block on most of the actions SoC seems to b
On Thu, 17 Jan 2019 21:09:45 +0530
Manivannan Sadhasivam wrote:
Hi,
> [On top of Andre's review]
>
> On Mon, Jan 14, 2019 at 06:11:03PM +0530, Amit Singh Tomar wrote:
> > This adds common arch owl support that can drive, 64-bits SoCs
> > from Actions Semi.
> >
>
> Could be, "This commit add
On 14/01/2019 12:41, Amit Singh Tomar wrote:
Hi,
> CMU block on most of the actions SoC seems to be identical(at-least, S900 and
> S700).
Actually they are not. Not even for the small subset that we implement
here. Try "diff -wu arch/arm/include/asm/arch-owl/regs_s*.h" for a
start, plus the dif
On 14/01/2019 12:41, Amit Singh Tomar wrote:
Hi,
> This adds common arch owl support that can drive, 64-bits SoCs
> from Actions Semi.
>
> It also removes the Bubblegum specific board files.
>
> Signed-off-by: Amit Singh Tomar
> ---
> Changes since v1:
> * Moved S700 specific changes to
On 14/01/2019 12:41, Amit Singh Tomar wrote:
> UART controller present on S700 is compatible with existing
> S900 controller, this patch simply adds a proper compatible string
> so that owl uart driver can be reused for S700.
>
> Signed-off-by: Amit Singh Tomar
Reviewed-by: Andre Przywara
Chee
On 14/01/2019 12:41, Amit Singh Tomar wrote:
> The Cubieboard is a single board computer containing a
> Actions S700 SoC(with 4 ARMv8 Cortex-A53 cores).
>
> This patch adds respective defconfig alongwith device tree(sync with
> Linux 4.20).
This should come later in the series, as patch 8/9, just
On 14/01/2019 12:41, Amit Singh Tomar wrote:
Hi,
> This adds memory regions needed to setup MMU for actions
> S900 and S700 SoCs.
Please change this sentence and the subject to state that this just
moves code, there is nothing new here that gets added. That helps later
when people browse through
On 10/01/2019 18:40, Jagan Teki wrote:
> CLK and DM_RESET drivers are now available for most
> of the Allwinner platforms, so enable in mach-sunxi/Kconfig
>
> Enabling CLK will select DM_RESET by default.
Shame we don't have the new A80 DTs in our tree, otherwise we would have
got away with a one
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