pointer after calling the stop() handler.
Signed-off-by: Bernhard Rosenkränzer
---
net/eth-uclass.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index f41da4b37b..410f3310c7 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -343,6 +343,11
The SPI and NAND board variants never went into production.
Drop those board variants.
Signed-off-by: Bernhard Messerklinger
---
arch/arm/dts/Makefile | 2 -
arch/arm/dts/am335x-brppt1-nand.dts | 374 ---
arch/arm/dts/am335x-brppt1-spi.dts | 377
Drop board variants that were never produced, fix the SPL loader,
and update environment.
Bernhard Messerklinger (5):
brppt1: Remove unused board variants
brppt1: Fix SPL boot stage
brppt1: Cleanup device tree
include: configs: brppt1: Fix commit 0ea4fc4dcf90
brppt1: Update
* Remove unnecessary device tree nodes which are not needed in
U-Boot directly.
* Move all U-Boot specific device tree properties to u-boot dtsi.
Signed-off-by: Bernhard Messerklinger
---
arch/arm/dts/am335x-brppt1-mmc-u-boot.dtsi | 32
arch/arm/dts/am335x-brppt1-mmc.dts | 201
tbaddr} and configuration script at
${cfgaddr} to ensure proper boot in warm restart case.
Signed-off-by: Bernhard Messerklinger
---
configs/brppt1_mmc_defconfig | 4 +++-
include/configs/brppt1.h | 18 --
2 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/c
ivers are dropped.
Signed-off-by: Bernhard Messerklinger
---
arch/arm/dts/am335x-brppt1-mmc-u-boot.dtsi | 80 ++
configs/brppt1_mmc_defconfig | 2 +-
2 files changed, 81 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/am335x-brppt1-mmc-u-boot.dtsi
di
e. Because
of this, cfgscr is not allowed to destroy the previously loaded device
tree otherwise cfgscr will fail.
This patch moves the device trees invalidation on warm restart to the
PREBOOT cmd to fix that issue.
Fixes: 0ea4fc4dcf90 ("board/BuR: invalidate ${dtbaddr} before cfgscr")
Sig
patman's --limit-cc option parses its argument to an integer and uses
that to trim the list of CC recipients to a particular maximum. but that
only works if the cc variable is a list, which it is not.
Signed-off-by: Bernhard Kirchen
---
tools/patman/series.py | 2 +-
1 file changed, 1
t asserted, as the respective registers are write-protected
in that case.
Signed-off-by: Bernhard Kirchen
---
drivers/mtd/spi/spi-nor-core.c | 55 +-
1 file changed, 48 insertions(+), 7 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-co
ng the IOC bit in
SST26* devices' config register if any block is protected by "sf protect
lock" command, thus enabling hardware write protection. this behavior is
similar to the "sf protect lock" implementation for Micron (and
compatible) chips.
Signed-off-by: Bernhard Kirchen
prior to using the WBPR (write block protection register) command to
write new block protection register values, the WREN command must be
sent. otherwise the new values are not applied.
Signed-off-by: Bernhard Kirchen
---
drivers/mtd/spi/spi-nor-core.c | 8
1 file changed, 8
properly indent the help text and use single quotes consistently to mark
variable parameters.
Signed-off-by: Bernhard Kirchen
---
cmd/sf.c | 48 ++--
1 file changed, 22 insertions(+), 26 deletions(-)
diff --git a/cmd/sf.c b/cmd/sf.c
index c0d6a8f8a0
works for Micron (and compatible) SPI NOR flash chips as
well as the SST26* series of SPI NOR flash chips.
the changes were tested on proprietary boards using a M25P16 and a
SST26VF016B.
Signed-off-by: Bernhard Kirchen
---
cmd/sf.c | 23 +++--
drivers/mtd/spi
relevant bits are set.
Signed-off-by: Bernhard Kirchen
---
drivers/mtd/spi/spi-nor-core.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index b3873aaf6e..0b48e068be 100644
--- a/drivers/mtd/spi/spi
works for Micron (and compatible) SPI NOR flash chips as
well as the SST26* series of SPI NOR flash chips.
the changes were tested on proprietary boards using a M25P16 and a
SST26VF016B.
Signed-off-by: Bernhard Kirchen
---
cmd/sf.c | 23 +++--
drivers/mtd/spi
relevant bits are set.
Signed-off-by: Bernhard Kirchen
---
drivers/mtd/spi/spi-nor-core.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index b3873aaf6e..0b48e068be 100644
--- a/drivers/mtd/spi/spi
it is not guaranteed that there is a human readable message when the
lock or unlock operation failed. make sure there is a message emitted
by the "sf protect" implementation if the subcommand failed.
Signed-off-by: Bernhard Kirchen
---
cmd/sf.c | 7 ++-
1 file changed, 6 insert
properly indent the help text and use single quotes consistently to mark
variable parameters.
Signed-off-by: Bernhard Kirchen
---
cmd/sf.c | 48 ++--
1 file changed, 22 insertions(+), 26 deletions(-)
diff --git a/cmd/sf.c b/cmd/sf.c
index c0d6a8f8a0
expectations.
Bernhard Kirchen (7):
command sf: help text format
sf protect: warn about failed (un)lock operation
SST26* locking: need to enable write
write WPEN bit for SST26* devices when locking
sf protect (un)lock for SST26*: test BPR values
fix sst26_process_bpr check
provide &qu
t asserted, as the respective registers are write-protected
in that case.
Signed-off-by: Bernhard Kirchen
---
drivers/mtd/spi/spi-nor-core.c | 55 +-
1 file changed, 48 insertions(+), 7 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-co
ng the IOC bit in
SST26* devices' config register if any block is protected by "sf protect
lock" command, thus enabling hardware write protection. this behavior is
similar to the "sf protect lock" implementation for Micron (and
compatible) chips.
Signed-off-by: Bernhard Kirchen
prior to using the WBPR (write block protection register) command to
write new block protection register values, the WREN command must be
sent. otherwise the new values are not applied.
Signed-off-by: Bernhard Kirchen
---
drivers/mtd/spi/spi-nor-core.c | 8
1 file changed, 8
ble memory.
By calling dram_init_banksize() from my board's am33xx_spl_board_init() I
can work around the issue.
However, I think that dram_init_banksize() should be called in
common/spl/spl.c:board_init_r() also if CONFIG_LBM is defined.
Best,
Bernhard
Add missing parameters to support full configuration of the latest FSP
MR6 release.
Signed-off-by: Bernhard Messerklinger
---
arch/x86/cpu/apollolake/fsp_bindings.c| 23 +++
.../asm/arch-apollolake/fsp/fsp_m_upd.h | 5 +++-
.../asm/arch-apollolake/fsp/fsp_s_upd.h
Add FSP_UINT64 read support as preparation for FSP-M and FSP-S parameter
update.
Signed-off-by: Bernhard Messerklinger
---
arch/x86/cpu/apollolake/fsp_bindings.c| 28 +++
.../asm/arch-apollolake/fsp_bindings.h| 1 +
2 files changed, 29 insertions(+)
diff --git
This patch set adds new paramters and functions to allow full
configuration of the latest FSP MR6 release.
Bernhard Messerklinger (2):
x86: apl: fsp_bindings: Add support for u64 parameters
arch: x86: apl: Update FSP parameters
arch/x86/cpu/apollolake/fsp_bindings.c| 51
A the moment the FSP-S configuration is a mix of hard coded values and
devicetree properties.
This patch makes FSP-S full configurable from devicetree by
adding binding properties for all FSP-S parameters.
Co-developed-by: Wolfgang Wallner
Signed-off-by: Wolfgang Wallner
Signed-off-by: Bernhard
A the moment the FSP-M configuration is a mix of hard coded values and
devicetree properties.
This patch makes FSP-M full configurable from devicetree by adding
binding properties for all FSP-M parameters.
Co-developed-by: Wolfgang Wallner
Signed-off-by: Wolfgang Wallner
Signed-off-by: Bernhard
Only load VBT if it's present in the u-boot.rom.
Signed-off-by: Bernhard Messerklinger
Reviewed-by: Simon Glass
Tested on coral:
Tested-by: Simon Glass
---
Changes in v4:
Fix comment alignment
Changes in v3: None
Changes in v2: None
arch/x86/cpu/apollolake/fsp_s.c | 46
into FSP-M and FSP-S
Fix #if defined macro for FSP-S path to reduce SPL size
Changes in v2:
Integration of the review comments
Fix swizzle size bug
Bernhard Messerklinger (3):
arch: x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabled
arch: x86: apl: Use devicetree for FSP-M configuration
macro for FSP-S path to reduce SPL size
Changes in v2:
Integration of the review comments
Fix swizzle size bug
Bernhard Messerklinger (3):
arch: x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabled
arch: x86: apl: Use devicetree for FSP-M configuration
arch: x86: apl: Use devicetree for
A the moment the FSP-M configuration is a mix of hard coded values and
devicetree properties.
This patch makes FSP-M full configurable from devicetree by adding
binding properties for all FSP-M parameters.
Co-developed-by: Wolfgang Wallner
Signed-off-by: Wolfgang Wallner
Signed-off-by: Bernhard
A the moment the FSP-S configuration is a mix of hard coded values and
devicetree properties.
This patch makes FSP-S full configurable from devicetree by
adding binding properties for all FSP-S parameters.
Co-developed-by: Wolfgang Wallner
Signed-off-by: Wolfgang Wallner
Signed-off-by: Bernhard
Only load VBT if it's present in the u-boot.rom.
Signed-off-by: Bernhard Messerklinger
---
Changes in v3: None
Changes in v2: None
arch/x86/cpu/apollolake/fsp_s.c | 46 ++---
1 file changed, 25 insertions(+), 21 deletions(-)
diff --git a/arch/x86/cpu/apollolake
-by: Bernhard Messerklinger
---
Changes in v2:
Integration of the review comments
Fix swizzle size bug
arch/x86/cpu/apollolake/Makefile |1 +
arch/x86/cpu/apollolake/fsp_bindings.c| 1803 +
arch/x86/cpu/apollolake/fsp_m.c | 169 +-
arch/x86/cpu
ructures
[1]: https://lists.denx.de/pipermail/u-boot/2020-April/405852.html
[2]: https://lists.denx.de/pipermail/u-boot/2020-April/406590.html
Changes in v2:
Integration of the review comments
Fix swizzle size bug
Bernhard Messerklinger (2):
arch: x86: apl: Only load VBT if CONFIG_HAVE_VBT is
Only load VBT if it's present in the u-boot.rom.
Signed-off-by: Bernhard Messerklinger
---
Changes in v2: None
arch/x86/cpu/apollolake/fsp_s.c | 46 ++---
1 file changed, 25 insertions(+), 21 deletions(-)
diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu
Hi Simon,
>Hi Bernhard,
>
>On Thu, 30 Apr 2020 at 03:16, Bernhard Messerklinger
> wrote:
>>
>> A the moment the FSP configuration is a mix of hard coded values
>and
>> devicetree properties.
>> This patch makes FSP-M and FSP-S full configurable from devi
Hi Simon,
>Hi Bernhard,
>
>On Thu, 30 Apr 2020 at 03:16, Bernhard Messerklinger
> wrote:
>>
>> Only load VBT if it's present in the u-boot.rom.
>>
>
>I think you can drop the RFC from this series. The approach seems
>good to me.
>
>Also, what APL boa
-by: Bernhard Messerklinger
---
arch/x86/cpu/apollolake/Makefile |1 +
arch/x86/cpu/apollolake/fsp_bindings.c| 2096 +
arch/x86/cpu/apollolake/fsp_m.c | 164 +-
arch/x86/cpu/apollolake/fsp_s.c | 382 +--
arch/x86/dts
Hi Bin, Simon,
>
>Move FSP-M configuration to the device-tree like it's already done
>for
>other SoCs (Baytrail).
>
>Signed-off-by: Bernhard Messerklinger
>
>---
>With this patch I moved the FSP-M configuration to the device-tree
>based
>on the Baytrail boa
eries.
This series is superseded by:
"Move FSP configuration to devicetree" [1]
[1]: https://lists.denx.de/pipermail/u-boot/2020-April/409505.html
>Changes in v2:
>Remove FSP-M binding file
>
>Bernhard Messerklinger (2):
> arch: x86: apl: Only load VBT if CONFIG_HAVE_V
ructures
[1]: https://lists.denx.de/pipermail/u-boot/2020-April/405852.html
[2]: https://lists.denx.de/pipermail/u-boot/2020-April/406590.html
Bernhard Messerklinger (2):
arch: x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabled
arch: x86: apl: Use devicetree for FSP configuration
arc
Only load VBT if it's present in the u-boot.rom.
Signed-off-by: Bernhard Messerklinger
---
arch/x86/cpu/apollolake/fsp_s.c | 18 --
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index 17cf1682ad
Hi Simon,
>
>Hi Bernhard,
>
>On Mon, 20 Apr 2020 at 07:11, Bernhard Messerklinger
> wrote:
>>
>> Hi Simon,
>>
>> >Hi Bernhard,
>> >
>> >On Tue, 14 Apr 2020 at 03:26, Bernhard Messerklinger
>> > wrote:
>> &
Hi Simon,
>Hi Bernhard,
>
>On Tue, 14 Apr 2020 at 03:26, Bernhard Messerklinger
> wrote:
>>
>> Move FSP-S configuration to the device-tree like it's already done
>for
>> other SoCs (Baytrail).
>>
>> Signed-off-by: Bernhard Messerklinger
>
>>
This patch series moves the configuration of FPS-S for Apollo Lake
based SoCs from the code to the device-tree.
This is similar to the previous patch series for FSP-M.
If wanted, I can also send FSP-M and FSP-S patch as a single series.
Changes in v2:
Remove FSP-M binding file
Bernhard
Move FSP-S configuration to the device-tree like it's already done for
other SoCs (Baytrail).
Signed-off-by: Bernhard Messerklinger
---
Changes in v2:
Remove FSP-M binding file
arch/x86/cpu/apollolake/fsp_s.c | 1070 +++--
arch/x86/dts/chromebook_coral.dts
Only load VBT if it's present in the u-boot.rom.
Signed-off-by: Bernhard Messerklinger
---
Changes in v2: None
arch/x86/cpu/apollolake/fsp_s.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
This patch series moves the configuration of FPS-S for Apollo Lake
based SoCs from the code to the device-tree.
This is similar to the previous patch series for FSP-M.
Bernhard Messerklinger (2):
arch: x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabled
arch: x86: apl: Read FSP-S
Move FSP-S configuration to the device-tree like it's already done for
other SoCs (Baytrail).
Signed-off-by: Bernhard Messerklinger
---
arch/x86/cpu/apollolake/fsp_s.c | 1070 +++--
arch/x86/dts/chromebook_coral.dts | 35 +-
.../asm/arch-apollolake/fsp
Only load VBT if it's present in the u-boot.rom.
Signed-off-by: Bernhard Messerklinger
---
arch/x86/cpu/apollolake/fsp_s.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index 1f22c1ea3c
Move FSP-M configuration to the device-tree like it's already done for
other SoCs (Baytrail).
Signed-off-by: Bernhard Messerklinger
---
With this patch I moved the FSP-M configuration to the device-tree based
on the Baytrail boards.
Changes in v3:
Added doc binding file
Added fspm prefix
Hi Bin,
>Hi Bernhard,
>
>On Mon, Mar 30, 2020 at 4:25 PM Bernhard Messerklinger
> wrote:
>>
>> Hi Bin,
>>
>> >Hi Bernhard,
>> >
>> >On Mon, Mar 30, 2020 at 3:35 PM Bernhard Messerklinger
>> > wrote:
>> >>
>>
Hi Bin,
>Hi Bernhard,
>
>On Mon, Mar 30, 2020 at 3:35 PM Bernhard Messerklinger
> wrote:
>>
>> Hi Simon, Bin,
>>
>> I am facing problems with the PCI enumeration at SPL loader stage.
>> On our HW we have PCIe x2 port connected to a FPGA. Since SPL does
olake/fsp-m.txt.
Sorry after some more detailed research I don't know if my first
understanding of binding file was right.
With binding file do you mean a header file for defines in
/include/dt-bindings or a documentation in doc/device-tree-bindings?
>>Is that ok for you?
>
>Do you also agree to change the fsp-s configuration in the same way?
Regards,
Bernhard
the pci_uclass.
Then we could also move the other apollolake specific things into this driver.
What do you think about this?
Do you have better/other ideas?
Regards,
Bernhard
ral:
>Tested-by: Simon Glass
>
>Do you think we should add a binding file for this though?
Yes, I will create v3 with a binding file in
doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt.
Is that ok for you?
Do you also agree to change the fsp-s configuration in the same way?
Regards,
Bernhard
Move FSP-M configuration to the device-tree like it's already done for
other SoCs (Baytaril).
Signed-off-by: Bernhard Messerklinger
---
With this patch I moved the fsp-m configuration to the device-tree based
on the baytrail boards.
I have tried to build it so that only entries that differ from
Move FSP-M configuration to the device-tree like it's already done for
other SoCs (Baytaril).
Signed-off-by: Bernhard Messerklinger
---
arch/x86/cpu/apollolake/fsp_m.c | 337 +++---
arch/x86/dts/chromebook_coral.dts | 35 ++
.../asm/arch-apollolake/fsp
Hello Vagrant
> I presume this is configs/Sinovoip_BPI_M3_defconfig ?
Yes. This is correct.
Best regards
Bernhard
signature.asc
Description: This is a digitally signed message part
-by: Bernhard Messerklinger
---
This patch is a revised version of the patch "arm: imx6: configure NoC on
i.MX6DQP" from the original author Filip Brozovic .
It takes care of the review notes for the original patch.
patchwork: https://patchwork.ozlabs.org/patch/670208/
mail-archive: https://lis
The i.MX6DP and i.MX6QP incorporate NoC interconnect logic
which needs to be configured in order to use external DDR memory.
This patch enables the SPL to configure the necessary registers
in accordance with the NXP engineering bulletin EB828.
Signed-off-by: Bernhard Messerklinger
The i.MX6DP and i.MX6QP incorporate NoC interconnect logic
which needs to be configured in order to use external DDR memory.
This patch enables the SPL to configure the necessary registers
in accordance with the NXP engineering bulletin EB828.
Signed-off-by: Bernhard Messerklinger
t; With this patch my i.MX6QP DDR3 NoC configuration works fine.
>
> What is the current state of the patch?
> Is anyone still working on it?
> If no, what would I have to do to get it mainline?
>
> Regards,
> Bernhard
Hi Stefano, Filip,
I am still looking for feedback
is the current state of the patch?
Is anyone still working on it?
If no, what would I have to do to get it mainline?
Regards,
Bernhard
With the introduction of the new spi-mem model operations changed
slightly. The new spi-mem operations make things a bit easier to
handle for ich-spi flash interface. This patch converts the ich-spi
driver by using spi-mem operations.
Signed-off-by: Bernhard Messerklinger
---
Changes in v4
message a little bit
Changes in v3:
- update erase op code handling to work with latest master
spi-nor driver
Signed-off-by: Bernhard Messerklinger
---
drivers/spi/ich.c | 267 +-
drivers/spi/ich.h | 9 +-
2 files changed, 100 insertions(+), 176
Hello Bin,
> Von: "Bin Meng"
> An: "Simon Glass" , "Bernhard Messerklinger"
> , "Vignesh Raghavendra"
> , "U-Boot Mailing List"
> Kopie: "Bernhard Messerklinger"
> Datum: 07/28/2019 01:31 PM
> Betreff: [PATCH
With the introduction of the new spi-mem model operations changed
slightly, which broke the ich-spi driver. The new spi-mem operations
make things a bit easier to handle for ich flash interface. This patch
makes ich-spi work again by using spi-mem operations.
Signed-off-by: Bernhard Messerklinger
Add check if exec_op is set before calling it.
At the moment it is called unconditionally, which leads to a crash if it
is not set correctly.
Signed-off-by: Bernhard Messerklinger
---
drivers/spi/spi-mem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/spi
Reviewed-by: Bernhard Messerklinger
Tested-by: Bernhard Messerklinger
Von:Anssi Hannula
An: u-boot@lists.denx.de, Bernhard Messerklinger
Kopie: Hannes Schmelzer
Datum: 02/27/2019 11:56 AM
Betreff:[PATCH v2] fs: fat: fix reading non-cluster-aligned root
directory
Add native tsc calibration function. Calibrate the tsc timer the same
way as linux does in arch/x86/kernel/tsc.c.
Fixes booting for Apollo Lake processors.
Signed-off-by: Bernhard Messerklinger
---
I hope this patch won't break other x86 board.
I only can test it with APL board.
Changes in v4
Add native tsc calibration function. Calibrate the tsc timer the same
way as linux does arch/x86/kernel/tsc.c.
Fixes booting for Apollo Lake processors.
Signed-off-by: Bernhard Messerklinger
---
I hope this patch won't break other x86 board.
I only can test it with APL board.
Changes in v1
6_model == INTEL_FAM6_ATOM_GOLDMONT)
> > > > setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
> > > > ...
> > > > }
> > > >
> > > > So, that's what we need to do in U-boot.
> > > >
> > >
> > > Thanks for the invest
Hi Andy,
> Von: Bin Meng
> An: Andy Shevchenko ,
> Kopie: Bernhard Messerklinger automation.com>, U-Boot Mailing List
> Datum: 25.11.2018 15:50
> Betreff: Re: [U-Boot] [PATCH] x86: tsc: Add support for APL soc
>
> Hi Andy,
>
> On Sun, Nov 25, 2018 at 10:
Hi Bin,
> Missing commit message
I will fix this.
>
> APL means ApolloLake? Could you please spell it out?
I will fix this.
>
> > Signed-off-by: Bernhard Messerklinger automation.com>
> > ---
> >
> > drivers/timer/tsc_timer.c | 2 ++
> > 1 fil
mydata->clust_size));
}
mydata->fatbufnum = -1;
After patch:
sect_to_clust: 0xfff0 = (0x112 - 132) / 2
sect_to_clust: 112 = 132 + 0xfff0 * 2
Can you verify this?
If yes? Is it maybe possible to add this to your p
> Von: Bernhard Messerklinger/Eggelsberg/AT/B
> An: Jagan Teki ,
> Kopie: Jagan Teki , U-Boot-Denx
> Datum: 04.09.2018 10:54
> Betreff: Antwort: Re: [U-Boot] [PATCH] spi: mxc_spi: Fix chipselect
> with DM_SPI in SPL
>
> Hi Jagan,
>
> it's not about any size con
Signed-off-by: Bernhard Messerklinger
---
drivers/timer/tsc_timer.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
index da7c812908..b2a982812a 100644
--- a/drivers/timer/tsc_timer.c
+++ b/drivers/timer/tsc_timer.c
@@ -64,6 +64,8
Signed-off-by: Bernhard Messerklinger
---
drivers/spi/ich.c | 7 +++
drivers/spi/ich.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index d84bbdb2e5..4ec107d323 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -213,6 +213,10 @@ static
Signed-off-by: Bernhard Messerklinger
---
drivers/spi/ich.c | 168 +-
drivers/spi/ich.h | 46 -
2 files changed, 178 insertions(+), 36 deletions(-)
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 03531a8c0c..d84bbdb2e5 100644
with CONFIG_DM_SPI.
Would you prefer to add CONFIG_SPL_DM_SPI as configuration parameter?
Bernhard
Von:Jagan Teki
An: Bernhard Messerklinger ,
Kopie: U-Boot-Denx , Jagan Teki
Datum: 03.09.2018 18:33
Betreff:Re: [U-Boot] [PATCH] spi: mxc_spi: Fix chipselect with
DM_SPI in SPL
On Mon
Since CONFIG_IS_ENABLED(DM_SPI) is not working in SPL because
CONFIG_SPL_DM_SPI is not defined we should go with #ifdef CONFIG_DM_SPI.
Signed-off-by: Bernhard Messerklinger
---
drivers/spi/mxc_spi.c | 28
1 file changed, 16 insertions(+), 12 deletions(-)
diff
Signed-off-by: Bernhard Messerklinger
---
drivers/serial/serial_mxc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index 4f1f822c58..e586c18cf0 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -339,6
.
Regards,
Bernhard
On Thu, Mar 22, 2018 at 10:06 AM, Bin Meng <bmeng...@gmail.com> wrote:
> Hi,
>
> On Thu, Feb 15, 2018 at 3:59 PM, Bernhard Messerklinger
> <bernhard.messerklin...@br-automation.com> wrote:
>> Since memory banks may not be located behind each other we
Use dm_pci_map_bar function for BAR mapping. This has the advantage
of clearing BAR flags and and only accepting mapped memory.
Signed-off-by: Bernhard Messerklinger <bernhard.messerklin...@br-automation.com>
---
drivers/mmc/pci_mmc.c | 5 ++---
1 file changed, 2 insertions(+), 3 del
Do a explicit check for CONFIG_SYS_BIG_ENDIAN and
CONFIG_SYS_LITTLE_ENDIAN to avoid errors on platforms where both
are undefined (x86).
Signed-off-by: Bernhard Messerklinger <bernhard.messerklin...@br-automation.com>
---
drivers/serial/ns16550.c | 4 ++--
1 file changed, 2 insertions
Since memory banks may not be located behind each other we need to add
them separately.
Signed-off-by: Bernhard Messerklinger <bernhard.messerklin...@br-automation.com>
---
drivers/pci/pci-uclass.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drive
Fix commit f1bcad22dd19 ("net: e1000: add support for writing to
EEPROM").
Signed-off-by: Bernhard Messerklinger <bernhard.messerklin...@br-automation.com>
---
drivers/net/e1000.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/e1000.c b/drivers/n
ed address).
To avoid this we tell the compiler to always align this scratchpad to a
word aligned address.
Signed-off-by: Bernhard Messerklinger <bernhard.messerklin...@br-automation.com>
---
cmd/fdt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/cmd/fdt.c b/cmd/fdt.c
ORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS0
/* USB Ethernet Configs */
#define CONFIG_USBD_HS
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_CDC
#define CONFIG_USBNET_DEV_ADDR "de:ad:be:ef:00:01"
#define CONFIG_USBNET_HOST_ADDR "de:ad:be:ef:00:
Side note:
Am 19.12.2016 um 16:22 schrieb Icenowy Zheng:
[...]
According to some facts:
- The register based access to SID is weird: it needs ~5 register
operations per word of SID.
[...]
My experiments seem to indicate that Allwinner's implementation might be
overly complicated. I have
Hi all!
This is rather interesting stuff. Actually it's possible to find partial
documentation for this method (of reading SID/efuse values) even for older
SoCs. There's an early version of the A20 User Manual (Revision 1.0 -
Feb. 18, 2013) available on the net, where chapter 1.18 describes the
Hi Joe!
Thanks for chiming in, especially seeing that you have previously worked
on something very similar.
Am 27.11.2016 um 19:53 schrieb Joe Hershberger:
On Wed, Nov 16, 2016 at 4:29 AM, Bernhard Nortmann
<bernhard.nortm...@web.de> wrote:
"transient" (='t') is like &qu
Hi Simon,
Am 23.11.2016 um 00:08 schrieb Simon Glass:
Hi Bernhard,
[...]
Well you could add a separate patch before this one which renames
everything. I don't think anyone else is working in this area.
Regards,
Simon
Doing so, I have arrived at the (additional) commit attached below
Hi Simon!
Am 19.11.2016 um 14:47 schrieb Simon Glass:
Hi Bernhard,
On 16 November 2016 at 03:30, Bernhard Nortmann
<bernhard.nortm...@web.de> wrote:
This is an attempt to prevent such information from ending up
in exported environment data, especially when doing "save
Hi Simon!
Am 19.11.2016 um 14:47 schrieb Simon Glass:
Hi Bernhard,
On 16 November 2016 at 03:30, Bernhard Nortmann
<bernhard.nortm...@web.de> wrote:
Like setenv(), but automatically marks the entry as "don't export".
Signed-off-by: Bernhard Nortmann <bernhard.nortm...@w
Hi Simon!
Am 19.11.2016 um 14:47 schrieb Simon Glass:
Hi Bernhard,
On 16 November 2016 at 03:29, Bernhard Nortmann
<bernhard.nortm...@web.de> wrote:
"transient" (='t') is like "any", but requests that a variable
should not be exported (ENV_FLAGS_VARACCESS_PREVE
031.html
Regards, B. Nortmann
Changes in v2:
- Add "Reviewed-by" sjg
- Removed too narrow (flag & H_FORCE) expression, use "flag" directly
- Fixed outdated "env_flags_varaccess_lock" to the correct
"env_flags_varaccess_system"
Bernhard Nortmann (7):
1 - 100 of 215 matches
Mail list logo
