[U-Boot] [PATCH] arm: socfpga: gen5: Enabling cache and TLB maintenance broadcast

From: Chin Liang See <chin.liang@intel.com> Enabling cache and TLB maintenance broadcast through ACTLR as required by Linux. Signed-off-by: Chin Liang See <chin.liang@intel.com> --- arch/arm/mach-socfpga/misc_gen5.c | 11 ++- 1 file changed, 10 insertions(+), 1 delet

[U-Boot] [PATCH v2] arm: socfpga: cyclone5: Enable Macronix flash support

From: Chin Liang See <chin.liang@intel.com> Enable Macronix flash support for Cyclone5 SoC Signed-off-by: Chin Liang See <chin.liang@intel.com> --- Changes for v2 - Undo change for is1, sr1500 and vining --- configs/socfpga_cyclone5_defconfig | 1 + configs/socfpga_sock

[U-Boot] [PATCH 2/2] arm: socfpga: cyclone5: Ensure spi-flash in the compatible string

From: Chin Liang See <chin.liang@intel.com> Ensure "spi-flash" is added into compatible string when there is NOR flash being instantiated in DTS. Discovered "sf probe" command without argument would hit error if spi-flash compatible string is missing. Sig

[U-Boot] [PATCH 1/2] arm: socfpga: cyclone5: Enable Macronix flash support

From: Chin Liang See <chin.liang@intel.com> Enable Macronix flash support for Cyclone5 SoC Signed-off-by: Chin Liang See <chin.liang@intel.com> --- configs/socfpga_cyclone5_defconfig| 1 + configs/socfpga_is1_defconfig | 1 + configs/socfpga_sockit_defcon

[U-Boot] [PATCH v2 10/14] arm: socfpga: stratix10: Add SPL driver for Stratix10 SoC

From: Chin Liang See <chin.liang@intel.com> Add SPL driver support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang@intel.com> --- arch/arm/mach-socfpga/Makefile| 4 + arch/arm/mach-socfpga/include/mach/firewall_s10.h | 84 + a

[U-Boot] [PATCH v2 07/14] arm: socfpga: stratix10: Add MMU support for Stratix10 SoC

From: Chin Liang See <chin.liang@intel.com> Add MMU support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang@intel.com> --- arch/arm/mach-socfpga/Makefile| 1 + arch/arm/mach-socfpga/mmu-arm64_s10.c | 71 +++ 2 files

[U-Boot] [PATCH v2 11/14] arm: socfpga: stratix10: Add timer support for Stratix10 SoC

From: Chin Liang See <chin.liang@intel.com> Add timer support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang@intel.com> --- arch/arm/mach-socfpga/timer.c | 17 - 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/ti

[U-Boot] [PATCH v2 09/14] arm: socfpga: Restructure the SPL file

From: Chin Liang See <chin.liang@intel.com> Restructure the SPL so each devices such as CV, A10 and S10 will have their own dedicated SPL file. SPL file determine the HW initialization flow which is device specific Signed-off-by: Chin Liang See <chin.liang@intel.com> --- a

[U-Boot] [PATCH v2 14/14] arm: socfpga: stratix10: Enable Stratix10 SoC build

From: Chin Liang See <chin.liang@intel.com> Add build support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang@intel.com> --- arch/arm/Kconfig | 8 +- arch/arm/mach-socfpga/Kconfig | 13 ++ configs/socfpga_stratix10_defconfig

[U-Boot] [PATCH v2 13/14] board: altera: stratix10: Add socdk board support for Stratix10 SoC

From: Chin Liang See <chin.liang@intel.com> Add socdk board support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang@intel.com> --- board/altera/stratix10-socdk/MAINTAINERS | 7 +++ board/altera/stratix10-socdk/Makefile| 7 +++ board/altera/stratix10-soc

[U-Boot] [PATCH v2 08/14] arm: dts: Add dts for Stratix10 SoC

From: Chin Liang See <chin.liang@intel.com> Device tree for Stratix10 SoC Signed-off-by: Chin Liang See <chin.liang@intel.com> --- arch/arm/dts/Makefile| 3 +- arch/arm/dts/socfpga_stratix10_socdk.dts | 180 +++ 2 files

[U-Boot] [PATCH v2 12/14] ddr: altera: stratix10: Add DDR support for Stratix10 SoC

From: Chin Liang See <chin.liang@intel.com> Add DDR support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang@intel.com> --- arch/arm/mach-socfpga/include/mach/sdram_s10.h | 333 + drivers/ddr/altera/Makefile| 1 + driver

[U-Boot] [PATCH v2 04/14] arm: socfpga: stratix10: Add pinmux support for Stratix10 SoC

From: Chin Liang See <chin.liang@intel.com> Add pinmux driver support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang@intel.com> --- arch/arm/mach-socfpga/Makefile | 2 + .../arm/mach-socfpga/include/mach/system_manager.h | 5 +- .../

[U-Boot] [PATCH v2 03/14] arm: socfpga: stratix10: Add Reset Manager driver for Stratix10 SoC

From: Chin Liang See <chin.liang@intel.com> Add Reset Manager driver support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang@intel.com> --- arch/arm/mach-socfpga/Makefile | 1 + arch/arm/mach-socfpga/include/mach/reset_manager.h | 2 + .../

[U-Boot] [PATCH v2 02/14] arm: socfpga: stratix10: Add Clock Manager driver for Stratix10 SoC

From: Chin Liang See <chin.liang@intel.com> Add Clock Manager driver support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang@intel.com> -- Changes in v2 - Declared defines for constant value used - Fixed spacing and comments --- arch/arm/mach-socf

[U-Boot] [PATCH v2 05/14] arm: socfpga: stratix10: Add misc support for Stratix10 SoC

From: Chin Liang See <chin.liang@intel.com> Add misc support such as EMAC and cpu info printout for Stratix SoC Signed-off-by: Chin Liang See <chin.liang@intel.com> --- arch/arm/mach-socfpga/Makefile| 1 + arch/arm/mach-socfpga/include/mach/misc.h | 1 + a

[U-Boot] [PATCH v2 01/14] arm: socfpga: stratix10: Add base address map for Statix10 SoC

From: Chin Liang See <chin.liang@intel.com> Add the base address map for Statix10 SoC Signed-off-by: Chin Liang See <chin.liang@intel.com> --- arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 56 ++ 1 file changed, 56 insertions(+) create mode 100

[U-Boot] [PATCH v2 00/14] Enable Stratix10 SoC support

From: Chin Liang See <chin.liang@intel.com> This patch series are enabling support for Stratix 10 SoC Changes for v2 - Removed defines for base addresses that can be extracted from DTS - Added CPU node plus MDIO node for Ethernet at DTS - Added defines for constant value for reada

[U-Boot] [PATCH 11/14] arm: socfpga: stratix10: Add timer support for Stratix10 SoC

From: Chin Liang See <chin.liang@intel.com> Add timer support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang@intel.com> --- arch/arm/mach-socfpga/timer.c | 17 - 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/ti

[U-Boot] [PATCH 07/14] arm: socfpga: stratix10: Add mailbox support for Stratix10 SoC

From: Chin Liang See <chin.liang@intel.com> Add mailbox support for Stratix SoC Signed-off-by: Ley Foon Tan <ley.foon@intel.com> Signed-off-by: Chin Liang See <chin.liang@intel.com> --- arch/arm/mach-socfpga/Makefile | 1 + arch/arm/mach-so

[U-Boot] [PATCH 12/14] ddr: altera: stratix10: Add DDR support for Stratix10 SoC

From: Chin Liang See <chin.liang@intel.com> Add DDR support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang@intel.com> --- arch/arm/mach-socfpga/include/mach/sdram_s10.h | 333 + drivers/ddr/altera/Makefile| 1 + driver

[U-Boot] [PATCH 09/14] arm: socfpga: Restructure the SPL file

From: Chin Liang See <chin.liang@intel.com> Restructure the SPL so each devices such as CV, A10 and S10 will have their own dedicated SPL file. SPL file determine the HW initialization flow which is device specific Signed-off-by: Chin Liang See <chin.liang@intel.com> --- a

[U-Boot] [PATCH 05/14] arm: socfpga: stratix10: Add pinmux support for Stratix10 SoC

From: Chin Liang See <chin.liang@intel.com> Add pinmux driver support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang@intel.com> --- arch/arm/mach-socfpga/Makefile | 2 + .../arm/mach-socfpga/include/mach/system_manager.h | 5 +- .../

[U-Boot] [PATCH 08/14] arm: socfpga: stratix10: Add MMU support for Stratix10 SoC

From: Chin Liang See <chin.liang@intel.com> Add MMU support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang@intel.com> --- arch/arm/mach-socfpga/Makefile| 1 + arch/arm/mach-socfpga/mmu-arm64_s10.c | 71 +++ 2 files

[U-Boot] [PATCH 13/14] board: altera: stratix10: Add socdk board support for Stratix10 SoC

From: Chin Liang See <chin.liang@intel.com> Add socdk board support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang@intel.com> --- board/altera/stratix10-socdk/MAINTAINERS | 7 +++ board/altera/stratix10-socdk/Makefile| 7 +++ board/altera/stratix10-soc

[U-Boot] [PATCH 03/14] arm: socfpga: stratix10: Add Clock Manager driver for Stratix10 SoC

From: Chin Liang See <chin.liang@intel.com> Add Clock Manager driver support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang@intel.com> --- arch/arm/mach-socfpga/Makefile | 4 + arch/arm/mach-socfpga/clock_manager.c | 4 +- a

[U-Boot] [PATCH 10/14] arm: socfpga: stratix10: Add SPL driver for Stratix10 SoC

From: Chin Liang See <chin.liang@intel.com> Add SPL driver support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang@intel.com> --- arch/arm/mach-socfpga/Makefile | 4 + arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 4 + arch/arm/

[U-Boot] [PATCH 14/14] arm: socfpga: stratix10: Enable Stratix10 SoC build

From: Chin Liang See <chin.liang@intel.com> Add build support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang@intel.com> --- arch/arm/Kconfig | 8 +- arch/arm/mach-socfpga/Kconfig | 13 ++ configs/socfpga_stratix10_defconfig

[U-Boot] [PATCH 06/14] arm: socfpga: stratix10: Add misc support for Stratix10 SoC

From: Chin Liang See <chin.liang@intel.com> Add misc support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang@intel.com> --- arch/arm/mach-socfpga/Makefile | 1 + arch/arm/mach-socfpga/misc.c | 4 + arch/arm/mach-socfpga/misc

[U-Boot] [PATCH 04/14] arm: socfpga: stratix10: Add Reset Manager driver for Stratix10 SoC

From: Chin Liang See <chin.liang@intel.com> Add Reset Manager driver support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang@intel.com> --- arch/arm/mach-socfpga/Makefile | 1 + arch/arm/mach-socfpga/include/mach/reset_manager.h | 2 + .../

[U-Boot] [PATCH 02/14] arm: dts: Add dts for Stratix10 SoC

From: Chin Liang See <chin.liang@intel.com> Device tree for Stratix10 SoC Signed-off-by: Chin Liang See <chin.liang@intel.com> --- arch/arm/dts/Makefile| 3 +- arch/arm/dts/socfpga_stratix10_socdk.dts | 141 +++ 2 files

[U-Boot] [PATCH 01/14] arm: socfpga: stratix10: Add base address map for Statix10 SoC

From: Chin Liang See <chin.liang@intel.com> Add the base address map for Statix10 SoC Signed-off-by: Chin Liang See <chin.liang@intel.com> --- arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 58 ++ 1 file changed, 58 insertions(+) create mode 100

[U-Boot] [PATCH 00/14] Enable Stratix10 SoC support

From: Chin Liang See <chin.liang@intel.com> This patch series are enabling support for Stratix 10 SoC Chin Liang See (14): arm: socfpga: stratix10: Add base address map for Statix10 SoC arm: dts: Add dts for Stratix10 SoC arm: socfpga: stratix10: Add Clock Manager driver for Str

Re: [U-Boot] [PATCH v2] arm: socfpga: fix issue with warm reset when CSEL is 0

e/mach/system_manager.h |  7 ++- >  arch/arm/mach-socfpga/misc.c   | 27 >  arch/arm/mach-socfpga/reset_clock_manager.S| 71 > ++ >  6 files changed, 134 insertions(+), 3 deletions(-) >  create mode 100644 arch/arm/mach-s

Re: [U-Boot] [PATCH v2] spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible

On Sel, 2016-11-29 at 10:55 +0530, Vignesh R wrote: > > On Monday 28 November 2016 07:45 PM, See, Chin Liang wrote: > > > > On Jum, 2016-11-25 at 17:51 +0100, Marek Vasut wrote: > > > > > > On 11/24/2016 06:35 AM, Vignesh R wrote: > > > > > > > > > > > > According to Section 11.15.4.9.2

Re: [U-Boot] Macronix NOR_SPI and Quad I/O

On Sab, 2016-11-26 at 08:43 +0530, Jagan Teki wrote: > On Fri, Nov 25, 2016 at 10:07 PM, Champ, Andy > wrote: > > > > Hi all, > > > > > > in the table in drivers/mtd/spi/spi_flash_ids.c there is a flag > > WR_QPP set against Macronix devices (including the ones Dumitru

Re: [U-Boot] [PATCH] ARM: socfpga: Add boot0 hook to prevent SPL corruption

de at 0x004c or > > > 0x0050 , at which point the value of r0 and r1 registers is > > > undefined. Moreover, jumping directly to the preloader entry > > > point > > > at address 0x will also fail, because address 0xffff004. > > > is in

Re: [U-Boot] [PATCH v3 04/12] arm: socfpga: clkmgr: Separate the Clock Manager for Stratix 10

On Sel, 2016-10-18 at 06:00 +0200, Marek Vasut wrote: > On 10/18/2016 05:22 AM, Chin Liang See wrote: > > > > On Sen, 2016-10-17 at 18:14 +0200, Marek Vasut wrote: > > > > > > On 10/17/2016 05:59 PM, Chin Liang See wrote: > > > > > > > >

Re: [U-Boot] [PATCH v3 04/12] arm: socfpga: clkmgr: Separate the Clock Manager for Stratix 10

On Sen, 2016-10-17 at 18:14 +0200, Marek Vasut wrote: > On 10/17/2016 05:59 PM, Chin Liang See wrote: > > > > On Sen, 2016-10-17 at 17:39 +0200, Marek Vasut wrote: > > > > > > On 10/17/2016 05:28 PM, Chin Liang See wrote: > > > > > > > >

Re: [U-Boot] [PATCH v3 05/12] arm: socfpga: fpgamgr: Disable FPGA Manager for Stratix 10

On Sen, 2016-10-17 at 15:42 +0200, Marek Vasut wrote: > On 10/17/2016 03:35 PM, See, Chin Liang wrote: > > > > On Min, 2016-10-16 at 17:34 +0200, Marek Vasut wrote: > > > > > > On 10/13/2016 10:33 AM, Chin Liang See wrote: > > > > > > >

Re: [U-Boot] [PATCH v3 09/12] arm: socfpga: stratix10: Add board directory for Stratix 10 socdk

On Min, 2016-10-16 at 17:39 +0200, Marek Vasut wrote: > On 10/13/2016 10:33 AM, Chin Liang See wrote: > > > > Add board folder > directory > Will fix this. > > > > for Stratix 10 SoC development kit > > > > Signed-off-by: Chin Liang See <cl..

Re: [U-Boot] [PATCH v3 04/12] arm: socfpga: clkmgr: Separate the Clock Manager for Stratix 10

On Sen, 2016-10-17 at 17:39 +0200, Marek Vasut wrote: > On 10/17/2016 05:28 PM, Chin Liang See wrote: > > > > On Sen, 2016-10-17 at 17:20 +0200, Marek Vasut wrote: > > > > > > On 10/17/2016 05:07 PM, Chin Liang See wrote: > > > > > > > >

Re: [U-Boot] [PATCH v3 11/12] arm: socfpga: Add SPL support for Stratix 10 SoC

On Min, 2016-10-16 at 17:41 +0200, Marek Vasut wrote: > On 10/13/2016 10:33 AM, Chin Liang See wrote: > > > > Add SPL support for Stratix 10 SoC development kit > > > > Signed-off-by: Chin Liang See <cl...@altera.com> > > Cc: Marek Vasut <

Re: [U-Boot] [PATCH v3 05/12] arm: socfpga: fpgamgr: Disable FPGA Manager for Stratix 10

On Sen, 2016-10-17 at 17:20 +0200, Marek Vasut wrote: > On 10/17/2016 05:14 PM, Chin Liang See wrote: > > > > On Sen, 2016-10-17 at 15:42 +0200, Marek Vasut wrote: > > > > > > On 10/17/2016 03:35 PM, See, Chin Liang wrote: > > > > > > > >

Re: [U-Boot] [PATCH v3 01/12] arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address

On Sen, 2016-10-17 at 15:40 +0200, Marek Vasut wrote: > On 10/17/2016 03:26 PM, See, Chin Liang wrote: > > > > On Min, 2016-10-16 at 17:31 +0200, Marek Vasut wrote: > > > > > > On 10/13/2016 10:32 AM, Chin Liang See wrote: > > > > > > > >

Re: [U-Boot] [PATCH v3 04/12] arm: socfpga: clkmgr: Separate the Clock Manager for Stratix 10

On Sen, 2016-10-17 at 17:20 +0200, Marek Vasut wrote: > On 10/17/2016 05:07 PM, Chin Liang See wrote: > > > > On Sen, 2016-10-17 at 15:42 +0200, Marek Vasut wrote: > > > > > > On 10/17/2016 03:32 PM, See, Chin Liang wrote: > > > > > > > >

Re: [U-Boot] [PATCH v3 07/12] arm: socfpga: sysmgr: Disable System Manager for Stratix 10

On Min, 2016-10-16 at 17:38 +0200, Marek Vasut wrote: > On 10/13/2016 10:33 AM, Chin Liang See wrote: > > > > Disable the System Manager for Stratix 10 SoC as we are not > > using this for SOCVP > So I wonder, shouldn't we introduce some bool Kconfig e

Re: [U-Boot] [PATCH v3 04/12] arm: socfpga: clkmgr: Separate the Clock Manager for Stratix 10

On Sen, 2016-10-17 at 15:42 +0200, Marek Vasut wrote: > On 10/17/2016 03:32 PM, See, Chin Liang wrote: > > > > On Min, 2016-10-16 at 17:33 +0200, Marek Vasut wrote: > > > > > > On 10/13/2016 10:33 AM, Chin Liang See wrote: > > > > > > > >

[U-Boot] [PATCH v3 09/12] arm: socfpga: stratix10: Add board directory for Stratix 10 socdk

Add board folder for Stratix 10 SoC development kit Signed-off-by: Chin Liang See <cl...@altera.com> Cc: Marek Vasut <ma...@denx.de> Cc: Dinh Nguyen <dingu...@opensource.altera.com> Cc: Ley Foon Tan <lf...@altera.com> Cc: Tien Fong Chee <tfc...@altera.com> ---

[U-Boot] [PATCH v3 10/12] arm: dts: socfpga: Add dts for Stratix 10 socdk

Add device tree for Stratix 10 SoC development kit Signed-off-by: Chin Liang See <cl...@altera.com> Cc: Marek Vasut <ma...@denx.de> Cc: Dinh Nguyen <dingu...@opensource.altera.com> Cc: Ley Foon Tan <lf...@altera.com> Cc: Tien Fong Chee <tfc...@altera.com> Acked-

[U-Boot] [PATCH v3 12/12] arm: socfpga: Add support for Stratix 10 SoC dev kit

Add support for Stratix 10 SoC development kit Signed-off-by: Chin Liang See <cl...@altera.com> Cc: Marek Vasut <ma...@denx.de> Cc: Dinh Nguyen <dingu...@opensource.altera.com> Cc: Ley Foon Tan <lf...@altera.com> Cc: Tien Fong Chee <tfc...@altera

[U-Boot] [PATCH v3 07/12] arm: socfpga: sysmgr: Disable System Manager for Stratix 10

Disable the System Manager for Stratix 10 SoC as we are not using this for SOCVP Signed-off-by: Chin Liang See <cl...@altera.com> Cc: Marek Vasut <ma...@denx.de> Cc: Dinh Nguyen <dingu...@opensource.altera.com> Cc: Ley Foon Tan <lf...@altera.com> Cc: Tien Fong Chee <t

[U-Boot] [PATCH v3 11/12] arm: socfpga: Add SPL support for Stratix 10 SoC

Add SPL support for Stratix 10 SoC development kit Signed-off-by: Chin Liang See <cl...@altera.com> Cc: Marek Vasut <ma...@denx.de> Cc: Dinh Nguyen <dingu...@opensource.altera.com> Cc: Ley Foon Tan <lf...@altera.com> Cc: Tien Fong Chee <tfc...@altera.com> --- arch/

[U-Boot] [PATCH v3 06/12] arm: socfpga: misc: Separate the misc.c for Stratix 10

Separate the misc.c to support both GEN5 SoC and Stratix 10 SoC. Signed-off-by: Chin Liang See <cl...@altera.com> Cc: Marek Vasut <ma...@denx.de> Cc: Dinh Nguyen <dingu...@opensource.altera.com> Cc: Ley Foon Tan <lf...@altera.com> Cc: Tien Fong Chee <tfc...@altera.com&

[U-Boot] [PATCH v3 03/12] arm: socfpga: rstmgr: Separate the Reset Manager for Stratix 10

Separate the Reset Manager to support both GEN5 SoC and Stratix 10 SoC. Signed-off-by: Chin Liang See <cl...@altera.com> Cc: Marek Vasut <ma...@denx.de> Cc: Dinh Nguyen <dingu...@opensource.altera.com> Cc: Ley Foon Tan <lf...@altera.com> Cc: Tien Fong Chee <tfc...@

[U-Boot] [PATCH v3 05/12] arm: socfpga: fpgamgr: Disable FPGA Manager for Stratix 10

Disable the FPGA Manager for Stratix 10 SoC as we are not using this for SOCVP Signed-off-by: Chin Liang See <cl...@altera.com> Cc: Marek Vasut <ma...@denx.de> Cc: Dinh Nguyen <dingu...@opensource.altera.com> Cc: Ley Foon Tan <lf...@altera.com> Cc: Tien Fong Chee <tfc..

[U-Boot] [PATCH v3 08/12] arm: socfpga: mmu: Add memory map layout for Stratix 10 SoC

Add memory map layout for Stratix 10 SoC Signed-off-by: Chin Liang See <cl...@altera.com> Cc: Marek Vasut <ma...@denx.de> Cc: Dinh Nguyen <dingu...@opensource.altera.com> Cc: Ley Foon Tan <lf...@altera.com> Cc: Tien Fong Chee <tfc...@altera.com> --- arch/arm

[U-Boot] [PATCH v3 00/12] Add support for Stratix 10 SoC

Add support for Stratix 10 SoC which is ARM64 based. This series of patches are tested with Stratix 10 SOC Virtual Platform that is available today. Signed-off-by: Chin Liang See <cl...@altera.com> Cc: Marek Vasut <ma...@denx.de> Cc: Dinh Nguyen <dingu...@opensource.altera.com>

[U-Boot] [PATCH v3 04/12] arm: socfpga: clkmgr: Separate the Clock Manager for Stratix 10

Separate the Clock Manager to support both GEN5 SoC and Stratix 10 SoC. Signed-off-by: Chin Liang See <cl...@altera.com> Cc: Marek Vasut <ma...@denx.de> Cc: Dinh Nguyen <dingu...@opensource.altera.com> Cc: Ley Foon Tan <lf...@altera.com> Cc: Tien Fong Chee <tfc...@alt

[U-Boot] [PATCH v3 01/12] arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address

Add base address header file for Stratix10 SoC Signed-off-by: Chin Liang See <cl...@altera.com> Cc: Marek Vasut <ma...@denx.de> Cc: Dinh Nguyen <dingu...@opensource.altera.com> Cc: Ley Foon Tan <lf...@altera.com> Cc: Tien Fong Chee <tfc...@altera.com> Acked-

[U-Boot] [PATCH v3 02/12] arm: socfpga: rstmgr: Add Reset Manager for Stratix 10

Add Reset Manager registers structure for Stratix 10 SoC Signed-off-by: Chin Liang See <cl...@altera.com> Cc: Marek Vasut <ma...@denx.de> Cc: Dinh Nguyen <dingu...@opensource.altera.com> Cc: Ley Foon Tan <lf...@altera.com> Cc: Tien Fong Chee <tfc...@altera.com

[U-Boot] [PATCH v3 00/12] Add support for Stratix 10 SoC

Add support for Stratix 10 SoC which is ARM64 based. This series of patches are tested with Stratix 10 SOC Virtual Platform that is available today. Signed-off-by: Chin Liang See <cl...@altera.com> Cc: Marek Vasut <ma...@denx.de> Cc: Dinh Nguyen <dingu...@opensource.altera.com>

Re: [U-Boot] [RFC 4/4] arm: socfpga: scrub the SDRAM to properly enable ECC support

On Mon, 2016-10-10 at 10:52 -0500, Dinh Nguyen wrote: > From: Dinh Nguyen > > In order for SDRAM ECC to work correctly, the SDRAM needs to get > zero'd which > enables the ECC bit. By using the PL330 DMA to fill the SDRAM with > zeroes, > the operation is

Re: [U-Boot] [RFC 2/4] dma: Kconfig: Add CONFIG_PL330_DMA entry

Makefile | 1 + > 2 files changed, 5 insertions(+) > Reviewed-by: Chin Liang See <cl...@altera.com> Thanks Chin Liang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [RFC 1/4] drivers: dma: Add the ARM PL330 DMA driver

On Mon, 2016-10-10 at 10:52 -0500, Dinh Nguyen wrote: > From: Dinh Nguyen > > Adopted from the Linux kernel PL330 DMA driver. > > Signed-off-by: Dinh Nguyen > --- > arch/arm/include/asm/pl330.h | 105 + > drivers/dma/pl330.c

Re: [U-Boot] [PATCH] spi: Add support for MX66U51235F, MX66L1G45G and MT25QU02G

intel.com> > Cc: Chin Liang See <cl...@altera.com> > Cc: Dinh Nguyen <dingu...@opensource.altera.com> > Cc: Jagan Teki <jt...@openedev.com> > Cc: Radu Bacrau <radu.bac...@gmail.com> > --- > drivers/mtd/spi/sf_params.c | 3 +++ > 1 file changed, 3 in

Re: [U-Boot] [PATCH] doc: socfpga: Update README.socfpga for Preloader development flow

On Wed, 2016-09-21 at 11:59 +0200, Marek Vasut wrote: > On 09/21/2016 04:35 AM, Chin Liang See wrote: > > Update documentation to include the Cyclone V SoC Preloader > > development flow. This include the update of Preloader handoff > > through qts-filter.sh script. At same ti

[U-Boot] [PATCH] doc: socfpga: Update README.socfpga for Preloader development flow

Update documentation to include the Cyclone V SoC Preloader development flow. This include the update of Preloader handoff through qts-filter.sh script. At same time, removed the SDMMC documentation as its using DM now. Signed-off-by: Chin Liang See <cl...@altera.com> Cc: Marek Vas

[U-Boot] [PATCH v3 8/9] arm: socfpga: de0-nano-soc: Adding handoff for SDRAM ctrlcfg.extratime1

Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <cl...@altera.com> Cc: Marek Vasut <ma...@denx.de> Cc: Dinh Nguyen <dingu...@openso

[U-Boot] [PATCH v3 9/9] arm: socfpga: sockit: Adding handoff for SDRAM ctrlcfg.extratime1

Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <cl...@altera.com> Cc: Marek Vasut <ma...@denx.de> Cc: Dinh Nguyen <dingu...@openso

[U-Boot] [PATCH v3 7/9] arm: socfpga: sr1500: Adding handoff for SDRAM ctrlcfg.extratime1

Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <cl...@altera.com> Cc: Marek Vasut <ma...@denx.de> Cc: Dinh Nguyen <dingu...@openso

[U-Boot] [PATCH v3 6/9] arm: socfpga: vining_fpga: Adding handoff for SDRAM ctrlcfg.extratime1

Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <cl...@altera.com> Cc: Marek Vasut <ma...@denx.de> Cc: Dinh Nguyen <dingu...@openso

[U-Boot] [PATCH v3 2/9] arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1

Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <cl...@altera.com> Cc: Marek Vasut <ma...@denx.de> Cc: Dinh Nguyen <dingu...@openso

[U-Boot] [PATCH v3 4/9] arm: socfpga: socrates: Adding handoff for SDRAM ctrlcfg.extratime1

Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <cl...@altera.com> Cc: Marek Vasut <ma...@denx.de> Cc: Dinh Nguyen <dingu...@openso

[U-Boot] [PATCH v3 5/9] arm: socfpga: is1: Adding handoff for SDRAM ctrlcfg.extratime1

Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <cl...@altera.com> Cc: Marek Vasut <ma...@denx.de> Cc: Dinh Nguyen <dingu...@openso

[U-Boot] [PATCH v3 3/9] arm: socfpga: mcvevk: Adding handoff for SDRAM ctrlcfg.extratime1

Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <cl...@altera.com> Cc: Marek Vasut <ma...@denx.de> Cc: Dinh Nguyen <dingu...@openso

[U-Boot] [PATCH v3 1/9] ddr: altera: Configuring SDRAM extra cycles timing parameters

To enable configuration of sdr.ctrlcfg.extratime1 register which enable extra clocks for read to write command timing. This is critical to ensure successful LPDDR2 interface Signed-off-by: Chin Liang See <cl...@altera.com> Cc: Marek Vasut <ma...@denx.de> Cc: Dinh N

Re: [U-Boot] [PATCH v2] ddr: altera: Configuring SDRAM extra cycles timing parameters

On Wed, 2016-09-21 at 03:20 +0200, Marek Vasut wrote: > On 09/20/2016 08:05 AM, Chin Liang See wrote: > > To enable configuration of sdr.ctrlcfg.extratime1 register which > > enable > > extra clocks for read to write command timing. This is critical to > > ensure

Re: [U-Boot] [PATCH 2/9] arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1

On Tue, 2016-09-20 at 09:52 +0200, Marek Vasut wrote: > On 09/20/2016 07:37 AM, Chin Liang See wrote: > > On Mon, 2016-09-19 at 20:52 +0200, Marek Vasut wrote: > > > On 09/19/2016 12:12 PM, Chin Liang See wrote: > > > > On Mon, 2016-09-19 at 16:24 +0200, Marek Vasut

[U-Boot] [PATCH v2] ddr: altera: Configuring SDRAM extra cycles timing parameters

To enable configuration of sdr.ctrlcfg.extratime1 register which enable extra clocks for read to write command timing. This is critical to ensure successful LPDDR2 interface Signed-off-by: Chin Liang See <cl...@altera.com> Cc: Marek Vasut <ma...@denx.de> Cc: Dinh N

Re: [U-Boot] [PATCH 1/9] ddr: altera: Configuring SDRAM extra cycles timing parameters

On Mon, 2016-09-19 at 20:54 +0200, Marek Vasut wrote: > On 09/19/2016 12:11 PM, Chin Liang See wrote: > > On Mon, 2016-09-19 at 16:22 +0200, Marek Vasut wrote: > > > On 09/15/2016 09:26 AM, Chin Liang See wrote: > > > > To enable configuration of sdr.ctrlcfg.ext

Re: [U-Boot] [PATCH 2/9] arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1

On Mon, 2016-09-19 at 20:52 +0200, Marek Vasut wrote: > On 09/19/2016 12:12 PM, Chin Liang See wrote: > > On Mon, 2016-09-19 at 16:24 +0200, Marek Vasut wrote: > > > On 09/15/2016 09:27 AM, Chin Liang See wrote: > > > > Adding new handoff for SDRAM ctrcfg.extrat

Re: [U-Boot] [PATCH 4/9] arm: socfpga: socrates: Adding handoff for SDRAM ctrlcfg.extratime1

On Mon, 2016-09-19 at 16:24 +0200, Marek Vasut wrote: > On 09/15/2016 09:27 AM, Chin Liang See wrote: > > Adding new handoff for SDRAM ctrcfg.extratime1 which is > > required for stabil LPDDR2 operation > > Same comment as 2/9 applies to the rest Yup, we just need 1/

Re: [U-Boot] [PATCH 3/9] arm: socfpga: mcvevk: Adding handoff for SDRAM ctrlcfg.extratime1

On Mon, 2016-09-19 at 16:24 +0200, Marek Vasut wrote: > On 09/15/2016 09:27 AM, Chin Liang See wrote: > > Adding new handoff for SDRAM ctrcfg.extratime1 which is > > required for stabil LPDDR2 operation > > Same comment as 2/9 Yup, this patch is not required. Thanks Chin

Re: [U-Boot] [PATCH 2/9] arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1

On Mon, 2016-09-19 at 16:24 +0200, Marek Vasut wrote: > On 09/15/2016 09:27 AM, Chin Liang See wrote: > > Adding new handoff for SDRAM ctrcfg.extratime1 which is > > required for stabil LPDDR2 operation > > ... stable ... > > Isn't SoCDK using DDR3 DRAM ? Yah, you ar

Re: [U-Boot] [PATCH 1/9] ddr: altera: Configuring SDRAM extra cycles timing parameters

On Mon, 2016-09-19 at 16:22 +0200, Marek Vasut wrote: > On 09/15/2016 09:26 AM, Chin Liang See wrote: > > To enable configuration of sdr.ctrlcfg.extratime1 register which > > enable > > extra clocks for read to write command timing. This is critical to > > ensure

[U-Boot] [PATCH 7/9] arm: socfpga: sr1500: Adding handoff for SDRAM ctrlcfg.extratime1

Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stabil LPDDR2 operation Signed-off-by: Chin Liang See <cl...@altera.com> --- board/sr1500/qts/sdram_config.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/sr1500/qts/sdram_config.h b/board/sr15

[U-Boot] [PATCH 9/9] arm: socfpga: sockit: Adding handoff for SDRAM ctrlcfg.extratime1

Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stabil LPDDR2 operation Signed-off-by: Chin Liang See <cl...@altera.com> --- board/terasic/sockit/qts/sdram_config.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/terasic/sockit/qts/sdram_config.h b

[U-Boot] [PATCH 8/9] arm: socfpga: de0-nano-soc: Adding handoff for SDRAM ctrlcfg.extratime1

Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stabil LPDDR2 operation Signed-off-by: Chin Liang See <cl...@altera.com> --- board/terasic/de0-nano-soc/qts/sdram_config.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/terasic/de0-nano-soc/qts/sdram_confi

[U-Boot] [PATCH 6/9] arm: socfpga: vining_fpga: Adding handoff for SDRAM ctrlcfg.extratime1

Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stabil LPDDR2 operation Signed-off-by: Chin Liang See <cl...@altera.com> --- board/samtec/vining_fpga/qts/sdram_config.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/samtec/vining_fpga/qts/sdram_confi

[U-Boot] [PATCH 5/9] arm: socfpga: is1: Adding handoff for SDRAM ctrlcfg.extratime1

Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stabil LPDDR2 operation Signed-off-by: Chin Liang See <cl...@altera.com> --- board/is1/qts/sdram_config.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/is1/qts/sdram_config.h b/board/is1/qts/sdram_config.h

[U-Boot] [PATCH 4/9] arm: socfpga: socrates: Adding handoff for SDRAM ctrlcfg.extratime1

Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stabil LPDDR2 operation Signed-off-by: Chin Liang See <cl...@altera.com> --- board/ebv/socrates/qts/sdram_config.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/ebv/socrates/qts/sdram_config.h b/boa

[U-Boot] [PATCH 3/9] arm: socfpga: mcvevk: Adding handoff for SDRAM ctrlcfg.extratime1

Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stabil LPDDR2 operation Signed-off-by: Chin Liang See <cl...@altera.com> --- board/denx/mcvevk/qts/sdram_config.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/denx/mcvevk/qts/sdram_config.h b/board/denx/

[U-Boot] [PATCH 2/9] arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1

Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stabil LPDDR2 operation Signed-off-by: Chin Liang See <cl...@altera.com> --- board/altera/arria5-socdk/qts/sdram_config.h | 3 +++ board/altera/cyclone5-socdk/qts/sdram_config.h | 3 +++ 2 files changed, 6 insertions(+)

[U-Boot] [PATCH 1/9] ddr: altera: Configuring SDRAM extra cycles timing parameters

To enable configuration of sdr.ctrlcfg.extratime1 register which enable extra clocks for read to write command timing. This is critical to ensure successful LPDDR2 interface Signed-off-by: Chin Liang See <cl...@altera.com> --- arch/arm/mach-socfpga/include/mach/sdram.h | 8 +++- ar

Re: [U-Boot] [PATCH v2 01/11] arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address

On Tue, 2016-09-06 at 09:29 -0500, Dinh Nguyen wrote: > > On 09/06/2016 05:03 AM, Chin Liang See wrote: > > Add base address header file for Stratix10 SoC > > > > Signed-off-by: Chin Liang See <cl...@altera.com> > > Cc: Marek Vasut <ma

Re: [U-Boot] [PATCH 11/11] arm: socfpga: Add support for Stratix 10 SoC dev kit

On Tue, 2016-09-06 at 14:15 +0200, Marek Vasut wrote: > On 09/06/2016 11:18 AM, Chin Liang See wrote: > > On Mon, 2016-09-05 at 18:06 +0200, Marek Vasut wrote: > > > On 08/22/2016 05:02 PM, Chin Liang See wrote: > > > > Add support for Stratix 10 SoC development

Re: [U-Boot] [PATCH v2 09/11] arm: socfpga: stratix10: Add board directory for Stratix 10 socdk

On Tue, 2016-09-06 at 09:30 -0500, Dinh Nguyen wrote: > > On 09/06/2016 05:03 AM, Chin Liang See wrote: > > Add board folder for Stratix 10 SoC development kit > > > > Signed-off-by: Chin Liang See <cl...@altera.com> > > Cc: Marek Vasut <ma

Re: [U-Boot] [PATCH v2 11/11] arm: socfpga: Add support for Stratix 10 SoC dev kit

On Tue, 2016-09-06 at 09:32 -0500, Dinh Nguyen wrote: > > On 09/06/2016 05:03 AM, Chin Liang See wrote: > > Add support for Stratix 10 SoC development kit > > > > Signed-off-by: Chin Liang See <cl...@altera.com> > > Cc: Marek Vasut <ma

Re: [U-Boot] [PATCH v2 10/11] arm: dts: socfpga: Add dts for Stratix 10 socdk

On Tue, 2016-09-06 at 09:14 -0500, Dinh Nguyen wrote: > > On 09/06/2016 05:03 AM, Chin Liang See wrote: > > Add device tree for Stratix 10 SoC development kit > > > > Signed-off-by: Chin Liang See <cl...@altera.com> > > Cc: Marek Vasut <ma

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