Signed-off-by: Jonas Karlman
---
Cc: David Wu
Cc: Ezequiel Garcia
---
drivers/net/Kconfig| 8 +
drivers/net/Makefile | 1 +
drivers/net/dwc_eth_qos.c | 8 +-
drivers/net/dwc_eth_qos.h | 2 +
drivers/net/dwc_eth_qos_rockch
Hi Pierre-Clément,
Thanks for your correction, there was wrong mask here.
Reviewed-by: David Wu
在 2022/4/6 23:08, Kever Yang 写道:
Add David,
Hi David,
Could you help to check this patch?
Thanks,
- Kever
On 2022/3/16 23:39, Pierre-Clément Tosi wrote:
Swap the arguments as that seems
sses are inherited based on the devices
sequence IDs which is in turn given by the device tree.
Before there are more users in u-boot and both worlds will differ even
more, rename the alias prefix to "ethernet" to match the linux ones.
Also adapt the test cases and rename any old aliases in
he alias stem is a more
reasonable way.
Signed-off-by: David Wu
---
net/eth-uclass.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index e14695c0f1..3497a17db6 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -593,8 +593,8 @@ static in
he alias stem is a more
reasonable way.
Signed-off-by: David Wu
---
net/eth-uclass.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index e14695c0f1..7dd962db64 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -594,7 +594,7 @@ static in
,
Reviewed-by: David Wu
在 2020/6/27 下午11:03, Alexander Kochetkov 写道:
To make clear, there is kernel driver i2c-rk3x.c.
For rk3066 it write bits in the GRF word at offset 0x154. See [1] and [2].
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/i2c/busses/i2c
Hi Tom,
在 2020/6/12 下午10:48, Tom Rini 写道:
On Tue, May 12, 2020 at 05:56:01PM +0800, David Wu wrote:
It can be seen that most of the Socs using STM mac, "snps,reset-gpio"
gpio is used, adding this option makes reset function more general.
Signed-off-by: David Wu
Reviewed-by: Patri
Hi Patrick,
Yes, this is the case, it should be add at PHY node, and I also used the
original writing "snps,reset*" at MAC node. Anyway, I will try to put
the reset gpio in the PHY node.
在 2020/5/13 下午8:55, Patrick DELAUNAY 写道:
Hi David
From: David Wu
Sent: mardi 12 mai
.
Thanks
Patrice
On 5/11/20 9:00 AM, David Wu wrote:
Rockchip Socs can support two controllers "snps, dwmac-4.20a"
and "snps, dwmac-3.50". In order to support two at gmac-rockchip.c,
export public interface functions and struct data, it will be more
general for others.
C
This Soc is different from the previous Socs, need to
define eqos_config, and follow the dwc_eth_qos driver
process.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/gmac_rockchip.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/net
The Rockchip CSR clock range is from 100M to 150M, add
EQOS_MAC_MDIO_ADDRESS_CR_100_150.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index
The eqos_rockchip_ops is simillar to eqos_stm32_ops, and
export the eqos_rockchip_ops to use.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.c | 16
drivers/net/dwc_eth_qos.h | 2 ++
2 files changed, 18 insertions(+)
diff --git a/drivers/net
Change the original data structure so that Rockchip's Soc
gmac controller can support the designware.c and dwc_eth_qos.c
drivers, a Soc can only support one.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/Kconfig | 2 +-
drivers/net/gmac_rockchip.c | 160
Open structure data and interface, so that Soc using dw_eth_qos
controller can reference.
Signed-off-by: David Wu
---
Changes in v2:
- Add the lost head file. (Patrice)
drivers/net/dwc_eth_qos.c | 81
drivers/net/dwc_eth_qos.h | 87
according to the current link speed.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.c | 56 ++-
1 file changed, 38 insertions(+), 18 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index bec9bf556b
After moving to eqos_ops, if eqos_config is defined
outside file, can not export interface() definition,
only export eqos_ops struct defined in dwc_eth_qos.c.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.c | 20 ++--
1 file changed, 10 insertions
If there are definitions for eqos_start_clks and eqos_stop_clks,
then call these callback function.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b
rice)
- None
- Don't change the Rx and Tx clock names. (Patrice, Stephen)
- None
- None
- Add the lost head file. (Patrice)
- None
- None
- None
- None
David Wu (11):
net: dwc_eth_qos: Use dev_ functions calls to get FDT data
net: dwc_eth_qos: Add option "snps,reset-gpio" phy-rst gpi
It seems dev_ functions are more general than fdt_ functions.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index f67c5f4570
It can be seen that most of the Socs using STM mac, "snps,reset-gpio"
gpio is used, adding this option makes reset function more general.
Signed-off-by: David Wu
---
Changes in v2:
- Remove the code is not related (Patrice)
drivers/net/dwc_eth_qos.c | 32 +
For others using, clk_rx and clk_tx may not be necessary,
and their clock names are different.
Signed-off-by: David Wu
---
Changes in v2:
- Don't change the Rx and Tx clock names. (Patrice, Stephen)
drivers/net/dwc_eth_qos.c | 61 +++
1 file changed, 29
Hi Patrice,
在 2020/5/11 下午8:48, Patrice CHOTARD 写道:
Hi David
On 5/9/20 8:42 AM, David Wu wrote:
Hi Patrice,
在 2020/4/30 下午11:33, Patrice CHOTARD 写道:
Can you explain why you are splitting this function in 2 parts and calling
these parts sequentially ?
For rockchip, need to obtain
Open structure data and interface, so that Soc using dw_eth_qos
controller can reference.
Signed-off-by: David Wu
---
Changes in v2:
- Add the lost head file. (Patrice)
drivers/net/dwc_eth_qos.c | 81
drivers/net/dwc_eth_qos.h | 87
The Rockchip CSR clock range is from 100M to 150M, add
EQOS_MAC_MDIO_ADDRESS_CR_100_150.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index
Discard this duplicate patch.
在 2020/5/11 下午3:08, David Wu 写道:
The Rockchip CSR clock range is from 100M to 150M, add
EQOS_MAC_MDIO_ADDRESS_CR_100_150.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
This Soc is different from the previous Socs, need to
define eqos_config, and follow the dwc_eth_qos driver
process.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/gmac_rockchip.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/net
The Rockchip CSR clock range is from 100M to 150M, add
EQOS_MAC_MDIO_ADDRESS_CR_100_150.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index
The eqos_rockchip_ops is simillar to eqos_stm32_ops, and
export the eqos_rockchip_ops to use.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.c | 16
drivers/net/dwc_eth_qos.h | 2 ++
2 files changed, 18 insertions(+)
diff --git a/drivers/net
Change the original data structure so that Rockchip's Soc
gmac controller can support the designware.c and dwc_eth_qos.c
drivers, a Soc can only support one.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/Kconfig | 2 +-
drivers/net/gmac_rockchip.c | 160
If there are definitions for eqos_start_clks and eqos_stop_clks,
then call these callback function.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b
For Rockchip, before enabling mac and mac working, we
need to obtain the current link speed to configure the
TX/RX clocks, so split eqos_start into two functions.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.c | 56 ++-
1 file
It seems dev_ functions are more general than fdt_ functions.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 63f2086dec
For others using, clk_rx and clk_tx may not be necessary,
and their clock names are different.
Signed-off-by: David Wu
---
Changes in v2:
- Don't change the Rx and Tx clock names. (Patrice, Stephen)
drivers/net/dwc_eth_qos.c | 61 +++
1 file changed, 29
After moving to eqos_ops, if eqos_config is defined
outside file, can not export interface() definition,
only export eqos_ops struct defined in dwc_eth_qos.c.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.c | 14 +++---
1 file changed, 7 insertions(+), 7
It can be seen that most of the Socs using STM mac, "snps,reset-gpio"
gpio is used, adding this option makes reset function more general.
Signed-off-by: David Wu
---
Changes in v2:
- Remove the code is not related (Patrice)
drivers/net/dwc_eth_qos.c | 32 +
rice)
- None
- Don't change the Rx and Tx clock names. (Patrice, Stephen)
- None
- None
- Add the lost head file. (Patrice)
- None
- None
- None
- None
David Wu (11):
net: dwc_eth_qos: Use dev_ functions calls to get FDT data
net: dwc_eth_qos: Add option "snps,reset-gpio" phy-rst gpi
Hi Stephen,
在 2020/5/1 上午6:52, Stephen Warren 写道:
I'm really confused; with a filename like gmac_rockchip.c that sounds
like it's driver for a MAC device. DWC EQoS is also a MAC device. The
two shouldn't be related or coupled in any way.
I think what you need is to completely drop this patch
Hi Patrice,
在 2020/4/30 下午11:33, Patrice CHOTARD 写道:
Can you explain why you are splitting this function in 2 parts and calling
these parts sequentially ?
For rockchip, need to obtain the current link speed to configure the tx
clocks, (for example, in rgmii mode, 1000M link: 125M, 100M
Hi Stephen,
在 2020/5/1 上午6:45, Stephen Warren 写道:
Oh... Judging by your email, you're trying to make this driver work on a
Rockchip system. However, you're editing an STM32-specific probe
function. You should introduce a new probe function for Rockchip if it
needs to work differently to the
Hi Patrice,
在 2020/4/30 下午10:00, Patrice CHOTARD 写道:
@@ -647,8 +653,10 @@ static void eqos_stop_clks_stm32(struct udevice *dev)
debug("%s(dev=%p):\n", __func__, dev);
- clk_disable(>clk_tx);
- clk_disable(>clk_rx);
+ if (clk_valid(>clk_tx))
+
Hi Stephen,
在 2020/5/9 上午10:41, David Wu 写道:
The kernel's ./Documentation/devicetree/bindings/net/stmmac.txt mentions
that Required properties:
- phy-mode: See ethernet.txt file in the same directory.
- snps,reset-gpio gpio number for phy reset.
- snps,reset-active-low boolean flag
Hi Stephen,
在 2020/5/1 上午6:39, Stephen Warren 写道:
On 4/30/20 4:36 AM, David Wu wrote:
After moving to eqos_ops, if eqos_config is defined
outside, can not export interface() definition.
Looking at the patch itself, I think this patch just moves a function
pointer from the config to the ops
Hi Patrice,
在 2020/4/30 下午11:47, Patrice CHOTARD 写道:
@@ -701,6 +702,15 @@ static int eqos_start_resets_stm32(struct udevice *dev)
debug("%s(dev=%p):\n", __func__, dev);
if (dm_gpio_is_valid(>phy_reset_gpio)) {
+ ret = dm_gpio_set_value(>phy_reset_gpio, 0);
+
Hi Stephen,
在 2020/5/1 上午6:36, Stephen Warren 写道:
The kernel's bindings/net/snps,dwmac.yaml does not mention any
reset-gpios property (which is what the existing code parses just above
the portion that is quoted by this patch as context). I suspect that
this patch should simply change the name
For others using, clk_rx and clk_tx may not be necessary,
and their clock names are different.
Signed-off-by: David Wu
---
drivers/net/dwc_eth_qos.c | 65 +++
1 file changed, 31 insertions(+), 34 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers
Change the original data structure so that Rockchip's Soc
gmac controller can support the designware.c and dwc_eth_qos.c
drivers, a Soc can only support one.
Signed-off-by: David Wu
---
drivers/net/Kconfig | 2 +-
drivers/net/gmac_rockchip.c | 160
Open structure data and interface, so that Soc using dw_eth_qos
controller can reference.
Signed-off-by: David Wu
---
drivers/net/dwc_eth_qos.c | 81 +--
1 file changed, 9 insertions(+), 72 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net
Before enabling mac and mac working, we need to obtain
the current link speed to configure the clock, so split
eqos_start into two functions.
Signed-off-by: David Wu
---
drivers/net/dwc_eth_qos.c | 56 ++-
1 file changed, 38 insertions(+), 18 deletions
After moving to eqos_ops, if eqos_config is defined
outside, can not export interface() definition.
Signed-off-by: David Wu
---
drivers/net/dwc_eth_qos.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
When using rgmii Gigabit mode, the wait_for_bit_le32()
reset method resulting in RX can not receive data, after
this patch, works well.
Signed-off-by: David Wu
---
drivers/net/dwc_eth_qos.c | 21 +++--
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/drivers/net
It can be seen that most of the Socs using STM mac, "snps,reset-gpio"
gpio is used, adding this option makes reset function more general.
Signed-off-by: David Wu
---
drivers/net/dwc_eth_qos.c | 40 ++-
1 file changed, 35 insertions(+), 5 deletion
It seems dev_ functions are more general than fdt_ functions.
Signed-off-by: David Wu
---
drivers/net/dwc_eth_qos.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 63f2086dec..a72132cacf 100644
--- a/drivers
Rockchip Socs can support two controllers "snps, dwmac-4.20a"
and "snps, dwmac-3.50". In order to support two at gmac-rockchip.c,
export public interface functions and struct data, it will be more
general for others.
David Wu (8):
net: dwc_eth_qos: Use dev_ functions c
An iomux register contains 8 pins, each of which is represented
by 2 bits, but the register offset is 0x8.
For example, GRF_GPIO0A_IOMUX offset is 0x0, but GRF_GPIO0B_IOMUX
offset is 0x8, the offset 0x4 is reserved.
So add a type IOMUX_8WIDTH_2BIT to calculate offset.
Signed-off-by: David Wu
,
configure duty, period and polarity at next same period, to
prevent the intermediate temporary state.
Signed-off-by: David Wu
---
Change in v2: None
- Remove RK3399 compatible
arch/arm/include/asm/arch-rockchip/pwm.h | 17 ++-
drivers/pwm/rk_pwm.c | 138
Hi Kever,
在 2019/11/27 下午2:23, Kever Yang 写道:
David,
On 2019/11/26 上午9:39, David Wu wrote:
The rk3308 only support RMII mode, and if it is output clock
mode, better to use ref_clk pin with drive strength 12ma.
Signed-off-by: David Wu
Did you send this to kernel list at the same time?
I
The Firefly ROC_RK3308_CC use ref_clock of input mode,
and rmii pins of m1 group.
Signed-off-by: David Wu
---
arch/arm/dts/rk3308-roc-cc.dts | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/dts/rk3308-roc-cc.dts b/arch/arm/dts/rk3308-roc-cc.dts
index e10aa638a3..b4a54a852c
The rk3308 only support RMII mode, and if it is output clock
mode, better to use ref_clk pin with drive strength 12ma.
Signed-off-by: David Wu
---
arch/arm/dts/rk3308.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/dts/rk3308.dtsi b/arch/arm/dts/rk3308
Add the glue code to allow the rk3308 variant of the Rockchip gmac
to provide network functionality.
Signed-off-by: David Wu
---
drivers/net/gmac_rockchip.c | 65 +
1 file changed, 65 insertions(+)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net
The most pins of rk3308 are 2bits iomux, but the banks's register
width is 0x8.
Signed-off-by: David Wu
---
drivers/pinctrl/rockchip/Makefile | 1 +
drivers/pinctrl/rockchip/pinctrl-rk3308.c | 464 ++
.../pinctrl/rockchip/pinctrl-rockchip-core.c | 3
When we want to use plus iomux feature, we need to enable
them at spl.
Signed-off-by: David Wu
---
arch/arm/mach-rockchip/rk3308/rk3308.c | 33 ++
1 file changed, 33 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c
b/arch/arm/mach-rockchip/rk3308
The new PWM driver supports PWM polarity, lock and more functions.
Signed-off-by: David Wu
---
arch/arm/include/asm/arch-rockchip/pwm.h | 17 ++-
drivers/pwm/rk_pwm.c | 139 +++
2 files changed, 131 insertions(+), 25 deletions(-)
diff --git a/arch/arm
Only some Soc need Schmitter feature, so move the
implementation into their own files.
Signed-off-by: David Wu
---
Change in v3:
- None
drivers/pinctrl/rockchip/pinctrl-rk3328.c | 17 -
.../pinctrl/rockchip/pinctrl-rockchip-core.c | 19 +++
drivers/pinctrl
As the mux/pull/drive feature implement at own file,
the type and label are not necessary.
Signed-off-by: David Wu
---
Change in v3:
- None
drivers/pinctrl/rockchip/pinctrl-rk3036.c | 2 --
drivers/pinctrl/rockchip/pinctrl-rk3128.c | 2 --
drivers/pinctrl/rockchip/pinctrl-rk3188.c
RK3288 pmu_gpio0 pull setting have no higher 16 writing corresponding
bits, need to read before write the register.
Signed-off-by: David Wu
---
Change in v3:
- None
drivers/pinctrl/rockchip/pinctrl-rk3288.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git
As the common set_mux func(), implement the feature at the own file
for each Soc.
Signed-off-by: David Wu
---
Change in v3:
- None
drivers/pinctrl/rockchip/pinctrl-rk3036.c | 23 -
drivers/pinctrl/rockchip/pinctrl-rk3128.c | 23 -
drivers/pinctrl/rockchip/pinctrl-rk3188.c
RK3288 pmu_gpio0 drive strength setting have no higher 16 writing
corresponding bits, need to read before write the register.
Signed-off-by: David Wu
---
Change in v3:
- Add some comment
drivers/pinctrl/rockchip/pinctrl-rk3288.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions
As the common set_mux func(), implement the feature at the own file
for each Soc.
Signed-off-by: David Wu
---
Change in v3:
- None
drivers/pinctrl/rockchip/pinctrl-rk322x.c | 25 -
drivers/pinctrl/rockchip/pinctrl-rk3288.c | 35 +--
drivers/pinctrl/rockchip/pinctrl-rk3328.c
Some files have the redundant spaces, remove them.
Signed-off-by: David Wu
---
Change in v3:
- None
drivers/pinctrl/rockchip/pinctrl-rk3036.c | 12 ++--
drivers/pinctrl/rockchip/pinctrl-rk3188.c | 12 ++--
drivers/pinctrl/rockchip/pinctrl-rk322x.c | 18
RK3288 pmu_gpio0 iomux setting have no higher 16 writing corresponding
bits, need to read before write the register.
Signed-off-by: David Wu
---
Change in v3:
- Add some comment
drivers/pinctrl/rockchip/pinctrl-rk3288.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff
Such as rk3288's pins of pmu_gpio0 are a special feature, which have no
higher 16 writing corresponding bits, use common set_mux() func would
introduce more code, so implement their set_mux() in each Soc's own
file to reduce the size of code.
Signed-off-by: David Wu
---
Change in v3:
- None
Some Socs use the pull-pin-default config param, need to add it.
And input-enable/disable config params are not necessary, remove it.
Signed-off-by: David Wu
---
Change in v3:
- Add some commit message
drivers/pinctrl/rockchip/pinctrl-rockchip-core.c | 3 +--
1 file changed, 1 insertion(+), 2
To reduce the pinctrl driver, implement the mux/drive/pull/schmitt
func at per Soc.
David Wu (10):
pinctrl: rockchip: Add pull-pin-default param and remove unused param
pinctrl: rockchip: Remove redundant spaces
pinctrl: rockchip: Split the common set_mux() into per Soc
pinctrl
Hi Philipp,
在 2019/4/4 下午3:19, Philipp Tomsich 写道:
On 04.04.2019, at 05:51, David Wu wrote:
RK3288 pmu_gpio0 iomux setting have no higher 16 writing corresponding
bits, need to read before write the register.
Signed-off-by: David Wu
---
drivers/pinctrl/rockchip/pinctrl-rk3288.c | 8
Only some Soc need Schmitter feature, so move the
implementation into their own files.
Signed-off-by: David Wu
---
drivers/pinctrl/rockchip/pinctrl-rk3328.c | 17 -
.../pinctrl/rockchip/pinctrl-rockchip-core.c | 19 +++
drivers/pinctrl/rockchip/pinctrl
As the mux/pull/drive feature implement at own file,
the type and label are not necessary.
Signed-off-by: David Wu
---
drivers/pinctrl/rockchip/pinctrl-rk3036.c | 2 --
drivers/pinctrl/rockchip/pinctrl-rk3128.c | 2 --
drivers/pinctrl/rockchip/pinctrl-rk3188.c | 2 --
drivers/pinctrl
RK3288 pmu_gpio0 pull setting have no higher 16 writing corresponding
bits, need to read before write the register.
Signed-off-by: David Wu
---
drivers/pinctrl/rockchip/pinctrl-rk3288.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/rockchip
As the common set_mux func(), implement the feature at the own file
for each Soc.
Signed-off-by: David Wu
---
drivers/pinctrl/rockchip/pinctrl-rk3036.c | 23 -
drivers/pinctrl/rockchip/pinctrl-rk3128.c | 23 -
drivers/pinctrl/rockchip/pinctrl-rk3188.c | 29 +-
drivers
RK3288 pmu_gpio0 drive strength setting have no higher 16 writing
corresponding bits, need to read before write the register.
Signed-off-by: David Wu
---
drivers/pinctrl/rockchip/pinctrl-rk3288.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl
As the common set_mux func(), implement the feature at the own file
for each Soc.
Signed-off-by: David Wu
---
drivers/pinctrl/rockchip/pinctrl-rk322x.c | 25 -
drivers/pinctrl/rockchip/pinctrl-rk3288.c | 35 +--
drivers/pinctrl/rockchip/pinctrl-rk3328.c | 26 -
drivers
Such as rk3288's pins of pmu_gpio0 are a special feature, which have no
higher 16 writing corresponding bits, use common set_mux() func would
introduce more code, so implement their set_mux() in each Soc's own
file to reduce the size of code.
Signed-off-by: David Wu
---
drivers/pinctrl
Some files have the redundant spaces, remove them.
Signed-off-by: David Wu
---
drivers/pinctrl/rockchip/pinctrl-rk3036.c | 12 ++--
drivers/pinctrl/rockchip/pinctrl-rk3188.c | 12 ++--
drivers/pinctrl/rockchip/pinctrl-rk322x.c | 18 -
drivers/pinctrl/rockchip
RK3288 pmu_gpio0 iomux setting have no higher 16 writing corresponding
bits, need to read before write the register.
Signed-off-by: David Wu
---
drivers/pinctrl/rockchip/pinctrl-rk3288.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/rockchip/pinctrl
Some Socs use the pull-pin-default config param, need to add it.
Signed-off-by: David Wu
---
drivers/pinctrl/rockchip/pinctrl-rockchip-core.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
b/drivers/pinctrl/rockchip
To reduce the pinctrl driver, implement the mux/drive/pull/schmitt
func at per Soc.
David Wu (10):
pinctrl: rockchip: Add pull-pin-default param and remove unused param
pinctrl: rockchip: Remove redundant spaces
pinctrl: rockchip: Split the common set_mux() into per Soc
pinctrl
Hi Philipp,
This config does not look like it will be used in SPL and can be
deleted.
Reviewed-by: David Wu
在 2019/2/28 上午3:05, Heinrich Schuchardt 写道:
The SPL for the Tinker Board has to fit into 32 KiB. Currently this limit
is exceeded.
CONFIG_SPL_I2C_SUPPORT is not needed to move to main
.
Thanks,
Philipp.
On 12.02.2019, at 12:55, Philipp Tomsich
<mailto:philipp.toms...@theobroma-systems.com>> wrote:
On 12.02.2019, at 12:51, David Wu <mailto:david...@rock-chips.com>> wrote:
There are no higher 16 writing corresponding bits for pmu_gpio0's
iomux/drive/pu
:05:12 CET schrieb David Wu:
Hi Heinrich and Michael,
Another thing i see is that I missed a patch, for the 3288 gpio0, its
iomux is special, there is no high 16-bit write-enabled bit. For Tinker
board, it uses I2C0, the current driver will overwrite the I2C0 iomux,
while request the GPIO0A4
Hi Philipp,
在 2019/2/28 下午8:36, Philipp Tomsich 写道:
On 28.02.2019, at 11:50, Heiko Stübner <mailto:he...@sntech.de>> wrote:
Hi David,
Am Montag, 18. Februar 2019, 02:05:12 CET schrieb David Wu:
Hi Heinrich and Michael,
Another thing i see is that I missed a patch, for the 3288 g
causes SPL not to start.
CONFIG_SYS_MALLOC_F_LEN=0x4000
does not solve the problem.
Best regards
Heinrich
Michael
On Sun., 17 Feb. 2019, 1:11 pm Heinrich Schuchardt mailto:xypron.g...@gmx.de> wrote:
On 2/17/19 9:19 AM, David Wu wrote:
> Hi Henrich,
>
> 在 2019
Hi Henrich,
在 2019/2/16 下午5:53, Heinrich Schuchardt 写道:
On 2/13/19 11:56 AM, Philipp Tomsich wrote:
On 13.02.2019, at 11:52, David Wu wrote:
Hi philipp,
在 2019/2/13 下午6:47, Philipp Tomsich 写道:
On 13.02.2019, at 11:33, David Wu wrote:
在 2019/2/13 下午6:13, Philipp Tomsich 写道
Hi philipp,
在 2019/2/13 下午6:47, Philipp Tomsich 写道:
On 13.02.2019, at 11:33, David Wu wrote:
在 2019/2/13 下午6:13, Philipp Tomsich 写道:
On 13.02.2019, at 11:10, David Wu wrote:
Hi Philipp,
在 2019/2/12 下午9:54, Philipp Tomsich 写道:
On 12.02.2019, at 13:38, David Wu wrote:
Hi Philipp,
在
Hi Philipp,
在 2019/2/13 下午6:30, Philipp Tomsich 写道:
The 10k comes from a direct comparison on our RK3399-Q7, after pulling in all
the required DTS nodes and properties vs. a minimal simple pinctrl for I2C only
(which is ~ 100 bytes of code).
So according to your mind, do not use DTS at the
在 2019/2/13 下午6:13, Philipp Tomsich 写道:
On 13.02.2019, at 11:10, David Wu wrote:
Hi Philipp,
在 2019/2/12 下午9:54, Philipp Tomsich 写道:
On 12.02.2019, at 13:38, David Wu wrote:
Hi Philipp,
在 2019/2/10 上午2:24, Philipp Tomsich 写道:
That said, I have been fighting issues from this patchset
Hi Philipp,
在 2019/2/12 下午9:53, Philipp Tomsich 写道:
On 12.02.2019, at 13:38, David Wu wrote:
Hi Philipp,
在 2019/2/10 上午2:24, Philipp Tomsich 写道:
That said, I have been fighting issues from this patchset when trying to read
from devices on the i2c0 bus on a RK3399—which had me add
Hi Philipp,
在 2019/2/12 下午9:54, Philipp Tomsich 写道:
On 12.02.2019, at 13:38, David Wu wrote:
Hi Philipp,
在 2019/2/10 上午2:24, Philipp Tomsich 写道:
That said, I have been fighting issues from this patchset when trying to read
from devices on the i2c0 bus on a RK3399—which had me add
Hi Philipp,
在 2019/2/10 上午2:24, Philipp Tomsich 写道:
That said, I have been fighting issues from this patchset when trying to read
from devices on the i2c0 bus on a RK3399—which had me add a “simple”
pinctrl device again, as pulling all the dependencies into the SPL is a pain.
I think you can
can’t
test or debug on the rk3288 due to a lack of hardware.
If you want to start digging, that the changes in
commit 08c817c39908f9d120df1e4c90ddad4a11fc3891
Author: David Wu
Date: Wed Jan 2 20:51:00 2019 +0800
ARM: rockchip: Remove the pinctrl request at rk3288-board-spl
There are no higher 16 writing corresponding bits for pmu_gpio0's
iomux/drive/pull at rk3288, need to read the value from register
firstly. Add the flag to distinguish it from normal registers.
Signed-off-by: David Wu
---
drivers/pinctrl/rockchip/pinctrl-rk3288.c | 17 ++--
.../pinctrl
Ping Philipp...
在 2019/1/22 上午2:50, Simon Glass 写道:
Hi,
On Thu, 3 Jan 2019 at 01:51, David Wu wrote:
The common pinctrl driver for rockchip Socs, it depends the PINCTRL_FULL config.
If use it, the default pinctrl setup from DTS could be configured at device
probe.
Changes in v2:
- Remove
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