Hi Lukasz,
在 2019/1/19 上午7:34, Lukasz Majewski 写道:
Hi David,
Hi Heiko,
在 2019/1/6 上午1:17, Heiko Stuebner 写道:
diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c
b/arch/arm/mach-rockchip/rk3188-board-spl.c index
3c6c3d3c09..a5e4d39cb7 100644 ---
a/arch/arm/mach-rockchip/rk3188-board-spl.c
Hi Heiko,
在 2019/1/6 上午1:17, Heiko Stuebner 写道:
diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c
b/arch/arm/mach-rockchip/rk3188-board-spl.c
index 3c6c3d3c09..a5e4d39cb7 100644
--- a/arch/arm/mach-rockchip/rk3188-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3188-board-spl.c
@@ -120,7
To match the iomux setting of uart2 at SPL, correct the uart2
default pin configuration, if not changed, the evb-rk3229 can't
output the log message.
Signed-off-by: David Wu
---
Changes in v2: None
arch/arm/dts/rk322x.dtsi | 11 +--
1 file changed, 9 insertions(+), 2 deletions
If we used the pinctrl-rockchip driver, these config is not needed,
so remove them.
Signed-off-by: David Wu
---
Changes in v2: None
configs/chromebit_mickey_defconfig | 2 --
configs/chromebook_jerry_defconfig | 2 --
configs/chromebook_minnie_defconfig | 2 --
configs/evb-px5_defconfig
Use this driver to fit all Rockchip SOCs and to support
the desired pinctrl configuration via DTS.
Signed-off-by: David Wu
---
Changes in v2:
- Remove px30, rk2928, rk3066*.
- Split it to multiple files for the relevant per-SoC data structures.
drivers/pinctrl/Kconfig
The FDT is requested for new pinctrl driver, disable SPL_OF_PLATDATA
and enable SPL_OF_LIBFDT to make FDT be built in.
Signed-off-by: David Wu
---
Changes in v2: None
configs/chromebit_mickey_defconfig | 2 --
configs/chromebook_jerry_defconfig | 2 --
configs/chromebook_minnie_defconfig
If we use the new pinctrl driver, the pinctrl setup will be done
by device probe. Remove the pinctrl setup at rk3288-board-spl.
Signed-off-by: David Wu
Reviewed-by: Philipp Tomsich
---
Changes in v2: None
arch/arm/mach-rockchip/rk3288-board-spl.c | 79 ---
1 file changed
It seems that pinctrl is not requested for rk3188 SPL, remove it so
that can save more space for SPL image size.
Signed-off-by: David Wu
Reviewed-by: Philipp Tomsich
---
Changes in v2: None
arch/arm/mach-rockchip/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/mach
The FDT is requested for new pinctrl driver, disable SPL_OF_PLATDATA
to make FDT be built in.
Signed-off-by: David Wu
---
Changes in v2: None
configs/evb-rk3399_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index
When the boot ROM sets up MMC we don't need to do it again. Remove the
MMC setup code entirely, but we also need to enable uart for debug message.
Signed-off-by: David Wu
---
Changes in v2: None
arch/arm/mach-rockchip/rk3188-board-spl.c | 41 ++-
1 file changed, 2
The common pinctrl driver for rockchip Socs, it depends the PINCTRL_FULL config.
If use it, the default pinctrl setup from DTS could be configured at device
probe.
Changes in v2:
- Remove px30, rk2928, rk3066*.
- Split it to multiple files for the relevant per-SoC data structures.
David Wu (9
Hi Philipp,
在 2018/12/27 下午10:31, Philipp Tomsich 写道:
David,
On 27.12.2018, at 13:49, David Wu wrote:
Hi Christoph,
I once submitted a series of patches that they can support all Socs' Pinctrl
and how do you feel about using them.
http://patchwork.ozlabs.org/patch/868849/
Which reminds
Hi Christoph,
This patch seems is less of code about drive strength, for some modules,
like LCD, Ethernet is still needed.
在 2018/12/27 下午9:13, Christoph Müllner 写道:
Hi David,
On 12/27/18 1:49 PM, David Wu wrote:
Hi Christoph,
I once submitted a series of patches that they can support all
Hi Christoph,
I once submitted a series of patches that they can support all Socs'
Pinctrl and how do you feel about using them.
http://patchwork.ozlabs.org/patch/868849/
在 2018/12/27 上午9:11, Kever Yang 写道:
Add David to review the pinctrl driver.
Thanks,
- Kever
On 12/17/2018 09:30 PM,
Hi Philipp,
Okay, each SOC should have its own file, which include private data
structure, and probe(). Can reduce driver size.
在 2018年02月19日 03:20, Philipp Tomsich 写道:
On Sat, 3 Feb 2018, David Wu wrote:
Use this driver to fit all Rockchip SOCs and to support
the desired pinctrl
Hi Philipp,
在 2018年02月19日 03:00, Philipp Tomsich 写道:
On Sat, 3 Feb 2018, David Wu wrote:
When the boot ROM sets up MMC we don't need to do it again. Remove the
MMC setup code entirely, but we also need to enable uart for debug
message.
If the MMC always set up correctly for all
Hi Philipp,
在 2018年02月19日 03:38, Philipp Tomsich 写道:
On Sat, 3 Feb 2018, David Wu wrote:
In fact, the evb-rk3229 is default supported the integrated phy,
not need to change any hardware. So it is better to enbale it and
disable external 1000M phy.
Signed-off-by: David Wu <david...@r
Hi Philipp,
在 2018年02月19日 03:36, Philipp Tomsich 写道:
On Sat, 3 Feb 2018, David Wu wrote:
Some Socs both have rgmii and rmii interface, so we need to
separate their speed setting.
Signed-off-by: David Wu <david...@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.toms...@
In fact, the rk3328-evb is default supported the integrated phy,
not need to change any hardware. So it is better to enbale it and
disable external 1000M phy.
Signed-off-by: David Wu <david...@rock-chips.com>
---
arch/arm/dts/rk3328-evb.dts | 10 ++
1 file changed, 10 inse
The integtated phy inside the rk3229 and rk3328 need the reset
request for power up.
Signed-off-by: David Wu <david...@rock-chips.com>
---
configs/evb-rk3229_defconfig | 1 +
configs/evb-rk3328_defconfig | 1 +
2 files changed, 2 insertions(+)
diff --git a/configs/evb-rk3229_defco
Implement the setting parent and rate for gmac2phy clock, and
add internal pll div set for gmac2phy clk.
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/clk/rockchip/clk_rk3328.c | 86 +++
1 file changed, 86 insertions(+)
diff --git a/d
In fact, the evb-rk3229 is default supported the integrated phy,
not need to change any hardware. So it is better to enbale it and
disable external 1000M phy.
Signed-off-by: David Wu <david...@rock-chips.com>
---
arch/arm/dts/rk3229-evb.dts | 22 ++
1 file chang
The gmac2phy is connected with integrated with phy, we can
fix the phy node at dtsi level.
Signed-off-by: David Wu <david...@rock-chips.com>
---
arch/arm/dts/rk3328.dtsi | 35 +++
1 file changed, 35 insertions(+)
diff --git a/arch/arm/dts/rk3328.dtsi b/ar
To support the integrated phy for rk322x, add their reset and clock
property at dtsi level.
Signed-off-by: David Wu <david...@rock-chips.com>
---
arch/arm/dts/rk322x.dtsi | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/rk322x.dtsi b/arch/a
The gmac for integrated phy need 50M clock, it seems that only
come from CPLL 600M, the GPLL is not suitable.
Signed-off-by: David Wu <david...@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/cru_rk322x.h | 1 +
drivers/clk/rockchip/clk_rk322x.c | 11 +++
2
The SCLK_MAC_SRC is the same as the SCLK_MAC, it is requested
by the integrated phy usuage.
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/clk/rockchip/clk_rk322x.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/rockchip/clk_rk322x.c
b/drivers/clk/ro
There is a wrong selection for gmac pll source, fix it.
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/clk/rockchip/clk_rk322x.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk_rk322x.c
b/drivers/clk/rockchip/clk_rk322x.c
It seems that the "CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)" always
should not been active.
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/clk/rockchip/clk_rk3036.c | 2 +-
drivers/clk/rockchip/clk_rk322x.c | 4 ++--
drivers/clk/rockchip/clk_rk3288.c | 2 +-
driv
The rk3228 and rk3328 Socs both support integrated phy, implement
their power up function to support it.
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/net/gmac_rockchip.c | 122
1 file changed, 122 insertions(+)
diff --git a/d
Some rockchio Socs have integrated phy inside, to support it,
add the integrated phy ops.
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/net/gmac_rockchip.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/drivers/net/gmac_rockchip.c b/d
The rk3228 and rk3328 Socs both have rmii interface, that might be used,
so add them for usage.
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/net/gmac_rockchip.c | 115
1 file changed, 115 insertions(+)
diff --git a/drive
Some Socs both have rgmii and rmii interface, so we need to
separate their speed setting.
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/net/gmac_rockchip.c | 62 +++--
1 file changed, 43 insertions(+), 19 deletions(-)
diff --git a/d
To support the integrated phy, it is necessary that the gmac need
to get 50M clock rate from internal PLL, the integrated phy can't
generate 50M clock itself.
David Wu (14):
net: rockchip: Separate rmii and rgmii speed setup
net: rockchip: Add rmii interface and rmii speed setup for rk3228
To match the iomux setting of uart2 at SPL, correct the uart2
default pin configuration, if not changed, the evb-rk3229 can't
output the log message.
Signed-off-by: David Wu <david...@rock-chips.com>
---
arch/arm/dts/rk322x.dtsi | 11 +--
1 file changed, 9 insertions(+), 2 del
If we used the pinctrl-rockchip driver, these config is not needed,
so remove them.
Signed-off-by: David Wu <david...@rock-chips.com>
---
configs/chromebit_mickey_defconfig | 2 --
configs/chromebook_jerry_defconfig | 2 --
configs/chromebook_minnie_defconfig | 2 --
configs/evb-px5_def
Use this driver to fit all Rockchip SOCs and to support
the desired pinctrl configuration via DTS.
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/pinctrl/Kconfig| 98 +-
drivers/pinctrl/Makefile |2 +-
drivers/pinctrl/pinctrl-rockchip.c
The fdedesc is requested for new pinctrl driver, disable SPL_OF_PLATDATA
to make fdedesc be built in.
Signed-off-by: David Wu <david...@rock-chips.com>
---
configs/chromebit_mickey_defconfig | 2 --
configs/chromebook_jerry_defconfig | 2 --
configs/chromebook_minnie_defconfig | 2 --
3
If we use the new pinctrl driver, the pinctrl setup will be done
by device probe. Remove the pinctrl setup at rk3288-board-spl.
Signed-off-by: David Wu <david...@rock-chips.com>
---
arch/arm/mach-rockchip/rk3288-board-spl.c | 79 ---
1 file changed, 79 del
When the boot ROM sets up MMC we don't need to do it again. Remove the
MMC setup code entirely, but we also need to enable uart for debug message.
Signed-off-by: David Wu <david...@rock-chips.com>
---
arch/arm/mach-rockchip/rk3188-board-spl.c | 42 +++
1 file c
It seems that pinctrl is not requested for rk3188 SPL, remove it so
that can save more space for SPL image size.
Signed-off-by: David Wu <david...@rock-chips.com>
---
arch/arm/mach-rockchip/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/ar
The fdedesc is requested for new pinctrl driver, disable SPL_OF_PLATDATA
to make fdedesc be built in.
Signed-off-by: David Wu <david...@rock-chips.com>
---
configs/evb-rk3399_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_def
The common pinctrl driver for rockchip Socs, it depends the PINCTRL_FULL config.
If use it, the default pinctrl setup from DTS could be configured at device
probe.
David Wu (9):
rockchip: rk3399-evb: defconfig: Disable SPL_OF_PLATDATA for new
pinctrl driver
ARM: rockchip: rk3188: Remove
Add gmac config support for rk3229 evb.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- None
Changes in v2:
- New patch
configs/evb-rk3229_defconfig | 5 +
1 file changed, 5 insertions(+)
diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_def
Implement the setting parent for gmac clock, and add internal
pll div set for mac clk.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- New patch
Changes in v2: None
arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 7 ++
drivers/clk/rockchip/clk_rk
The LCDC assigned rate is 0, it will make boot error,
error log:"pll_para_config: the frequency can not be
0 Hz". Remove them, and the lcdc driver will do the
correct clock rate setting.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- New patch
Changes in
Add rk3328-evb gmac support.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- None
Changes in v2:
- New patch
arch/arm/dts/rk3328-evb.dts | 30 ++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/
The GMAC in the RK3228 once again is identical to the incarnation in
the RK3288 and the RK3399, except for where some of the configuration
and control registers are located in the GRF.
This adds the RK3368-specific logic necessary to reuse this driver.
Signed-off-by: David Wu <david...@r
to signal success.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- New patch
Changes in v2: None
drivers/clk/rockchip/clk_rk3288.c | 106 ++---
include/dt-bindings/clock/rk3288-cru.h | 1 +
2 files changed, 99 insertions(+), 8 del
Set gmac pins iomux and rgmii tx pins to 12ma drive-strength,
clean others to 2ma.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- adhere to the established way of writing this to avoid future confusion
- use defined symbolic constants for drive-strength
Changes
Add basic dts configuration for rk3328 gmac2io.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- None
Changes in v2:
- New patch
arch/arm/dts/rk3328.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/dts/rk3328.dtsi b/arch/a
Assuming mac_clk is fed by an external clock, set clk_rmii_src
clock select control register from IO for rgmii interface.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- Add "set parent" for gmac
- Add internal mac clk div_sel for gmac
Changes in v2:
- New
Clean the iomux definitions at grf_rk322x.h, and move them into
pinctrl-driver for resolving the compiling error of redefinition.
After that, define the uart2 iomux at rk322x-board file.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- Fix the wrong define for uart2
Enable GMAC configs for evb-rk3328
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- None
Changes in v2:
- New patch
configs/evb-rk3328_defconfig | 5 +
1 file changed, 5 insertions(+)
diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
The GMAC2IO in the RK3328 once again is identical to the incarnation in
the RK3288 and the RK3399, except for where some of the configuration
and control registers are located in the GRF.
This adds the RK3328-specific logic necessary to reuse this driver.
Signed-off-by: David Wu <david...@r
The rk3328 soc has two gmac controllers, one is gmac2io,
the other is gmac2phy. We use the gmac2io rgmii interface
for 1000M phy here.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- Add "set parent" for gmac2io
- Add internal mac clk div_sel for gmac2i
Clean the iomux definitions at grf_rk3328.h, and move them into
pinctrl-driver for resolving the compiling error of redefinition.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- None
Changes in v2:
- New patch
arch/arm/include/asm/arch-rockchip/grf_rk3328.h
Need to set gmac m1 pins iomux, gmac m0 tx pins, select bit2
and bit10 at com iomux register. After that, set rgmii m1 tx
pins to 12ma drive-strength, and clean others to 2ma.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- adhere to the established way of w
The rv1108 GMAC only support rmii interface, so need to add the
set_rmii() ops. Use the phy current interface to set rmii or
rgmii ops. At the same time, need to set the mac clock rate of
rmii with 50M, the clock rate of rgmii with 125M.
Signed-off-by: David Wu <david...@rock-chips.
If the Ethernet address is not set, the network can't work,
enable the random address config for default use.
Signed-off-by: David Wu <david...@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.toms...@theobr
If we include both the rk3288_grf.h and rv1108_grf.h, it will cause the
conflicts of redefinition. Clean the iomux definitions at grf_rv1108.h,
and move them into pinctrl-driver.
Signed-off-by: David Wu <david...@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.toms...@theobroma-sy
Give the mac controller the correct tx-delay and rx-delay value
for the rgmii mode transmission. If they are not matched, there
would be Ethernet packets lost, the net feature may not work.
Signed-off-by: David Wu <david...@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.toms...@
The last 4 grf registers offset of rv1108 are wrong, fix them
for correct usage.
Signed-off-by: David Wu <david...@rock-chips.com>
Reviewed-by: Simon Glass <s...@chromium.org>
---
Changes in v3:
- None
Changes in v2:
- New patch
arch/arm/include/asm/arch-rockchip/grf_rv1108.h | 8
use defined symbolic constants for drive-strength
Changes in v2:
- Add check whether the set rgmii/rmii function is a valid function pointer
- Clean the grf offset at gmac_rockchip.c
- New patch
- None
- Use current phy interface to set mac clock rate
David Wu (20):
rockchip: dts:
Assuming mac_clk is fed by an external clock, set clk_rmii_src
clock select control register from IO for rgmii interface.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v2:
- New patch
drivers/clk/rockchip/clk_rk322x.c | 13 +
1 file changed, 13 inse
Set gmac pins iomux and rgmii tx pins to 12ma drive-strength,
clean others to 2ma.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v2:
- New patch
drivers/pinctrl/rockchip/pinctrl_rk322x.c | 138 ++
1 file changed, 138 insertions(+)
diff
nt preview: Clean the iomux definitions at grf_rk322x.h, and move them
into pinctrl-driver for resolving the compiling error of redefinition. After
that, define the uart2 iomux at rk322x-board file. Signed-off-by: David Wu
<david...@rock-chips.com> --- [...]
Content analysis detail
Add rk3328-evb gmac support.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v2:
- New patch
arch/arm/dts/rk3328-evb.dts | 30 ++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts
index 3
nt preview: Add basic dts configuration for rk3328 gmac2io. Signed-off-by:
David Wu <david...@rock-chips.com> --- Changes in v2: - New patch [...]
Content analysis details: (5.7 points, 5.0 required)
pts rule name
Enable GMAC configs for evb-rk3328
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v2:
- New patch
configs/evb-rk3328_defconfig | 5 +
1 file changed, 5 insertions(+)
diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
index 3b8b104..3d8c04d
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v2:
- New patch
drivers/net/gmac_rockchip.c | 85 +
1 file changed, 85 insertions(+)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 22e3941..f24c347 1006
The rk3328 soc has two gmac controllers, one is gmac2io,
the other is gmac2phy. We use the gmac2io rgmii interface
for 1000M phy here.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v2:
- New patch
drivers/clk/rockchip/clk_rk3328.c | 20
incl
Need to set gmac m1 pins iomux, gmac m0 tx pins, select bit2
and bit10 at com iomux register. After that, set rgmii m1 tx
pins to 12ma drive-strength, and clean others to 2ma.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v2:
- New patch
drivers/pinctrl/ro
nt preview: Clean the iomux definitions at grf_rk3328.h, and move them
into pinctrl-driver for resolving the compiling error of redefinition.
Signed-off-by:
David Wu <david...@rock-chips.com> --- Changes in v2: - New patch [...]
Content analysis details: (6.5 points, 5.0 required)
The rv1108 GMAC only support rmii interface, so need to add the
set_rmii() ops. Use the phy current interface to set rmii or
rgmii ops. At the same time, need to set the mac clock rate of
rmii with 50M, the clock rate of rgmii with 125M.
Signed-off-by: David Wu <david...@rock-chips.
nt preview: If we include both the rk3288_grf.h and rv1108_grf.h, it will
cause the conflicts of redefinition. Clean the iomux definitions at
grf_rv1108.h,
and move them into pinctrl-driver. Signed-off-by: David Wu
<david...@rock-chips.com>
--- [...]
Content analysis details:
The last 4 grf registers offset of rv1108 are wrong, fix them
for correct usage.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v2:
- New patch
arch/arm/include/asm/arch-rockchip/grf_rv1108.h | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/ar
If the Ethernet address is not set, the network can't work,
enable the random address config for default use.
Signed-off-by: David Wu <david...@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.toms...@theobr
nt preview: Give the mac controller the correct tx-delay and rx-delay
value for the rgmii mode transmission. If they are not matched, there would
be Ethernet packets lost, the net feature may not work. Signed-off-by: David
Wu <david...@rock-chips.com> Acked-by: Philipp Tomsic
nt preview: Assuming mac_clk is fed by an external clock, set clk_rmii_src
clock select control register from IO for rgmii interface. Signed-off-by:
David Wu <david...@rock-chips.com> Acked-by: Philipp Tomsich
<philipp.toms...@theobroma-systems.com>
Reviewed-by: Philipp
the grf offset at gmac_rockchip.c
- New patch
- New patch
- New patch
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- New patch
- New patch
- New patch
David Wu (18):
rockchip: clk: Add mac clock set for rk3399
rockchip: dts: rk3399-evb: Change the tx/rx delay value
The rv1108 mac only support rmii interface, so need to add the
set_rmii() ops. Use the phy current interface to set rmii or
rgmii ops.
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/net/gmac_rockchip.c | 67 +++--
1 file chang
If the mac clock if from the external IO, set clock rate with 0;
If the mac clock if from the internal divider pll, set 50M for
rmii mode and set 125M for rgmii.
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/net/gmac_rockchip.c | 23 +++
1 file chang
Give the mac controller the correct tx-delay and rx-delay value
for the rgmii mode transmission. If they are not matched, there
would be Ethernet packets lost, the net feature may not work.
Signed-off-by: David Wu <david...@rock-chips.com>
---
arch/arm/dts/rk3399-evb.dts | 4 ++--
If the Ethernet address is not set, the network can't work,
enable the random address config for default use.
Signed-off-by: David Wu <david...@rock-chips.com>
---
configs/evb-rk3288_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/evb-rk3288_defconfig b/confi
If we include both the rk3288_grf.h and rv1108_grf.h, there is a
number of compiling error for redefinition. So we define the reg
structs of mac_grf at gmac_rockchip.c. Remove the rk**_grf.h files,
give them own grf offset for their use.
Signed-off-by: David Wu <david...@rock-chips.
Assuming mac_clk is fed by an external clock, set clk_rmii_src
clock select control register from IO for rgmii interface.
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/clk/rockchip/clk_rk3399.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
This serie of patches integrates the setup mac clock is
internal or external, as well as the way for setting rmii
or rgmii interface.
David Wu (6):
rockchip: clk: Add mac clock set for rk3399
rockchip: dts: rk3399-evb: Change the tx/rx delay value for
transmission quality
rockchip
Enable the SARADC for download key pressed detect.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- Add commit message
Changes in v2: None
arch/arm/dts/rk3399-evb.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/a
nt preview: Enable the SARADC for download key pressed detect.
Signed-off-by:
David Wu <david...@rock-chips.com> --- Changes in v3: - Add commit message
[...]
Content analysis details: (5.6 points, 5.0 required)
pts rule name
Enable the SARADC for download key pressed detect.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- Add commit message
Changes in v2: None
arch/arm/dts/rk3368-px5-evb.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rk3368-px5-evb.dts b/ar
nt preview: Enable the SARADC for download key pressed detect.
Signed-off-by:
David Wu <david...@rock-chips.com> --- Changes in v3: - Add commit message
[...]
Content analysis details: (5.6 points, 5.0 required)
pts rule name
Enable the SARADC for download key pressed detect.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- Add commit message
Changes in v2: None
arch/arm/dts/rv1108-evb.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rv1108-evb.dts b/arch/a
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.
Signed-off-by: David Wu <david...@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
Reviewed-by: Philipp Tomsich &
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.
Signed-off-by: David Wu <david...@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
Reviewed-by: Philipp Tomsich &
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.
Signed-off-by: David Wu <david...@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
Reviewed-by: Philipp Tomsich &
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.
Signed-off-by: David Wu <david...@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
Acked-by: Philipp Tomsich &
nt preview: Except for 3036 and 3228 Socs, which don't support SARADC,
enable the ROCKCHIP_SARADC config at the other Socs' defconfig.
Signed-off-by:
David Wu <david...@rock-chips.com> --- [...]
Content analysis details: (5.6 points, 5.0 required)
pts rule name
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.
Signed-off-by: David Wu <david...@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
Reviewed-by: Philipp Tomsich &
David Wu (14):
dm: adc: Add driver for Rockchip SARADC
rockchip: configs: Enable the ROCKCHIP_SARADC config
rockchip: clk: Add rv1108 SARADC clock support
rockchip: clk: Add SARADC clock support for rk3288
rockchip: clk: Add rk3328 SARADC clock support
rockchip: clk: Add rk3368 SARADC
Signed-off-by: David Wu <david...@rock-chips.com>
---
arch/arm/dts/rk3328-evb.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts
index 8a14c65..df44ccb 100644
--- a/arch/arm/dts/rk3328-evb.dts
+++ b/arch/arm/dts/rk3328-e
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