Add IOM_GRP register definitions for i.MX6SL to allow them to be
named in DDR configuration (.cfg) files.
Signed-off-by: Eric Nelson <e...@nelint.com>
---
arch/arm/include/asm/arch-mx6/mx6sl-ddr.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/include/asm/ar
Hi Peng,
On 10/09/2016 06:48 PM, Eric Nelson wrote:
> On 10/09/2016 08:12 AM, Peng Fan wrote:
>>> On 10/09/2016 04:20 AM, Peng Fan wrote:
>>>> On Sat, Oct 08, 2016 at 05:26:18PM +0200, Eric Nelson wrote:
>>>>> On 10/08/2016 08:58 AM, Peng Fan wrote:
Hi Peng,
On 10/09/2016 08:12 AM, Peng Fan wrote:
>> On 10/09/2016 04:20 AM, Peng Fan wrote:
>>> On Sat, Oct 08, 2016 at 05:26:18PM +0200, Eric Nelson wrote:
>>>> On 10/08/2016 08:58 AM, Peng Fan wrote:
>>>>
>>>> I also don't understand why
Hi Peng,
Note the typo in the subject header.
On 10/08/2016 08:58 AM, Peng Fan wrote:
> Introduce USE_IMXIMG_PLUGIN Kconfig
>
> Signed-off-by: Peng Fan
> Cc: Stefano Babic
> Reviewed-by: Tom Rini
> ---
>
> V3:
> None
>
> V2:
> New
>
Hi Peng,
On 10/09/2016 04:20 AM, Peng Fan wrote:
> On Sat, Oct 08, 2016 at 05:26:18PM +0200, Eric Nelson wrote:
>> On 10/08/2016 08:58 AM, Peng Fan wrote:
>>
>>From what I can tell, there's no reason that you can't have multiple
>> plugins, and the use of these va
> Signed-off-by: Peng Fan <peng@nxp.com>
> Cc: Stefano Babic <sba...@denx.de>
> Cc: Eric Nelson <e...@nelint.com>
> Cc: Ye Li <ye...@nxp.com>
> Reviewed-by: Tom Rini <tr...@konsulko.com>
> ---
>
> V3:
> Fix compile error.
>
> V2:
> D
Hi Tom,
On 09/06/2016 07:15 AM, Tom Rini wrote:
> On Tue, Sep 06, 2016 at 07:00:56AM -0700, Eric Nelson wrote:
>> On 09/06/2016 06:40 AM, Tom Rini wrote:
>>> On Fri, Sep 02, 2016 at 10:53:58PM +0200, Petr Kulhavy wrote:
>>>
>>> Would it be possible to
t;>> CONFIG_SPL_YMODEM_SUPPORT is set.
>>>
>>> This allows to load again a SPL based board
>>> with imx_usb_loader together with a tool
>>> such as kermit.
>>>
>>> Signed-off-by: Stefano Babic <sba...@denx.de>
>>> CC: T
F_SEL = 0 --> Periodic refresh cycle: 64kHz
> REFR = 1 ---> Refresh Rate - 2 refreshes
>
> So adjust the MDREF initialization for mx6ul_evk accordingly
> to fix the kernel hang issue at low bus frequency.
>
> Reported-by: Eric Nelson <e...@nelint.com>
> Signed-off
> .rst_to_cke = 0x23,
> .sde_to_rst = 0x10,
> + .refsel = 1,/* Refresh cycles at 32KHz */
> + .refr = 7, /* 8 refresh commands per refresh cycle */
> };
>
> static void ccgr_init(void)
> diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c
&g
cy */
> + .walat = 0, /* Write additional latency */
> .ralat = 5, /* Read additional latency */
> .mif3_mode = 3, /* Command prediction working mode */
> .bi_on = 1, /* Bank interleaving enabled */
>
Reviewed-by: Eric Nelson <e...@nelint.com>
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
On 08/29/2016 01:59 PM, Fabio Estevam wrote:
> Hi Eric,
>
> On Mon, Aug 29, 2016 at 5:56 PM, Eric Nelson <e...@nelint.com> wrote:
>
>>> /* Step 12: Configure and activate periodic refresh */
>>> - mmdc0->mdref = (1 << 14
Hi Fabio,
On 08/29/2016 01:35 PM, Fabio Estevam wrote:
> From: Fabio Estevam
>
> Currently MX6 SPL DDR initialization hardcodes the REF_SEL and
> REFR fields of the MDREF register as 1 and 7, respectively.
>
> Looking at the MDREF initialization done via DCD we see that
Hi Fabio,
On 08/29/2016 12:53 PM, Fabio Estevam wrote:
> Hi Eric,
>
> On Mon, Aug 29, 2016 at 3:48 PM, Eric Nelson <e...@nelint.com> wrote:
>
>> I think this commit message needs work.
>>
>> "we have" seems to mean that the NXP U-Boot fork has
Hi Fabio,
On 08/29/2016 11:48 AM, Eric Nelson wrote:
> Hi Fabio,
>
> On 08/29/2016 10:56 AM, Fabio Estevam wrote:
>> From: Fabio Estevam <fabio.este...@nxp.com>
>>
>> When running a NXP 4.1 kernel with U-Boot mainline we observe a
>> hang when going into
Thanks very much for your efforts Fabio,
On 08/29/2016 11:06 AM, Fabio Estevam wrote:
> Hi Eric,
>
> On Mon, Aug 29, 2016 at 2:14 PM, Eric Nelson <e...@nelint.com> wrote:
>
>> Things are working well using your config patch:
>> http://pastebin.com/crAe
ms to mean that the NXP U-Boot fork has this
setting, but this isn't an explanation of why.
> DATA 4 0x021B0020 0x0800
>
> ,which means:
>
> REF_SEL = 0 -->Periodic refresh cycle: 64kHz
> REFR = 1 ---> Refresh Rate - 2 refreshes
>
> So adjust the MDREF initial
42,11 +842,11 @@ static void spl_dram_init(void)
>
> void board_init_f(ulong dummy)
> {
> + ccgr_init();
> +
> /* setup AIPS and disable watchdog */
> arch_cpu_init();
>
> - ccgr_init();
> -
> /* iomux and setup of i2c */
&g
Hi Fabio,
On 08/29/2016 10:00 AM, Eric Nelson wrote:
> On 08/29/2016 04:58 AM, Fabio Estevam wrote:
>> On Mon, Aug 29, 2016 at 12:20 AM, Fabio Estevam <feste...@gmail.com> wrote:
>>> From: Fabio Estevam <fabio.este...@nxp.com>
>>>
>>> When runnin
ve a
>> hang when going into the lowest operational point of cpufreq.
>>
>> Comparing the DDR calibration values against NXP U-Boot showed
>> that the values were incorrect.
>>
>> Adjust the calibration values so that we can avoid such system hang.
>&
*src, int len,
>
> s.next_in = src + i;
> s.avail_in = payload_size+8;
> - writebuf = (unsigned char *)malloc(szwritebuf);
> + writebuf = (unsigned char *)malloc_cache_aligned(szwritebuf);
>
> /* decompress until deflate stream ends or end of file */
>
Hi Fabio,
On 08/28/2016 07:47 PM, Fabio Estevam wrote:
> On Sun, Aug 28, 2016 at 6:04 PM, Eric Nelson <e...@nelint.com> wrote:
>> On 08/28/2016 01:59 PM, Eric Nelson wrote:
>>> Hi Fabio, Peng, and all.
>>>
>>> I just ran into a problem with bus frequency
On 08/28/2016 01:59 PM, Eric Nelson wrote:
> Hi Fabio, Peng, and all.
>
> I just ran into a problem with bus frequency switching
> on the EVK and there appears to be a U-Boot component.
>
> Using the 4.1.15 kernel from git.freescale.com (commit a4d2a08)
> and the latest U-Bo
Hi Fabio, Peng, and all.
I just ran into a problem with bus frequency switching
on the EVK and there appears to be a U-Boot component.
Using the 4.1.15 kernel from git.freescale.com (commit a4d2a08)
and the latest U-Boot from Stefano's imx tree (commit a3e5519)
causes the EVK to hang during a
Hi Tim,
On 08/26/2016 08:00 AM, Tim Harvey wrote:
> On Tue, Jun 21, 2016 at 11:41 AM, Eric Nelson <e...@nelint.com> wrote:
>> This patch set makes use of the dynamic DDR calibration routines added in
>> commit
>> d339f16 to define an alternative to the Frees
Hi Gary,
On 08/24/2016 03:12 AM, Gary Bisson wrote:
> Hi Eric, all,
>
> On Tue, Aug 23, 2016 at 05:24:48PM -0700, Eric Nelson wrote:
>> Nicely done Gary!
>>
>> On 08/23/2016 02:55 PM, Gary Bisson wrote:
>>> So the option can easily be selected through men
Hi Gary,
On 08/23/2016 02:55 PM, Gary Bisson wrote:
> Selecting the proper options to enable the build of the HAB tools.
>
> Also adding a CSF section to the imx final image so it can contain
> the signature information.
>
> Note, this support is disabled by default, one will have to select
>
Hi Gary and Peng,
On 08/23/2016 02:55 PM, Gary Bisson wrote:
> From: Peng Fan
>
> This commit "2bb014820c49a63902103bac710bc86b5772e843"
> do some clean up to use the code in lib/time.c.
> But usec2ticks is still being used by security related job ring code.
> Bring back
Nicely done Gary!
On 08/23/2016 02:55 PM, Gary Bisson wrote:
> So the option can easily be selected through menuconfig.
>
> Signed-off-by: Gary Bisson
> ---
> arch/arm/imx-common/Kconfig | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git
Only a single pad is changed to change sdhc2_dat3 from an
SDIO pin to and from GPIO4:5, so remove the array and use
the imx_iomux_v3_setup_pad() routine.
Signed-off-by: Eric Nelson <e...@nelint.com>
---
board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 24 ++-
On 06/22/2016 04:57 PM, Marek Vasut wrote:
> On 06/23/2016 01:52 AM, Eric Nelson wrote:
>> Hi Marek,
>>
>> On 06/22/2016 04:18 PM, Marek Vasut wrote:
>>> On 06/21/2016 08:41 PM, Eric Nelson wrote:
>>>> Allow the calibration data from mmdc_do_write_level_ca
Hi Marek,
On 06/22/2016 04:18 PM, Marek Vasut wrote:
> On 06/21/2016 08:41 PM, Eric Nelson wrote:
>> Allow the calibration data from mmdc_do_write_level_calibration
>> and mmdc_do_dqs_calibration to be returned to the caller for
>> display.
>>
>> Signed-off
Signed-off-by: Eric Nelson <e...@nelint.com>
---
arch/arm/cpu/armv7/mx6/Kconfig | 5 +
arch/arm/cpu/armv7/mx6/ddr.c| 2 +-
arch/arm/include/asm/arch-mx6/mx6-ddr.h | 2 +-
3 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/Kconfig
On 06/21/2016 11:41 AM, Eric Nelson wrote:
> This patch set makes use of the dynamic DDR calibration routines added in
> commit
> d339f16 to define an alternative to the Freescale DDR stress tester tool.
>
Hi all,
While preparing this patch set, I thought again about the t
Signed-off-by: Eric Nelson <e...@nelint.com>
---
Note that I haven't tested this board because I don't currently have one.
configs/mx6memcal_warpboard_defconfig | 32
1 file changed, 32 insertions(+)
create mode 100644 configs/mx6memcal_warpboard_defconfig
Signed-off-by: Eric Nelson <e...@nelint.com>
---
board/kosagi/novena/novena_spl.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/kosagi/novena/novena_spl.c b/board/kosagi/novena/novena_spl.c
index 9b18187..39b846f 100644
--- a/board/kosagi/novena/novena_spl.c
for a board that
isn't supported in main-line U-Boot (nitrogen6_max).
Eric Nelson (12):
imx: mx6: ddr: return output of calibration routines
novena: supply calibration parameter to DDR calibration routines
imx: mx6: ddr: make calibration optional in config routines
imx: mx6: ddr: pass
Signed-off-by: Eric Nelson <e...@nelint.com>
---
arch/arm/cpu/armv7/mx6/ddr.c | 44
1 file changed, 24 insertions(+), 20 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index bde6fe3..eb2d000 100644
--- a/ar
Signed-off-by: Eric Nelson <e...@nelint.com>
---
configs/mx6memcal_mx6slevk_defconfig | 30 ++
1 file changed, 30 insertions(+)
create mode 100644 configs/mx6memcal_mx6slevk_defconfig
diff --git a/configs/mx6memcal_mx6slevk_defconfig
b/c
_defconfig configures the board for use with
mx6sabresd or mx6qsabreauto.
Signed-off-by: Eric Nelson <e...@nelint.com>
---
arch/arm/cpu/armv7/mx6/Kconfig| 9 +
board/freescale/mx6memcal/Kconfig | 135 ++
board/freescale/mx6memcal/MAINTAINERS | 7 +
board/freescale/mx
Signed-off-by: Eric Nelson <e...@nelint.com>
---
configs/mx6memcal_sabrelite_defconfig | 27 +++
1 file changed, 27 insertions(+)
create mode 100644 configs/mx6memcal_sabrelite_defconfig
diff --git a/configs/mx6memcal_sabrelite_defconfig
b/c
Signed-off-by: Eric Nelson <e...@nelint.com>
---
board/kosagi/novena/novena_spl.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/kosagi/novena/novena_spl.c b/board/kosagi/novena/novena_spl.c
index f779bb4..9b18187 100644
--- a/board/kosagi/novena/novena_spl.c
Signed-off-by: Eric Nelson <e...@nelint.com>
---
configs/mx6memcal_nitrogen6_max_defconfig | 26 ++
1 file changed, 26 insertions(+)
create mode 100644 configs/mx6memcal_nitrogen6_max_defconfig
diff --git a/configs/mx6memcal_nitrogen6_max_defconfig
b/c
Allow the calibration data from mmdc_do_write_level_calibration
and mmdc_do_dqs_calibration to be returned to the caller for
display.
Signed-off-by: Eric Nelson <e...@nelint.com>
---
arch/arm/cpu/armv7/mx6/ddr.c| 29 +++--
arch/arm/include/asm/arch-m
Signed-off-by: Eric Nelson <e...@nelint.com>
---
configs/novena_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/novena_defconfig b/configs/novena_defconfig
index 69e5ea9..207e8eb 100644
--- a/configs/novena_defconfig
+++ b/configs/novena_defconfig
@@ -1,5 +1,6 @@
CONF
() and assumed
64-bit support in mmdc_do_write_level_calibration().
This allows the use of the DDR calibration routines on CPU variants
like i.MX6SL that only have a single MMDC port.
Signed-off-by: Eric Nelson <e...@nelint.com>
---
arch/arm/cpu/armv7/mx6/ddr.c
ecific versions in a
handful of drivers and simplify the addition of new drivers.
Signed-off-by: Eric Nelson <e...@nelint.com>
Reviewed-by: Stephen Warren <swar...@nvidia.com>
---
V2 removes parsing of offset from the gpio_find_and_xlate routine,
and only parses the offset and GPIO_AC
Thanks Stephen,
On 04/21/2016 10:03 AM, Stephen Warren wrote:
> On 04/20/2016 09:37 AM, Eric Nelson wrote:
>> Many drivers use a common form of offset + flags for device
>> tree nodes. e.g.:
>> < 2 GPIO_ACTIVE_LOW>
>>
>> This patch adds a common
This patch adds the IOMUX setting for using SD1_DAT5 as GPIO5:9.
Signed-off-by: Eric Nelson <e...@nelint.com>
---
arch/arm/include/asm/arch-mx6/mx6sl_pins.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
b/arch/arm/include/asm/ar
With the addition of GPIO_ACTIVE_LOW parsing in gpio-uclass,
the omap gpio driver doesn't need a custom xlate routine.
Signed-off-by: Eric Nelson <e...@nelint.com>
Acked-by: Simon Glass <s...@chromium.org>
---
V2 removes the include of
drivers/gpio/omap_gpio.c | 11 ---
1
Hi Simon,
On 04/20/2016 07:40 AM, Simon Glass wrote:
> Hi Eric,
>
> On 11 April 2016 at 11:17, Eric Nelson <e...@nelint.com> wrote:
>> On 04/11/2016 09:53 AM, Simon Glass wrote:
>>> On 11 April 2016 at 10:10, Stephen Warren <swar...@wwwdotorg.org> wrote:
>
ecific versions in a
handful of drivers and simplify the addition of new drivers.
Signed-off-by: Eric Nelson <e...@nelint.com>
---
V2 removes parsing of offset from the gpio_find_and_xlate routine,
and only parses the offset and GPIO_ACTIVE_LOW flag when a
driver-specific xlate is unavailab
With the addition of GPIO_ACTIVE_LOW parsing in gpio-uclass,
the pic32 gpio driver doesn't need a custom xlate routine.
Signed-off-by: Eric Nelson <e...@nelint.com>
Acked-by: Simon Glass <s...@chromium.org>
Reviewed-by: Purna Chandra Mandal <purna.man...@microchip.com>
---
V2 r
With the addition of GPIO_ACTIVE_LOW parsing in gpio-uclass,
the Exynos/S5P gpio driver doesn't need a custom xlate routine.
Signed-off-by: Eric Nelson <e...@nelint.com>
Acked-by: Simon Glass <s...@chromium.org>
Acked-by: Minkyu Kang <mk7.k...@samsung.com>
---
V2 removes the in
With the addition of GPIO_ACTIVE_LOW parsing in gpio-uclass,
the Rockchip gpio driver doesn't need a custom xlate routine.
Signed-off-by: Eric Nelson <e...@nelint.com>
Acked-by: Simon Glass <s...@chromium.org>
---
V2 removes the include of
drivers/gpio/rk_gpio.c | 11 ---
xlate is still needed.
[1] - http://lists.denx.de/pipermail/u-boot/2016-March/thread.html#249946
[2] - https://patchwork.ozlabs.org/patch/597363/
Eric Nelson (7):
dm: gpio: handle GPIO_ACTIVE_LOW flag in DT
gpio: intel_broadwell: remove gpio_xlate routine
gpio: omap: remove gpio_xlate
With the addition of GPIO_ACTIVE_LOW parsing in gpio-uclass,
the intel_broadwell driver doesn't need a custom xlate routine.
Signed-off-by: Eric Nelson <e...@nelint.com>
Acked-by: Simon Glass <s...@chromium.org>
---
Nothing changed in V2.
drivers/gpio/intel_broadwell_gpio.c | 10 -
Hi Fabio,
On 04/19/2016 05:45 PM, Fabio Estevam wrote:
> Hi Eric,
>
> On Tue, Apr 19, 2016 at 9:21 PM, Eric Nelson <e...@nelint.com> wrote:
>
>> Do you have details of which cards are failing and how?
>
> The brand that fails is SanDisk 8GB microSD HC I (4).
>
Hi Fabio,
On 04/19/2016 01:13 PM, Fabio Estevam wrote:
> On Tue, Apr 19, 2016 at 4:22 PM, Otavio Salvador
> wrote:
>
>> This is a huge step back; why it cannot be fixed in the SPL properly?
>
> Maybe it can, but as explained in the commit log, there is no such
Thanks Stephen,
On 04/12/2016 09:45 AM, Stephen Warren wrote:
> On 04/11/2016 04:21 PM, Eric Nelson wrote:
>> Call blk_dwrite to ensure that the block cache is notified
>> if enabled and remove build breakage when CONFIG_BLK is enabled.
>
> Reviewed-by: Stephen Warre
Call blk_dwrite to ensure that the block cache is notified
if enabled and remove build breakage when CONFIG_BLK is enabled.
Signed-off-by: Eric Nelson <e...@nelint.com>
---
lib/gunzip.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/lib/gunzip.c b/lib/gunzip.c
ecific versions in a
handful of drivers and simplify the addition of new drivers.
Signed-off-by: Eric Nelson <e...@nelint.com>
Acked-by: Stephen Warren <swar...@wwwdotorg.org>
---
V2 removes parsing of offset from the gpio_find_and_xlate routine,
and only parses the offset and GPIO_AC
Hi Stephen,
On 04/11/2016 10:16 AM, Stephen Warren wrote:
> On 04/11/2016 11:00 AM, Eric Nelson wrote:
>> Many drivers use a common form of offset + flags for device
>> tree nodes. e.g.:
>> < 2 GPIO_ACTIVE_LOW>
>>
>> This patch adds a common implementati
On 04/11/2016 09:53 AM, Simon Glass wrote:
> Hi,
>
> On 11 April 2016 at 10:10, Stephen Warren <swar...@wwwdotorg.org> wrote:
>> On 04/11/2016 09:12 AM, Simon Glass wrote:
>>>
>>> Hi Eric,
>>>
>>> On 11 April 2016 at 09:10, Eric Nelson <
With the addition of GPIO_ACTIVE_LOW parsing in gpio-uclass,
the Exynos/S5P gpio driver doesn't need a custom xlate routine.
Signed-off-by: Eric Nelson <e...@nelint.com>
Acked-by: Simon Glass <s...@chromium.org>
---
V2 removes the include of
drivers/gpio/s5p_gpio.c | 11 ---
ecific versions in a
handful of drivers and simplify the addition of new drivers.
Signed-off-by: Eric Nelson <e...@nelint.com>
---
drivers/gpio/gpio-uclass.c | 26 +++---
include/asm-generic/gpio.h | 19 ++-
2 files changed, 33 insertions(+), 12 deletions(-)
With the addition of GPIO_ACTIVE_LOW parsing in gpio-uclass,
the omap gpio driver doesn't need a custom xlate routine.
Signed-off-by: Eric Nelson <e...@nelint.com>
Acked-by: Simon Glass <s...@chromium.org>
---
V2 removes the include of
drivers/gpio/omap_gpio.c | 11 ---
1
ch set removes parsing of offset from the gpio_find_and_xlate
routine, and only parses the offset and GPIO_ACTIVE_LOW flag when a
driver-specific xlate is unavailable.
V2 also drops the update to the tegra_gpio driver.
Eric Nelson (6):
dm: gpio: add a default gpio xlate routine
gpio: intel_bro
With the addition of GPIO_ACTIVE_LOW parsing in gpio-uclass,
the pic32 gpio driver doesn't need a custom xlate routine.
Signed-off-by: Eric Nelson <e...@nelint.com>
Acked-by: Simon Glass <s...@chromium.org>
---
V2 removes the include of
drivers/gpio/pic32_gpio.c | 10 --
1
With the addition of GPIO_ACTIVE_LOW parsing in gpio-uclass,
the Rockchip gpio driver doesn't need a custom xlate routine.
Signed-off-by: Eric Nelson <e...@nelint.com>
Acked-by: Simon Glass <s...@chromium.org>
---
V2 removes the include of
drivers/gpio/rk_gpio.c | 11 ---
With the addition of GPIO_ACTIVE_LOW parsing in gpio-uclass,
the intel_broadwell driver doesn't need a custom xlate routine.
Signed-off-by: Eric Nelson <e...@nelint.com>
Acked-by: Simon Glass <s...@chromium.org>
---
Nothing changed in V2.
drivers/gpio/intel_broadwell_gpio.c | 10 -
Hi Simon,
On 04/11/2016 07:59 AM, Simon Glass wrote:
> On 11 April 2016 at 08:55, Eric Nelson <e...@nelint.com> wrote:
>> On 04/11/2016 07:47 AM, Simon Glass wrote:
>>> On 10 April 2016 at 08:48, Eric Nelson <e...@nelint.com> wrote:
>>>> On 04/09/2016 11:
Hi Peng,
On 04/10/2016 10:28 PM, Peng Fan wrote:
> On Tue, Mar 15, 2016 at 09:32:51PM -0600, Simon Glass wrote:
>> On 14 March 2016 at 23:48, Peng Fan wrote:
>>> To i.MX controller, we use such as "< 3 GPIO_ACTIVE_LOW>" for
>>> a device to refer a gpio pin in device tree.
Hi Simon,
On 04/11/2016 07:47 AM, Simon Glass wrote:
> Hi Eric,
>
> On 10 April 2016 at 08:48, Eric Nelson <e...@nelint.com> wrote:
>> Hi Simon,
>>
>> On 04/09/2016 11:33 AM, Simon Glass wrote:
>>> On 4 April 2016 at 11:50, Stephen Warren <swar...@w
On 04/10/2016 07:45 AM, Eric Nelson wrote:
> On 04/09/2016 11:34 AM, Simon Glass wrote:
>> On 5 April 2016 at 16:09, Stephen Warren <swar...@wwwdotorg.org> wrote:
>>> On 04/01/2016 09:47 AM, Eric Nelson wrote:
>>>>
>>>> With the ad
Hi Simon,
On 04/09/2016 11:33 AM, Simon Glass wrote:
> On 4 April 2016 at 11:50, Stephen Warren <swar...@wwwdotorg.org> wrote:
>> On 04/03/2016 08:07 AM, Eric Nelson wrote:
>>> On 04/02/2016 08:37 PM, Stephen Warren wrote:
>>>> On 04/02/2016 09:13 AM, Eric Nel
Thanks for the feedback Simon.
On 04/09/2016 11:34 AM, Simon Glass wrote:
> On 5 April 2016 at 16:09, Stephen Warren <swar...@wwwdotorg.org> wrote:
>> On 04/01/2016 09:47 AM, Eric Nelson wrote:
>>>
>>> With the addition of GPIO_ACTIVE_LOW parsing in gpio-ucla
Hi Simon,
On 04/09/2016 10:55 AM, Simon Glass wrote:
> On 20 March 2016 at 16:54, Eric Nelson <e...@nelint.com> wrote:
>> On 03/20/2016 03:13 PM, Tom Rini wrote:
>>> On Sun, Mar 20, 2016 at 12:35:53PM -0700, Eric Nelson wrote:
>>>> On 03/17/2016 02:23 PM, Steph
Hi Stephen and Peng,
On 04/02/2016 08:37 PM, Stephen Warren wrote:
> On 04/02/2016 09:13 AM, Eric Nelson wrote:
>> On 04/01/2016 10:46 PM, Peng Fan wrote:
>>> On Thu, Mar 31, 2016 at 01:41:04PM -0700, Eric Nelson wrote:
>>>> On 03/28/2016 09:57 PM, Peng Fan wrote:
&g
Hi Peng,
On 04/01/2016 10:46 PM, Peng Fan wrote:
> On Thu, Mar 31, 2016 at 01:41:04PM -0700, Eric Nelson wrote:
>> On 03/28/2016 09:57 PM, Peng Fan wrote:
>>> On Fri, Mar 25, 2016 at 01:12:11PM -0700, Eric Nelson wrote:
>>>> Device tree parsing of GPIO nod
Signed-off-by: Eric Nelson <e...@nelint.com>
---
cmd/blkcache.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/cmd/blkcache.c b/cmd/blkcache.c
index d97bed5..1338dbd 100644
--- a/cmd/blkcache.c
+++ b/cmd/blkcache.c
@@ -73,12 +73,10 @@ static int do_blkcache(cmd
Signed-off-by: Eric Nelson <e...@nelint.com>
---
include/blk.h | 34 ++
1 file changed, 14 insertions(+), 20 deletions(-)
diff --git a/include/blk.h b/include/blk.h
index 263a791..f624671 100644
--- a/include/blk.h
+++ b/include/blk.h
@@ -96,10 +96,9 @@
Signed-off-by: Eric Nelson <e...@nelint.com>
---
cmd/blkcache.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/cmd/blkcache.c b/cmd/blkcache.c
index 725163a..d97bed5 100644
--- a/cmd/blkcache.c
+++ b/cmd/blkcache.c
@@ -16,11 +16,11 @@ static int blkc_show(cmd
This set of updates addresses a number of small coding style
issues caught by Stephen Warren's review of the block cache
patch set.
Eric Nelson (3):
cmd: blkcache: remove indentation from output of 'show'
cmd: blkcache: simplify sub-command handling
drivers: block: formatting: fix placement
Hi Stephen,
On 04/01/2016 07:07 PM, Stephen Warren wrote:
> On 04/01/2016 05:16 PM, Eric Nelson wrote:
>> On 04/01/2016 03:57 PM, Stephen Warren wrote:
>>> On 03/31/2016 02:24 PM, Eric Nelson wrote:
>>>> On 03/30/2016 02:57 PM, Stephen Warren wrote:
>>>>&
Hi Tom,
On 04/01/2016 06:59 PM, Tom Rini wrote:
> On Mon, Mar 28, 2016 at 10:05:44AM -0700, Eric Nelson wrote:
>
>> Add a block device cache to speed up repeated reads of block devices by
>> various filesystems.
>>
>> This small amount of cache can dramatically spe
On 04/01/2016 04:41 PM, Tom Rini wrote:
> On Fri, Apr 01, 2016 at 04:16:42PM -0700, Eric Nelson wrote:
>> Hi Stephen,
>>
>> On 04/01/2016 03:57 PM, Stephen Warren wrote:
>>> On 03/31/2016 02:24 PM, Eric Nelson wrote:
>>>> On 03/30/2016 02:57 PM, Stephen
Hi Stephen,
On 04/01/2016 03:57 PM, Stephen Warren wrote:
> On 03/31/2016 02:24 PM, Eric Nelson wrote:
>> On 03/30/2016 02:57 PM, Stephen Warren wrote:
>>> On 03/30/2016 11:34 AM, Eric Nelson wrote:
>>>> On 03/30/2016 07:36 AM, Stephen Warren wrote:
>>>>&
With the addition of GPIO_ACTIVE_LOW parsing in gpio-uclass, it is
no longer necessary for the tegra-specific xlate function to do this.
Signed-off-by: Eric Nelson <e...@nelint.com>
---
drivers/gpio/tegra_gpio.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpio/tegra_gp
of the driver-specific xlate routines.
Signed-off-by: Eric Nelson <e...@nelint.com>
---
drivers/gpio/gpio-uclass.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
index b58d4e6..a3cbb83 100644
--- a/drivers/gpi
xlate is still needed.
[1] - http://lists.denx.de/pipermail/u-boot/2016-March/thread.html#249946
[2] - https://patchwork.ozlabs.org/patch/597363/
Eric Nelson (7):
dm: gpio: handle GPIO_ACTIVE_LOW flag in DT
gpio: intel_broadwell: remove gpio_xlate routine
gpio: omap: remove gpio_xlate
With the addition of GPIO_ACTIVE_LOW parsing in gpio-uclass,
the omap gpio driver doesn't need a custom xlate routine.
Signed-off-by: Eric Nelson <e...@nelint.com>
---
drivers/gpio/omap_gpio.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/drivers/gpio/omap_gpio.c b/driver
With the addition of GPIO_ACTIVE_LOW parsing in gpio-uclass,
the Exynos/S5P gpio driver doesn't need a custom xlate routine.
Signed-off-by: Eric Nelson <e...@nelint.com>
---
drivers/gpio/s5p_gpio.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/drivers/gpio/s5p_gpio.c b/d
With the addition of GPIO_ACTIVE_LOW parsing in gpio-uclass,
the pic32 gpio driver doesn't need a custom xlate routine.
Signed-off-by: Eric Nelson <e...@nelint.com>
---
drivers/gpio/pic32_gpio.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/drivers/gpio/pic32_gpio.c b/driver
With the addition of GPIO_ACTIVE_LOW parsing in gpio-uclass,
the intel_broadwell driver doesn't need a custom xlate routine.
Signed-off-by: Eric Nelson <e...@nelint.com>
---
drivers/gpio/intel_broadwell_gpio.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/driver
With the addition of GPIO_ACTIVE_LOW parsing in gpio-uclass,
the Rockchip gpio driver doesn't need a custom xlate routine.
Signed-off-by: Eric Nelson <e...@nelint.com>
---
drivers/gpio/rk_gpio.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/drivers/gpio/rk_gpio.c b/driver
Hi Peng,
On 03/28/2016 09:57 PM, Peng Fan wrote:
> Hi Eric,
>
> On Fri, Mar 25, 2016 at 01:12:11PM -0700, Eric Nelson wrote:
>> Device tree parsing of GPIO nodes is currently ignoring flags.
>>
>> Add support for GPIO_ACTIVE_LOW by checking for the presence
>>
Hi Stephen,
On 03/30/2016 02:57 PM, Stephen Warren wrote:
> On 03/30/2016 11:34 AM, Eric Nelson wrote:
>> Thanks again for the detailed review, Stephen.
>>
>> On 03/30/2016 07:36 AM, Stephen Warren wrote:
>>> On 03/28/2016 11:05 AM, Eric Nelson wrote:
>>>
Hi Tom,
On 03/30/2016 08:19 AM, Tom Rini wrote:
> On Wed, Mar 30, 2016 at 08:36:21AM -0600, Stephen Warren wrote:
>> On 03/28/2016 11:05 AM, Eric Nelson wrote:
>>> Add a block device cache to speed up repeated reads of block devices by
>>> various filesystems.
>&
Thanks again for the detailed review, Stephen.
On 03/30/2016 07:36 AM, Stephen Warren wrote:
> On 03/28/2016 11:05 AM, Eric Nelson wrote:
>> Add a block device cache to speed up repeated reads of block devices by
>> various filesystems.
>>
>> +
>
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