There is a workaround for MPC8569 CPU Errata, which needs to set Bit 13 of LBCR
in 4K bootpage. We setup a temp TLB for eLBC controller in bootpage, then
invalidate it after LBCR bit 13 is set.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
cpu/mpc85xx/Makefile |1 +
cpu
This patch adds MPC8569MDS board support. The UART, QE UEC1 and UEC2, BRD
EEPROM on I2C2 bus, PCI express and DDR3 SPD are supported in this patch.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
Signed-off-by: Hillel Avni hillel.a...@freescale.com
---
MAKEALL
For the silicon which doesn't have ROM support in QE, it always needs to load
a pre-built ucode binary to IRAM so that QE can work.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
Signed-off-by: Hillel Avni hillel.a...@freescale.com
---
drivers/qe/qe.c |9 +
drivers/qe/qe.h
There is a workaround for MPC8569 CPU Errata, which needs to set Bit 13 of LBCR
in 4K bootpage. We setup a temp TLB for eLBC controller in bootpage, then
invalidate it after LBCR bit 13 is set.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
cpu/mpc85xx/Makefile |1 +
cpu
This patch adds MPC8569MDS board support. The UART, QE UEC1 and UEC2, BRD
EEPROM on I2C2 bus, PCI express and DDR3 SPD are supported in this patch.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
Signed-off-by: Hillel Avni hillel.a...@freescale.com
---
MAKEALL
On Wed, 2009-01-28 at 09:33 +0100, Wolfgang Denk wrote:
Dear Andy Haiying,
in message 1232753424-2863-1-git-send-email-aflem...@freescale.com you
wrote:
are available in the git repository at:
...
Haiying Wang (2):
Add README file for MPC8572DS board
Add secondary CPUs
Acked-by: Haiying Wang haiying.w...@freescale.com
On Wed, 2009-01-28 at 08:31 -0600, Kumar Gala wrote:
Configuring for MPC8540EVAL board...
mpc8540eval.c: In function 'checkboard':
mpc8540eval.c:53: error: invalid operands to binary /
make[1]: *** [mpc8540eval.o] Error 1
Signed-off
So that we can locate the DDR tlb start entry to the value other than 8. By
default, it is still 8.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
cpu/mpc85xx/tlb.c |6 +-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c
This patch updates e500 freqProcessor to array based on CONFIG_NUM_CPUS,
and prints each CPU's frequency separately. It also fixes up each CPU's
frequency in clock-frequency of fdt blob.
Signed-off-by: James Yang [EMAIL PROTECTED]
Signed-off-by: Haiying Wang [EMAIL PROTECTED]
---
This patch has
This patch updates e500 freqProcessor to array based on CONFIG_NUM_CPUS,
and prints each CPU's frequency separately. It also fixes up each CPU's
frequency in clock-frequency of fdt blob.
Signed-off-by: James Yang [EMAIL PROTECTED]
Signed-off-by: Haiying Wang [EMAIL PROTECTED]
---
This patch has
Signed-off-by: Haiying Wang [EMAIL PROTECTED]
---
doc/README.mpc8572ds | 167 ++
1 files changed, 167 insertions(+), 0 deletions(-)
create mode 100644 doc/README.mpc8572ds
diff --git a/doc/README.mpc8572ds b/doc/README.mpc8572ds
new file mode
MPC8572DS has two i2c buses. This patch moves the DDR SPD_EEPROM to i2c bus 1
according to the board spec, and adds the 2nd i2c bus offset.
Signed-off-by: Haiying Wang [EMAIL PROTECTED]
---
include/configs/MPC8572DS.h |8 ++--
1 files changed, 6 insertions(+), 2 deletions(-)
diff --git
Fix some bugs:
1. Correctly set intlv_ctl in cs_config.
2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
3. Set base_address and total memory for each ddr controller in memory
controller interleaving mode.
Signed-off-by: Haiying Wang [EMAIL PROTECTED]
---
cpu
Current new DDR code has included DDR interleaving support but has not
been tested out. The following patches fix the bugs for common code,
enable run time configuration of memory controller interleaving mode and
bank interleaving mode and add board specific parameters table to
decides the ddr
/cpu to /include directory.
* add ddr dimm parameters to populate board specific options.
* Fix fsl_ddr_board_options() for all the 8xxx boards which call this function.
Signed-off-by: Haiying Wang [EMAIL PROTECTED]
---
board/atum8548/ddr.c |5 ++-
board/freescale/mpc8536ds
* Check DDR interleaving mode from environment by reading memctl_intlv_ctl and
ba_intlv_ctl.
* Print DDR interleaving mode information
* Add doc/README.fsl-ddr to describe the interleaving setting
Signed-off-by: Haiying Wang [EMAIL PROTECTED]
---
cpu/mpc8xxx/ddr/main.c| 37
Signed-off-by: Haiying Wang [EMAIL PROTECTED]
---
cpu/mpc8xxx/ddr/ctrl_regs.c | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index 6297141..1783e92 100644
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu
) interleaving mode by default, because the default on-board
DDR DIMMs are 2x512MB single-rank.
* Change CONFIG_ICS307_REFCLK_HZ from to 3000.
Signed-off-by: James Yang [EMAIL PROTECTED]
Signed-off-by: Haiying Wang [EMAIL PROTECTED]
---
board/freescale/mpc8572ds/ddr.c | 123
Fix some bugs:
1. Correctly set intlv_ctl in cs_config.
2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
3. Set base_address and total memory for each ddr controller in memory
controller interleaving mode.
Signed-off-by: Haiying Wang [EMAIL PROTECTED]
---
cpu
) interleaving mode by default, because the default on-board
DDR DIMMs are 2x512MB single-rank.
* Change CONFIG_ICS307_REFCLK_HZ from to 3000.
Signed-off-by: James Yang [EMAIL PROTECTED]
Signed-off-by: Haiying Wang [EMAIL PROTECTED]
---
board/freescale/mpc8572ds/ddr.c | 123
* Add board specific parameter table to choose correct cpo, clk_adjust,
write_data_delay based on board ddr frequency and n_ranks.
* Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#.
Signed-off-by: James Yang [EMAIL PROTECTED]
Signed-off-by: Haiying Wang [EMAIL PROTECTED]
---
board
On Sat, 2008-10-04 at 01:35 +0200, Wolfgang Denk wrote:
Dear Haiying Wang,
In message [EMAIL PROTECTED] you wrote:
Fix some bugs:
1. Correctly set intlv_ctl in cs_config.
2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
3. Set base_address and total
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