Instead of using mix of hex and decimal numbering for i/d-cache size
and line-size use unified decimal integer only.
Cc: Daniel Schwierzeck
Cc: Paul Burton
Signed-off-by: Purna Chandra Mandal
---
arch/mips/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips
only.
Cc: Jagan Teki
Signed-off-by: Purna Chandra Mandal
---
drivers/spi/Kconfig | 8 +
drivers/spi/Makefile| 1 +
drivers/spi/pic32_spi.c | 448
3 files changed, 457 insertions(+)
create mode 100644 drivers/spi/pic32_spi.c
diff --git
h/mips/lib/bootm.c inline with ARM arch.
Signed-off-by: Purna Chandra Mandal
Cc: Daniel Schwierzeck
---
arch/mips/lib/bootm.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index eed159c..aa0475a 100644
--- a/arch/mips/l
On 04/15/2016 08:53 PM, Andreas Färber wrote:
> Am 15.04.2016 um 12:59 schrieb Heiko Schocher:
>> Fix following warnings for all mips based boards:
>> mips: + pic32mzdask
>> +Warning (unit_address_vs_reg): Node /memory has a reg or ranges property,
>> but no unit name
>> +Warning (unit_ad
; };
> };
> diff --git a/arch/mips/dts/skeleton.dtsi b/arch/mips/dts/skeleton.dtsi
> index 24ee6c3..643996c 100644
> --- a/arch/mips/dts/skeleton.dtsi
> +++ b/arch/mips/dts/skeleton.dtsi
> @@ -16,7 +16,7 @@
> aliases {
> };
>
>
oesn't supply its' own xlate
> routine.
>
> This will allow removal of the driver-specific versions in a
> handful of drivers and simplify the addition of new drivers.
>
> Signed-off-by: Eric Nelson
> Acked-by: Stephen Warren
Reviewed-by: Purna Chandra Mandal
__
On 04/11/2016 10:30 PM, Eric Nelson wrote:
> With the addition of GPIO_ACTIVE_LOW parsing in gpio-uclass,
> the pic32 gpio driver doesn't need a custom xlate routine.
>
> Signed-off-by: Eric Nelson
> Acked-by: Simon Glass
Reviewed-by:
On 03/21/2016 05:09 PM, Marek Vasut wrote:
> On 03/21/2016 12:19 PM, Purna Chandra Mandal wrote:
>> On 03/21/2016 04:49 PM, Marek Vasut wrote:
>>
>>> On 03/21/2016 08:35 AM, Purna Chandra Mandal wrote:
>>>> ARM defines __raw_writes[bwql], __raw_reads[bwql] in ar
On 03/21/2016 04:49 PM, Marek Vasut wrote:
> On 03/21/2016 08:35 AM, Purna Chandra Mandal wrote:
>> ARM defines __raw_writes[bwql], __raw_reads[bwql] in arch io.h
>> but not the writes[bwql], reads[bwql] needed by some drivers.
>>
>> Signed-off-by: Purna Chandra Mand
Enable MUSB host and USB storage support for Microchip
PIC32MZ[DA] Starter Kit.
Signed-off-by: Purna Chandra Mandal
---
Changes in v5: None
Changes in v4:
- dts: add USB clock to musb node
- add missing CONFIG_PIC32_USB in defconfig
Changes in v3:
- add arch specific reads{bwlq}, writes{bwlq
This driver adds support of PIC32 MUSB OTG controller as dual role device.
It implements platform specific glue to reuse musb core.
Signed-off-by: Cristian Birsan
Signed-off-by: Purna Chandra Mandal
---
Changes in v5:
- drop OR'ing irqreturn_t in pic32_interrupt().
Changes in v4:
Definition of writes{bwlq}, reads{bwlq} are now added into arch specific
asm/io.h. So removing them from driver to fix re-definition error
Signed-off-by: Purna Chandra Mandal
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/mtd/nand/pxa3xx_nand.c
pat.h seperated
- compilation fix in drivers/gadget/f_mass_storage.c seperated
Purna Chandra Mandal (4):
arm: add missing writes[bwql], reads[bwql].
drivers: remove writes{b,w,l,q} and reads{b,w,l,q}.
drivers: musb-new: Add USB DRC driver for Microchip PIC32 OTG
controller.
board: pic3
ARM defines __raw_writes[bwql], __raw_reads[bwql] in arch io.h
but not the writes[bwql], reads[bwql] needed by some drivers.
Signed-off-by: Purna Chandra Mandal
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/io.h | 7 +++
1 file
On 03/16/2016 09:18 PM, Marek Vasut wrote:
> On 03/16/2016 10:58 AM, Purna Chandra Mandal wrote:
>> On 03/15/2016 11:49 PM, Marek Vasut wrote:
>>
>>> On 03/15/2016 01:44 PM, Purna Chandra Mandal wrote:
>>>> This driver adds support of PIC32 MUSB OTG con
prefetch and cache contents to
improve execution performance. These flash can also be used to
store user data (like environment).
Flash erase and programming are handled by on-chip NVM controller.
Driver implemented driver model but MTD is not really support.
Signed-off-by: Purna Chandra Mandal
Enable MUSB host and USB storage support for Microchip
PIC32MZ[DA] Starter Kit.
Signed-off-by: Purna Chandra Mandal
---
Changes in v4:
- dts: add USB clock to musb node
- add missing CONFIG_PIC32_USB in defconfig
Changes in v3:
- add arch specific reads{bwlq}, writes{bwlq} in respective arch
ARM defines __raw_writes[bwql], __raw_reads[bwql] in arch io.h
but not the writes[bwql], reads[bwql] needed by some drivers.
Signed-off-by: Purna Chandra Mandal
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/io.h | 7 +++
1 file changed, 7 insertions
seperated
Purna Chandra Mandal (4):
arm: add missing writes[bwql], reads[bwql].
drivers: remove writes{b,w,l,q} and reads{b,w,l,q}.
drivers: musb-new: Add USB DRC driver for Microchip PIC32 OTG
controller.
board: pic32mzda: enable USB-host, USB-storage support.
arch/arm/include/asm/io.h
This driver adds support of PIC32 MUSB OTG controller as dual role device.
It implements platform specific glue to reuse musb core.
Signed-off-by: Cristian Birsan
Signed-off-by: Purna Chandra Mandal
---
Changes in v4:
- add support to handle multiple MUSB controllers.
- remove unaligned
Definition of writes{bwlq}, reads{bwlq} are now added into arch specific
asm/io.h. So removing them from drivers to fix re-definition error
Signed-off-by: Purna Chandra Mandal
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/mtd/nand/pxa3xx_nand.c | 8
Microchip PIC32 has internal parallel flash (non-CFI compliant).
These flash devices do not support any identifier command so no
standard IDs. Added unique IDs to seperate these flash devices
from others supported by U-Boot.
Signed-off-by: Purna Chandra Mandal
---
Changes in v3: None
Changes in
On 03/15/2016 05:35 PM, Jagan Teki wrote:
> On 14 March 2016 at 19:37, Purna Chandra Mandal
> wrote:
>> Jagan.
>>
>> On 03/14/2016 07:16 PM, Jagan Teki wrote:
>>
>>> On Monday 14 March 2016 07:00 PM, Purna Chandra Mandal wrote:
>>>> On 03/14/201
On 03/15/2016 11:49 PM, Marek Vasut wrote:
> On 03/15/2016 01:44 PM, Purna Chandra Mandal wrote:
>> This driver adds support of PIC32 MUSB OTG controller as dual role device.
>> It implements platform specific glue to reuse musb core.
>>
>> Signed-off-by: Cristian Birs
On 03/15/2016 11:40 PM, Marek Vasut wrote:
> On 03/15/2016 01:44 PM, Purna Chandra Mandal wrote:
>> Moved definition of writes{bwlq} and reads{bwlq} into arch.
>> There is no need of having arch specific wrapper in driver.
> And so the patch does ... what exactly ? I cannot fig
Enable MUSB host and USB storage support for Microchip
PIC32MZ[DA] Starter Kit.
Signed-off-by: Purna Chandra Mandal
---
Changes in v3:
- add arch specific reads{bwlq}, writes{bwlq} in respective arch io.h
- remove reads{bwlq}, writes{bwlq} in musb-new driver
Changes in v2:
- compilation fix
This driver adds support of PIC32 MUSB OTG controller as dual role device.
It implements platform specific glue to reuse musb core.
Signed-off-by: Cristian Birsan
Signed-off-by: Purna Chandra Mandal
---
Changes in v3: None
Changes in v2: None
drivers/usb/musb-new/Kconfig | 7 +
drivers
-by: Purna Chandra Mandal
---
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/io.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 75773bd..9d185a6 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/includ
Moved definition of writes{bwlq} and reads{bwlq} into arch.
There is no need of having arch specific wrapper in driver.
Signed-off-by: Purna Chandra Mandal
---
Changes in v3: None
Changes in v2: None
drivers/usb/musb-new/linux-compat.h | 7 ---
1 file changed, 7 deletions(-)
diff --git a
prefetch and cache contents to
improve execution performance. These flash can also be used to
store user data (like environment).
Flash erase and programming are handled by on-chip NVM controller.
Signed-off-by: Purna Chandra Mandal
---
Changes in v2:
- kconfig: add CONFIG_FLASH_PIC32 dependent on
Microchip PIC32 has internal parallel flash (non-CFI compliant).
These flash devices do not support any identifier command so no
standard IDs. Added unique IDs to seperate these flash devices
from others supported by U-Boot.
Signed-off-by: Purna Chandra Mandal
---
Changes in v2: None
include
Jagan.
On 03/14/2016 07:16 PM, Jagan Teki wrote:
> On Monday 14 March 2016 07:00 PM, Purna Chandra Mandal wrote:
>> On 03/14/2016 06:13 PM, Daniel Schwierzeck wrote:
>>> 2016-03-10 14:12 GMT+01:00 Purna Chandra Mandal
>>> :
>>>> PIC32 embedded flash banks
On 03/14/2016 06:13 PM, Daniel Schwierzeck wrote:
> 2016-03-10 14:12 GMT+01:00 Purna Chandra Mandal :
>> PIC32 embedded flash banks are memory mapped, directly read by CPU,
>> and programming (erase followed by write) operation on them are
>> handled by on-chip NVM controller
On 03/10/2016 07:11 PM, Jagan Teki wrote:
> On Thursday 10 March 2016 06:42 PM, Purna Chandra Mandal wrote:
>> PIC32 embedded flash banks are memory mapped, directly read by CPU,
>> and programming (erase followed by write) operation on them are
>> handled by on-chip NVM co
PIC32 embedded flash banks are memory mapped, directly read by CPU,
and programming (erase followed by write) operation on them are
handled by on-chip NVM controller.
Signed-off-by: Purna Chandra Mandal
---
drivers/mtd/Kconfig | 6 +
drivers/mtd/Makefile | 1 +
drivers/mtd
On 03/07/2016 09:18 PM, Daniel Schwierzeck wrote:
> 2016-03-07 14:19 GMT+01:00 Purna Chandra Mandal :
>> MIPS arch implements writes{b,w,l,q}, reads{b,w,l,q}
>> whereas other archs implement __raw version of them.
>> So defining macro writes{bwlq}() to __raw_writes{bwlq}()
ibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_ashldi3.o)
> /work/git-trees/u-boot-mips/Makefile:1171: recipe for target 'u-boot' failed
>
> One example for a failing build is Travis CI.
>
> Signed-off-by: Daniel Schwierzeck
Reviewed-by: Purna Chandra Mandal
&g
This driver adds support of PIC32 MUSB OTG controller as dual role device.
It implements platform specific glue to reuse musb core.
Signed-off-by: Cristian Birsan
Signed-off-by: Purna Chandra Mandal
---
Changes in v2: None
drivers/usb/musb-new/Kconfig | 7 +
drivers/usb/musb-new
Enable MUSB host and USB storage support for Microchip
PIC32MZ[DA] Starter Kit.
Signed-off-by: Purna Chandra Mandal
---
Changes in v2:
- compilation fix in drivers/usb/musb-new/linux-compat.h seperated
- compilation fix in drivers/gadget/f_mass_storage.c seperated
arch/mips/dts
c:245:
./arch/mips/include/asm/bitops.h:370:24: note: previous definition of
'clear_bit' was here
static __inline__ void clear_bit(int nr, volatile void * addr)
-
Fixed it by allowing default implementation of set_bit(), clear_bit()
for non MIPS.
Signed-off-by: Purna Chandra Ma
MIPS arch implements writes{b,w,l,q}, reads{b,w,l,q}
whereas other archs implement __raw version of them.
So defining macro writes{bwlq}() to __raw_writes{bwlq}()
(and similarly for reads{bwlq}) is not necessary for MIPS.
Signed-off-by: Purna Chandra Mandal
---
Changes in v2: None
drivers/usb
On 02/09/2016 06:48 PM, Marek Vasut wrote:
> On Tuesday, February 09, 2016 at 01:02:49 PM, Purna Chandra Mandal wrote:
>> From: Cristian Birsan
>>
>> This driver adds support of PIC32 MUSB OTG controller as dual role device.
>> It implements platform speci
Enable MUSB host and USB storage support for Microchip
PIC32MZ[DA] Starter Kit.
Signed-off-by: Purna Chandra Mandal
---
arch/mips/dts/pic32mzda.dtsi | 10 ++
arch/mips/dts/pic32mzda_sk.dts | 4
configs/pic32mzdask_defconfig | 6 +-
include/configs/pic32mzdask.h | 7
From: Cristian Birsan
This driver adds support of PIC32 MUSB OTG controller as dual role device.
It implements platform specific glue to reuse musb core.
Signed-off-by: Cristian Birsan
Signed-off-by: Purna Chandra Mandal
---
drivers/usb/gadget/f_mass_storage.c | 2 +
drivers/usb/musb-new
On 01/29/2016 08:42 PM, Daniel Schwierzeck wrote:
>
> Am 28.01.2016 um 11:00 schrieb Purna Chandra Mandal:
>> This adds support for Microchip PIC32MZ[DA] StarterKit board
>> based on a PIC32MZ[DA] family of microcontroller.
>>
>> Signed-off-by: Purna Chandra
ate (dts provided) physical address to MIPS kseg1 address before use
Andrei Pistirica (1):
drivers: mmc: add driver for Microchip PIC32 SDHCI controller.
Paul Thacker (1):
drivers: serial: add driver for Microchip PIC32 UART controller.
Purna Chandra Mandal (11):
MIPS: initial infrastructure f
This adds ethernet, TFTP support for PIC32MZ[DA] Starter Kit. Also
custom environment variables/scripts are added to help boot from network.
Signed-off-by: Purna Chandra Mandal
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- replace unbounded loop with wait_for_bit()
- replace
This driver implements MAC and MII layer of the ethernet controller.
Network data transfer is handled by controller internal DMA engine.
Ethernet controller is configurable through device-tree file.
Signed-off-by: Purna Chandra Mandal
---
Changes in v4:
- drop ioremap() success check
- drop
Add SMSC LAN8740 Phy support required for PIC32MZDA devices.
Signed-off-by: Purna Chandra Mandal
Reviewed-by: Tom Rini
Reviewed-by: Daniel Schwierzeck
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/net/phy/smsc.c | 10 ++
1 file changed, 10 insertions
This adds support for Microchip PIC32MZ[DA] StarterKit board
based on a PIC32MZ[DA] family of microcontroller.
Signed-off-by: Purna Chandra Mandal
---
Changes in v4:
- create defconfig by 'make savedefconfig'
- drop explicit SYS_BAUDRATE_TABLE in favor of default one
Changes in
This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy
module.
DDR2 controller operates in half-rate mode (upto 533MHZ frequency).
Signed-off-by: Paul Thacker
Signed-off-by: Purna Chandra Mandal
Reviewed-by: Daniel Schwierzeck
Reviewed-by: Tom Rini
Reviewed-by: Simon Glass
Add Microchip PIC32MZ[DA] SoC family support.
Signed-off-by: Purna Chandra Mandal
---
Changes in v4:
- drop forcing DM_SERIAL, PIC32_SERIAL, PIC32_PINCTRL in mach-pic32/Kconfig
- drop extra include
- rename clock compatible to "pic32mzda-clk" from "pic32mzda_clk".
- fix t
Enable MMC, SDHCI, FAT_FS support for PIC32MZ[DA] StarterKit.
Also add custom scripts, rules to boot Linux from microSD card.
Signed-off-by: Purna Chandra Mandal
---
Changes in v4: None
Changes in v3:
- use distro boot commands from config_distro_bootcmd.h
- separate old booting logic as
From: Andrei Pistirica
This driver implements platform specific glue and fixups for
PIC32 internal SDHCI controller.
Signed-off-by: Andrei Pistirica
Signed-off-by: Sandeep Sheriker Mallikarjun
Signed-off-by: Purna Chandra Mandal
Reviewed-by: Tom Rini
Reviewed-by: Daniel Schwierzeck
In PIC32 GPIO controller is part of PIC32 pin controller.
PIC32 has ten independently programmable ports and each with multiple pins.
Each of these pins can be configured and used as GPIO, provided they
are not in use for other peripherals.
Signed-off-by: Purna Chandra Mandal
Reviewed-by: Tom
Create initial directory, Kconfigs needed for PIC32 architecture
support. Also add PIC32 specific register definition required for drivers.
Signed-off-by: Purna Chandra Mandal
Reviewed-by: Daniel Schwierzeck
Reviewed-by: Tom Rini
---
Changes in v4: None
Changes in v3:
- drop empty choice in
From: Paul Thacker
This adds PIC32 UART controller support based on driver model.
Signed-off-by: Paul Thacker
Signed-off-by: Purna Chandra Mandal
Reviewed-by: Daniel Schwierzeck
Reviewed-by: Tom Rini
Reviewed-by: Simon Glass
---
Changes in v4:
- update kconfig dependency (DM_SERIAL
peripherals have default pins assigned thus
require no muxing.
Signed-off-by: Purna Chandra Mandal
Reviewed-by: Tom Rini
Reviewed-by: Daniel Schwierzeck
Reviewed-by: Simon Glass
---
Changes in v4:
- update commit message
- update kconfig dependency on (DM && MACH_PIC32) and default y
Ch
PIC32 clock module consists of multiple oscillators, PLLs, mutiplexers
and dividers capable of supplying clock to various controllers
on or off-chip.
Signed-off-by: Purna Chandra Mandal
Reviewed-by: Simon Glass
Reviewed-by: Daniel Schwierzeck
---
Changes in v4: None
Changes in v3:
- rename
Argument boot_flags of board_init_f() should be set to 0 as
$a0 may be utilized in lowlevel_init() or mips_cache_reset()
or previous stage boot-loader.
Signed-off-by: Purna Chandra Mandal
---
Changes in v2:
- add comment in same line as of the asm instruction
- add commit message
arch/mips
architecture by using compressed(gzip, lzma)
and uncompressed uImage.
Signed-off-by: Purna Chandra Mandal
---
common/bootm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/bootm.c b/common/bootm.c
index 58936ca..99d574d 100644
--- a/common/bootm.c
+++ b/common/bootm.c
On 01/13/2016 08:26 PM, Tom Rini wrote:
> On Tue, Jan 12, 2016 at 03:48:28PM +0530, Purna Chandra Mandal wrote:
>
>> This driver implements MAC and MII layer of the ethernet controller.
>> Network data transfer is handled by controller internal DMA engine.
>> Ethernet co
On 01/14/2016 01:40 AM, Simon Glass wrote:
> Hi Puma,
>
> On 12 January 2016 at 03:18, Purna Chandra Mandal
> wrote:
>> In PIC32 GPIO controller is part of PIC32 pin controller.
>> PIC32 has ten independently programmable ports and each with multiple pins.
>> Each o
On 01/13/2016 09:07 PM, Daniel Schwierzeck wrote:
> Am Dienstag, den 12.01.2016, 15:48 +0530 schrieb Purna Chandra Mandal:
>> This driver implements MAC and MII layer of the ethernet controller.
>> Network data transfer is handled by controller internal DMA engine.
>> E
On 01/13/2016 08:45 PM, Daniel Schwierzeck wrote:
> Am Dienstag, den 12.01.2016, 15:48 +0530 schrieb Purna Chandra Mandal:
>> From: Andrei Pistirica
>>
>> This driver implements platform specific glue and fixups for
>> PIC32 internal SDHCI controller.
>>
&
On 01/13/2016 08:33 PM, Daniel Schwierzeck wrote:
> Am Dienstag, den 12.01.2016, 15:48 +0530 schrieb Purna Chandra Mandal:
>> This adds support for Microchip PIC32MZ[DA] StarterKit board
>> based on a PIC32MZ[DA] family of microcontroller.
>>
>> Signed-o
On 01/13/2016 08:26 PM, Tom Rini wrote:
> On Tue, Jan 12, 2016 at 03:48:26PM +0530, Purna Chandra Mandal wrote:
>
>> Enable MMC, SDHCI, FAT FS, EXT4 FS support for PIC32MZ[DA] StarterKit.
>> Also add custom scripts, rules to boot Linux from microSD card.
>>
>> Signe
On 01/13/2016 08:26 PM, Tom Rini wrote:
> On Tue, Jan 12, 2016 at 03:48:24PM +0530, Purna Chandra Mandal wrote:
>
>> This adds support for Microchip PIC32MZ[DA] StarterKit board
>> based on a PIC32MZ[DA] family of microcontroller.
>>
>> Signed-off-by: Purna Chandra Ma
On 01/14/2016 01:39 AM, Simon Glass wrote:
> Hi Purna,
>
> On 12 January 2016 at 03:18, Purna Chandra Mandal
> wrote:
>> From: Paul Thacker
>>
>> This adds PIC32 UART controller support based on driver model.
>>
>> Signed-off-by: Paul Thack
On 01/13/2016 08:25 PM, Tom Rini wrote:
> On Tue, Jan 12, 2016 at 03:48:18PM +0530, Purna Chandra Mandal wrote:
>
>> PIC32 clock module consists of multiple oscillators, PLLs, mutiplexers
>> and dividers capable of supplying clock to various controllers
>> on or off-chip.
On 01/13/2016 08:19 PM, Daniel Schwierzeck wrote:
> Am Dienstag, den 12.01.2016, 15:48 +0530 schrieb Purna Chandra Mandal:
>> Add Microchip PIC32MZ[DA] SoC family support.
>>
>> Signed-off-by: Purna Chandra Mandal
>>
>> ---
>>
>> Changes in v3:
>
On 01/13/2016 07:33 PM, Daniel Schwierzeck wrote:
> Am Mittwoch, den 13.01.2016, 14:49 +0100 schrieb Daniel Schwierzeck:
>> Am Dienstag, den 12.01.2016, 15:48 +0530 schrieb Purna Chandra
>> Mandal:
>>> From: Paul Thacker
>>>
>>> This adds PIC32 UAR
On 01/13/2016 07:38 PM, Daniel Schwierzeck wrote:
> Am Mittwoch, den 13.01.2016, 14:46 +0100 schrieb Daniel Schwierzeck:
>> Am Dienstag, den 12.01.2016, 15:48 +0530 schrieb Purna Chandra
>> Mandal:
>>> In PIC32 GPIO controller is part of PIC32 pin controller.
>>
On 01/13/2016 07:08 PM, Daniel Schwierzeck wrote:
> Am Dienstag, den 12.01.2016, 15:48 +0530 schrieb Purna Chandra Mandal:
>> PIC32 clock module consists of multiple oscillators, PLLs,
>> mutiplexers
>> and dividers capable of supplying clock to various controllers
>> o
On 01/12/2016 05:59 PM, Daniel Schwierzeck wrote:
> 2016-01-12 11:18 GMT+01:00 Purna Chandra Mandal :
>> Signed-off-by: Purna Chandra Mandal
>> ---
>>
>> Changes in v3: None
>> Changes in v2: None
>>
>> arch/mips/cpu/start.S | 2 ++
>> 1 fi
r for Microchip PIC32 UART controller.
Purna Chandra Mandal (12):
MIPS: initialize board_init_f() argument to zero.
MIPS: initial infrastructure for Microchip PIC32 architecture
drivers: clk: Add clock driver for Microchip PIC32 Microcontroller.
drivers: pinctrl: Add pinctrl driver for
This adds ethernet, TFTP support for PIC32MZ[DA] Starter Kit. Also
custom environment variables/scripts are added to help boot from network.
Signed-off-by: Purna Chandra Mandal
---
Changes in v3: None
Changes in v2:
- replace unbounded loop with wait_for_bit()
- replace register access as
This driver implements MAC and MII layer of the ethernet controller.
Network data transfer is handled by controller internal DMA engine.
Ethernet controller is configurable through device-tree file.
Signed-off-by: Purna Chandra Mandal
---
Changes in v3:
- merge wrappers with eth operation
Add SMSC LAN8740 Phy support required for PIC32MZDA devices.
Signed-off-by: Purna Chandra Mandal
---
Changes in v3: None
Changes in v2: None
drivers/net/phy/smsc.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c
index bfd9815
This adds support for Microchip PIC32MZ[DA] StarterKit board
based on a PIC32MZ[DA] family of microcontroller.
Signed-off-by: Purna Chandra Mandal
---
Changes in v3:
- drop SKIP_LOWLEVEL_INIT, GBL_DATA_OFFSET from config header
- move CMD_MEMTEST, CMD_MEMINFO to defconfig
- increase
From: Andrei Pistirica
This driver implements platform specific glue and fixups for
PIC32 internal SDHCI controller.
Signed-off-by: Andrei Pistirica
Signed-off-by: Sandeep Sheriker Mallikarjun
Signed-off-by: Purna Chandra Mandal
---
Changes in v3:
- remove ofdata_to_platdata, and replace
Enable MMC, SDHCI, FAT FS, EXT4 FS support for PIC32MZ[DA] StarterKit.
Also add custom scripts, rules to boot Linux from microSD card.
Signed-off-by: Purna Chandra Mandal
---
Changes in v3: None
Changes in v2:
- drop shared bus (shared pin selection) configuration.
arch/mips/dts
Add Microchip PIC32MZ[DA] SoC family support.
Signed-off-by: Purna Chandra Mandal
---
Changes in v3:
- drop forcing CONFIG_MIPS_BOOT_* selection in mach-pic32/Kconfig
- indent assembly instructions in delay slot
- made GPIO-nodes child of pinctrl-node in devicetree
- replace pic32_ioremap
From: Paul Thacker
This adds PIC32 UART controller support based on driver model.
Signed-off-by: Paul Thacker
Signed-off-by: Purna Chandra Mandal
---
Changes in v3:
- remove ofdata_to_platdata, and replace platdata with priv
- remove special handling of '\r' as being handled
This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy
module.
DDR2 controller operates in half-rate mode (upto 533MHZ frequency).
Signed-off-by: Paul Thacker
Signed-off-by: Purna Chandra Mandal
---
Changes in v3:
- annotating fixed table with const
- fix camel-case in
In PIC32 GPIO controller is part of PIC32 pin controller.
PIC32 has ten independently programmable ports and each with multiple pins.
Each of these pins can be configured and used as GPIO, provided they
are not in use for other peripherals.
Signed-off-by: Purna Chandra Mandal
---
Changes in v3
peripherals have default pins assigned thus require
no muxing.
Signed-off-by: Purna Chandra Mandal
---
Changes in v3:
- read register base from device-tree
- add/update comments to explain how pinctrl'r works.
- replace pic32_ioremap() with ioremap().
Changes in v2:
- add pinconf routin
PIC32 clock module consists of multiple oscillators, PLLs, mutiplexers
and dividers capable of supplying clock to various controllers
on or off-chip.
Signed-off-by: Purna Chandra Mandal
Reviewed-by: Simon Glass
---
Changes in v3:
- rename clk-pic32.c to clk_pic32.c
- update clock binding
Signed-off-by: Purna Chandra Mandal
---
Changes in v3: None
Changes in v2: None
arch/mips/cpu/start.S | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index e95cdca..35d9650 100644
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
Create initial directory, Kconfigs needed for PIC32 architecture
support. Also add PIC32 specific register definition required for drivers.
Signed-off-by: Purna Chandra Mandal
---
Changes in v3:
- drop empty choices in mach-pic32/Kconfig
- add pic32_get_syscfg_base() for device-config
On 01/11/2016 10:28 PM, Simon Glass wrote:
> Hi,
>
> On 7 January 2016 at 23:46, Purna Chandra Mandal
> wrote:
>> On 01/08/2016 09:04 AM, Simon Glass wrote:
>>
>>> Hi Purna,
>>>
>>> On 4 January 2016 at 07:00, Purna Chandra Mandal
&
On 01/11/2016 10:27 PM, Simon Glass wrote:
> Hi,
>
> On 4 January 2016 at 07:01, Purna Chandra Mandal
> wrote:
>> Signed-off-by: Paul Thacker
>> Signed-off-by: Purna Chandra Mandal
> Please add a commit message.
Agreed, Will add.
>> ---
>>
>> Chan
On 01/11/2016 10:27 PM, Simon Glass wrote:
> Hi,
>
> On 4 January 2016 at 07:00, Purna Chandra Mandal
> wrote:
>> Signed-off-by: Purna Chandra Mandal
>>
> Commit message please.
Ack. Will add.
>> ---
>>
>> Changes in v2:
>> - add get clock r
On 01/11/2016 09:46 PM, Daniel Schwierzeck wrote:
> Am Montag, den 04.01.2016, 19:30 +0530 schrieb Purna Chandra Mandal:
>> Signed-off-by: Purna Chandra Mandal
>>
>> ---
>>
>> Changes in v2:
>> - add get clock rate for mpll clock
>>
>> .../c
On 12/20/2015 04:13 AM, Daniel Schwierzeck wrote:
> Prepare sub-folder for device-tree files. Make support for
> device-tree on MIPS available in Kbuild/Kconfig.
>
> Signed-off-by: Daniel Schwierzeck
> Signed-off-by: Purna Chandra Mandal
>
>
> ---
>
> Changes i
On 01/09/2016 10:02 PM, Daniel Schwierzeck wrote:
> This patch series updates all MIPS asm header files containing
> I/O code as well as processor, register and assembly definitions.
> The source of the update are the MIPS asm header files of linux-4.4.
>
> The main goal is to get a complete set o
On 12/21/2015 08:50 PM, Stefan Roese wrote:
> On 21.12.2015 15:58, Daniel Schwierzeck wrote:
>>
>>
>> Am 17.12.2015 um 18:30 schrieb Purna Chandra Mandal:
>>> From: Cristian Birsan
>>>
>>> Signed-off-by: Cristian Birsan
>>> Signed-off-b
On 01/08/2016 09:04 AM, Simon Glass wrote:
> Hi Purna,
>
> On 4 January 2016 at 07:00, Purna Chandra Mandal
> wrote:
>> Signed-off-by: Purna Chandra Mandal
>>
> Please add a commit message.
Ack. will add.
>> ---
>>
>> Changes in v2:
>> - add
On 01/07/2016 12:11 AM, Joe Hershberger wrote:
> [...]
> +static int pic32_eth_probe(struct udevice *dev)
> +{
> + struct eth_pdata *pdata = dev_get_platdata(dev);
> + struct pic32eth_device *priv = dev_get_priv(dev);
> + void __iomem *iobase;
> + int phy_addr = 0;
> +
> +#
On 01/06/2016 04:30 AM, Joe Hershberger wrote:
> On Mon, Jan 4, 2016 at 8:02 AM, Purna Chandra Mandal
> wrote:
>> This driver implements MAC and MII layer of PIC32 ethernet controller.
>> This controller is capable of handling 100/10mbps full/half duplex
>> ethernet com
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