of ARCH_RZN1 symbol.
Signed-off-by: Ralph Siemsen
---
arch/arm/Kconfig | 17 +
arch/arm/Makefile | 1 +
arch/arm/mach-rzn1/Kconfig| 18 ++
arch/arm/mach-rzn1/Makefile | 3 +++
arch/arm/mach-rzn1/cpu_info.c | 20
Driver for Cadence EDAC DDR controller, as found in the Renesas RZ/N1.
Only basic setup, not using the ECC features.
Signed-off-by: Ralph Siemsen
---
drivers/ram/Kconfig | 1 +
drivers/ram/Makefile| 2 +
drivers/ram/cadence/Kconfig | 24 ++
drivers/ram/cadence
Signed-off-by: Ralph Siemsen
---
This tool could possibly be incorporated into mkimage / imagetools.
However it is unclear how to handle the extra commandline parameters
(NAND ECC settings, etc). So for now it is stand-alone tool.
tools/Makefile | 2 +
tools/spkg_header.h | 49
This is taken from Linux kernel 5.17, and contains just bare minimum
functionality: CPU, UART and system timer.
Additional functionality (from newer kernel versions) will be added
later. Note that the Linux side is under active development.
Signed-off-by: Ralph Siemsen
---
The following changes
the regmap_update_bits for level1/level2 register updates
--> does not exist for regmap_ranges, consider adding?
Signed-off-by: Ralph Siemsen
---
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/renesas/Kconfig| 7 +
drivers/pinctrl/renesas/Makef
as existing Renesas RCAR2/3
clock drivers, using a temporary structure filled on-the-fly.
Signed-off-by: Ralph Siemsen
---
- TODO: add support for div_table
drivers/clk/renesas/Kconfig| 6 +
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r9a06g032-clocks.c | 734
.
The support code contains platform specific hardware access (TMU_BASE),
and it is not needed for other Renesas devices such as RZ/N1. Therefore,
alter Makefile to build renesas-cpg-mssr.c only for RCAR-GEN2 and RCAR-GEN3.
Signed-off-by: Ralph Siemsen
---
drivers/clk/renesas/Kconfig | 2 +-
drivers/clk
Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S")
added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For
platforms not using SPL boot, add the corresponding non-SPL config,
so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected.
Signed-off
://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzn1
[2] https://github.com/renesas-rz/rzn1_u-boot/tree/rzn1-stable
Michel Pollet (1):
tools: Add tool to create Renesas SPKG images
Ralph Siemsen (8):
ARM: armv7: add non-SPL enable for Cortex SMPEN
clk: renesas: prepare
Hi Simon,
On Sun, Aug 7, 2022 at 9:25 AM Simon Glass wrote:
>
> Link to patman's documentation from the doc/ directory so that it appears
> in the 'make htmldocs' output.
Presumably this will show up on readthedocs? Seems like a nice addition.
The rename of README to README.rst would break
Hi Martin,
On Wed, Aug 3, 2022 at 6:05 AM Martin Bonner wrote:
>
> I and my colleagues have a number of patches we would like to
> contribute back to the community, however for various reasons
> (principally operating inside corporate firewalls), it isn't possible
> to use `git send-email`, and
On Thu, Jul 7, 2022 at 7:07 AM Thu Ra wrote:
>
> Error: cmd/libkiosk_crypto.c:5:10: fatal error: unistd.h: No such file or
> directory
This file (libkiosk_crypto.c) is not part of u-boot. In the build log,
we can see that it is copied into the u-boot tree:
cp ../common/src/libkiosk_crypto.c
Correct spelling and copy/paste errors in comments.
Fixes 1c4db59d9b ("regmap: Add support for regmap fields")
Signed-off-by: Ralph Siemsen
---
include/regmap.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/regmap.h b/include/regmap.h
index
Update the diagnostic message with revised location of document, which
changed in 3e9fddfc4f1 ("doc: Move devicetree control doc to rST")
Signed-off-by: Ralph Siemsen
---
Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Makefile b/Makefile
index c
On Thu, Apr 21, 2022 at 2:01 PM Tom Rini wrote:
> OK, but this doesn't do anything. Where are you select'ing the new
> symbol from?
It is in code for a new platform which I am going to slowly beat into
shape and try to get upstreamed.
If you prefer to see everything at once, I can do that,
Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S")
added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For
platforms not using SPL boot, add the corresponding non-SPL config,
so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected.
Signed-off
Dear maintainers,
Any thoughts on this? It seems that "sf probe" behaviour should either
get fixed, or we should remove the "hz" and "mode" arguments entirely,
since they don't work anymore.
Regards,
Ralph
On Thu, Oct 15, 2020 at 12:25:41PM -0400, Ralph Siem
On Tue, Sep 29, 2020 at 02:52:05PM -0400, Ralph Siemsen wrote:
Fixes: db5741f7a85ec3ee79b64496172afaa7dc2cb225 ("arm: socfpga: Convert
system manager from struct to defines")
Just curious if you have had a chance to look over this patch?
http://patchwork.ozlabs.org/project/u
Hi,
The "sf probe" command is documented to take optional speed/mode args:
sf probe [[bus:]cs] [hz] [mode] - init flash device on given SPI bus
and chip select
This worked correctly in older u-boot versions, but as of 2019.07 the
speed/mode arguments appear to
when operating at 100Mbit.
Fixes: db5741f7a85ec3ee79b64496172afaa7dc2cb225 ("arm: socfpga: Convert system
manager from struct to defines")
Signed-off-by: Ralph Siemsen
---
I reviewed the other #defines for gen5 and they seem correct.
I have NOT checked the defines for Arria 10 or
Hi Jasper,
On Thu, Sep 10, 2020 at 11:19:29AM +0200, Jasper van Santen wrote:
I had already seen the movie, the book would have been better ;)
I feel that way too... ;)
Fortunately I build U-Boot with buildroot, so i have the source code.
It is a big meager, but I ended up grepping the man
Hi Jasper,
On Wed, Sep 09, 2020 at 07:03:58PM +0200, Jasper van Santen wrote:
I am sorry to ask such a basic question, but i really can't find any
documentation on the commands possible in scripting.
Documentation of Hush and its commands i can't find.
The hush shell gives you the ability to
t;cmd: mem: Add bitflip
memory test to alternate mtest")
Signed-off-by: Ralph Siemsen
--
Changes in v5:
- Correct logic for updating error count
Changes in v4:
- Avoid #ifdef in the code
Change-Id: Ie641d04e731fc5bc6a3bbef914bf7fad136cdc94
---
cmd/Kconfig | 12
cmd/mem.c | 21 ++
t;cmd: mem: Add bitflip
memory test to alternate mtest")
Signed-off-by: Ralph Siemsen
--
Changes in v4:
- Avoid #ifdef in the code
Change-Id: Ie641d04e731fc5bc6a3bbef914bf7fad136cdc94
---
cmd/Kconfig | 12
cmd/mem.c | 18 ++
2 files changed, 26 insertions(+), 4 dele
t;cmd: mem: Add bitflip
memory test to alternate mtest")
Signed-off-by: Ralph Siemsen
--
Changes in v3:
- Add Kconfig option to disable bitflip test
- Refactor the fix into a helper function
Change-Id: Ie641d04e731fc5bc6a3bbef914bf7fad136cdc94
---
cmd/Kconfig | 12
cmd/mem.c | 24 +
Hi Stefan,
On Wed, Sep 09, 2020 at 05:13:49PM +0200, Stefan Roese wrote:
Usually the RB is only added, when not too many further changes are
made by the committer. There is no strict rule here AFAIK.
In that case I'll omit your RB on v3 as the change is somewhat larger,
and includes the
Hi Stefan,
On Wed, Sep 09, 2020 at 03:53:08PM +0200, Stefan Roese wrote:
Hi Ralph,
On 09.09.20 15:49, Ralph Siemsen wrote:
Very good, I will send a separate patch that adds a Kconfig option.
As it turns out, doing a separate patch for this gets messy, and also
would introduce a dependency
Hi Stefan,
On Wed, Sep 09, 2020 at 03:34:35PM +0200, Stefan Roese wrote:
I agree that it's too time consuming (usually) for a manufacturing test.
Either you are okay with disabling CONFIG_SYS_ALT_MEMTEST on your board,
which will also disable this bitflip test. Or please continue adding a
new
Hi Stefan,
On Wed, Sep 09, 2020 at 10:49:29AM +0200, Stefan Roese wrote:
Hi Ralph,
Thanks for finding and fixing this:
I've sent a v2 with the suggested changes.
Have also noticed that mtest takes considerably longer when doing the
bitflip test. To the point where using it for
dress. Thus it fails to test
the last word of the requested range. Fixed by using (end - start + 1).
Fixes: 8e434cb705d463bc8cff935160e4fb4c77cb99ab ("cmd: mem: Add bitflip
memory test to alternate mtest")
Signed-off-by: Ralph Siemsen
--
Changes in v2:
- Minor refactor to reduce line l
st to alternate mtest")
Signed-off-by: Ralph Siemsen
--
TODO/FIXME: maybe the ending address should be automatically aligned?
Change-Id: Ie641d04e731fc5bc6a3bbef914bf7fad136cdc94
---
cmd/mem.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/cmd/mem.c b/cmd/me
On Wed, Aug 19, 2020 at 09:28:39PM +0200, Marek Vasut wrote:
Is the F2SDRAM port enabled in your case ?
Is there a way I can check this via software? Unfortunately I do not
have access to Quartus/Qsys files, nor the person who did the design.
Ralph
Hi Wolfgang et al.,
On Fri, Aug 07, 2020 at 05:49:13PM +0200, Wolfgang Grandegger wrote:
Am 07.08.20 um 17:05 schrieb Dinh Nguyen:
On 8/6/20 7:36 AM, Wolfgang Grandegger wrote:
Am 06.08.20 um 13:04 schrieb Marek Vasut:
On 8/6/20 12:53 PM, Wolfgang Grandegger wrote:
This reverts commit
On Wed, Oct 02, 2019 at 02:37:20PM +0200, Marek Szyprowski wrote:
malloc_cache_aligned() might return zero, so fix potential NULL pointer
access if __GFP_ZERO flag is set.
Signed-off-by: Marek Szyprowski
Reviewed-by: Ralph Siemsen
This looks reasonable to me. The memset() will happily
In combination with multiple partitions in NAND, this printf() ends up
being more noise than helpful. Change it to debug() instead.
Signed-off-by: Ralph Siemsen
---
drivers/dfu/dfu_nand.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dfu/dfu_nand.c b/drivers/dfu
Make it a little easier to find the documentation.
Signed-off-by: Ralph Siemsen
---
doc/driver-model/spi-howto.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/doc/driver-model/spi-howto.rst b/doc/driver-model/spi-howto.rst
index a538fdcb93..5540eb7d38 100644
--- a/doc
Signed-off-by: Ralph Siemsen
---
This compatible string also appears in: axs10x_mb.dtsi and hsdk.dts.
Maintainers of those boards have been copied, kindly review.
drivers/net/designware.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index
incrementing counter, as in dfu_prepare_function().
Signed-off-by: Ralph Siemsen
---
Changes in v2:
Remove incorrect note.
Fix spelling error in commit message.
drivers/usb/gadget/f_dfu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c
index 30ece524a
Small correction:
> Notes:
> The array of pointers allocated in dfu_prepare_function() is larger
> than necessary. For some reason it is N+2 when N+1 would suffice.
> Not a memory leak, so did not address in this commit.
Please ignore that note... the N+2 element is indeed needed, it
incrementing counter, as in dfu_prepare_function().
Signed-off-by: Ralph Siemsen
---
Notes:
The array of pointers allocated in dfu_prepare_function() is larger
than necessary. For some reason it is N+2 when N+1 would suffice.
Not a memory leak, so did not address in this commit.
drivers/usb/gadget/f
the exception
for spl/Makefile otherwise it has no effect.
Signed-off-by: Ralph Siemsen ral...@netwinder.org
---
Note: feel free to adjust the commit message to remove the
gratuitous ascii art emphasis, etc.
Note2: kindly CC: me on any replies
---
.gitignore | 2 +-
1 file changed, 1 insertion(+), 1
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