use a quirks field to support such quirks.
Signed-off-by: Jonas Karlman
Reviewed-by: Shawn Lin
---
drivers/mmc/rockchip_sdhci.c | 62 ++--
1 file changed, 59 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc
p, this is indeed a bug that we try to fix, which can be reproduced
with PM981 NVMe when booting kernel.
Reviewed-by: Shawn Lin
Signed-off-by: Jon Lin
---
(no changes since v1)
drivers/nvme/nvme.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/nvm
This sounds reasonable, so FWIW:
Shawn Lin
---
(no changes since v1)
drivers/nvme/nvme.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
index f6465ea7f4..5d05cb6e9e 100644
--- a/drivers/nvme/nvme.c
+++ b/drivers/nvme/nvme.c
@@ -761,6
Hi Neil,
On 2021/3/22 17:18, Neil Armstrong wrote:
With the introduction of pcie_dw_rockchip, and need to support the DW PCIe in
the
Amlogic AXG & G12 SoCs, most of the DW PCIe helpers would be duplicated.
This introduce a "common" DW PCIe helpers file with common code merged from the
dw_ti an
Add Rockchip dwc based PCIe controller driver for rk356x platform.
Driver support Gen3 by operating as a Root complex.
Signed-off-by: Shawn Lin
---
Changes in v2:
- reorder the header file
- add more comment
- use clrsetbits_le32 and setbits_le32
- fix other various suggestions from Simon
from Simon
Shawn Lin (2):
phy: rockchip: Add Rockchip Synopsys PCIe 3.0 PHY
pci: Add Rockchip dwc based PCIe controller driver
drivers/pci/Kconfig | 9 +
drivers/pci/Makefile | 1 +
drivers/pci/pcie_dw_rockchip.c| 877
Add the Rockchip Synopsys based PCIe 3.0 PHY driver as
part of Generic PHY framework.
Signed-off-by: Shawn Lin
Reviewed-by: Simon Glass
---
Changes in v2:
- reoder header file
- add comment
drivers/phy/rockchip/Kconfig | 6 +
drivers/phy/rockchip/Makefile
Hi Simon
Thanks you for reviewing it.
在 2021/1/14 23:42, Simon Glass 写道:
Hi Shawn,
On Thu, 14 Jan 2021 at 01:15, Shawn Lin wrote:
8<--
+
+static int rockchip_pcie_init_port(struct udevice *dev)
+{
+ int ret;
+ u32 val;
+ struct rk_pcie *priv = dev_get_p
在 2021/1/14 23:42, Simon Glass 写道:
Hi Shawn,
On Thu, 14 Jan 2021 at 01:15, Shawn Lin wrote:
Add the Rockchip Synopsys based PCIe 3.0 PHY driver as
part of Generic PHY framework.
Signed-off-by: Shawn Lin
---
drivers/phy/rockchip/Kconfig | 6 +
drivers/phy/rockchip
Add Rockchip dwc based PCIe controller driver for rk356x platform.
Driver support Gen3 by operating as a Root complex.
Signed-off-by: Shawn Lin
---
drivers/pci/Kconfig| 9 +
drivers/pci/Makefile | 1 +
drivers/pci/pcie_dw_rockchip.c | 755
Add the Rockchip Synopsys based PCIe 3.0 PHY driver as
part of Generic PHY framework.
Signed-off-by: Shawn Lin
---
drivers/phy/rockchip/Kconfig | 6 +
drivers/phy/rockchip/Makefile | 1 +
.../phy/rockchip/phy-rockchip-snps-pcie3.c| 146
This patchset add Rockchip dwc-based PCIe controller and PHY
found on RK356X platforms. It could support Gen3 as a root complex.
Shawn Lin (2):
phy: rockchip: Add Rockchip Synopsys PCIe 3.0 PHY
pci: Add Rockchip dwc based PCIe controller driver
drivers/pci/Kconfig
在 2020/6/2 9:59, Kever Yang 写道:
Hi Kurt,
On 2020/6/2 上午4:30, Kurt Miller wrote:
On at least the RockPro64, many cards will trip a
synchronous abort when first accessing PCIe config space
during bus scanning. A delay after link training allows
some of these cards to function.
Signed-off-by:
On 2020/4/25 19:03, Jagan Teki wrote:
Add Rockchip PCIe controller driver for rk3399 platform.
Driver support Gen1 by operating as a Root complex.
Thanks to Patrick for initial work.
Thanks for your patches!
Signed-off-by: Patrick Wildt
Signed-off-by: Jagan Teki
---
drivers/pci/Kconf
mentioned.
Feel free to add
Reviewed-by: Shawn Lin
Signed-off-by: Ziyuan Xu
---
drivers/mmc/dw_mmc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 2cf7bae..38d4a64 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -126,6
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