Fix up the debug prints that were dumping state of TCHAN RT registers to
use tchan for MEM_TO_DEV transfers.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Grygorii Strashko
---
drivers/dma/ti/k3-udma.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/ti/k3
Cast pointers properly so as to avoid warnings when driver is built for
32 bit platforms
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Grygorii Strashko
---
drivers/dma/ti/k3-udma.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/dma/ti/k3-udma.c
Exposed ring mode works well with 32 bit and 64 bit cores without need
for Proxies for 32 bit cores. Therefore switch to exposed ring mode.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Grygorii Strashko
---
drivers/dma/ti/k3-udma.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
UDMA always expects 64 bit address pointer of the transfer descriptor in
the Ring. But on 32 bit cores like R5, pointer is always 32 bit in size.
Therefore copy over 32 bit pointer value to 64 bit variable before
pushing it over to the ring, so that upper 32 bits are 0s.
Signed-off-by: Vignesh
Instead of looking getting reference to SYSFW device using name which
is not guaranteed to be constant, use phandle supplied in the DT node to
get reference to SYSFW
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Grygorii Strashko
---
drivers/soc/ti/k3-navss-ringacc.c | 3 ++-
1 file changed
Flush caches when pushing an element to ring and invalidate caches when
popping an element from ring in Exposed Ring mode. Otherwise DMA
transfers don't work properly in R5 SPL (with caches enabled) where the
core is not in coherency domain.
Signed-off-by: Vignesh Raghavendra
Reviewed
v4:
Rebase onto latest master and fix a compliation error due to recent
changes in master.
v3:
Address comments by Grygorii and add R-by
Vignesh Raghavendra (10):
lib: Import few bitmap functions from Linux
dma: ti: k3-udma: Query DMA channels allocated from Resource Manager
soc: ti: k3
On K3 SoCs, DMA channels are shared across multiple entities, therefore
U-Boot DMA driver needs to query resource range from centralised
resource management controller i.e SystemFirmware and use DMA channels
allocated for A72 host. Add support for the same.
Signed-off-by: Vignesh Raghavendra
Import few basic bitmap functions (bitmap_{weight,fill,set,clear,or}())
and their dependencies from Linux. These are required for upcoming DMA
resource allocation support for TI's K3 SoCs.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Grygorii Strashko
---
include/linux/bitmap.h | 133
TI's AM654 SoC has a Cadence OSPI IP. Add a new compatible string for
the same.
Signed-off-by: Vignesh Raghavendra
---
drivers/spi/cadence_qspi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 6374d3976a4a..f8b69406d4b9 100644
Cadence OSPI is similar to QSPI IP except that it supports Octal IO
(8 IO lines) flashes. Add support for Cadence OSPI IP with existing
driver using new compatible
Signed-off-by: Vignesh Raghavendra
---
drivers/spi/cadence_qspi.c | 1 +
drivers/spi/cadence_qspi_apb.c | 8 ++--
2 files
This series adds Octal mode support for Micron's mt35x flash.
Also adds Octal mode support for Cadance OSPI/QSPI controller.
Currently only 1-1-8 mode is supported.
Vignesh Raghavendra (3):
mtd: spi-nor-core: Add octal mode support
spi: cadence-qspi: Add support for Cadence Octal SPI
Add support for Octal flash devices. Octal flash devices use 8 IO lines
for data transfer. Currently only 1-1-8 Octal Read mode is supported.
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/spi/sf_internal.h | 3 ++-
drivers/mtd/spi/spi-nor-core.c | 20 +++-
drivers/spi/spi
Since, commit 62f9b6544728 ("common: Move older CPU functions to their own
header")
cache ops functions are declared in a separate header. Include the same
to avoid build warnings.
Signed-off-by: Vignesh Raghavendra
---
drivers/usb/cdns3/ep0.c | 1 +
1 file changed, 1 insertion(+)
Enable configs related to DMA and Ethernet so as to support networking at
U-Boot prompt
Signed-off-by: Vignesh Raghavendra
Acked-by: Joe Hershberger
Reviewed-by: Grygorii Strashko
---
configs/j721e_evm_a72_defconfig | 8
1 file changed, 8 insertions(+)
diff --git a/configs
and configs.
Depends on [1] for ethernet to work
[1] https://patchwork.ozlabs.org/project/uboot/list/?series=146508
v3:
Add a debug print to print flow ID
v2:
Address comments from Grygorii.
Collect Acks
Vignesh Raghavendra (6):
dma: Introduce dma_get_cfg() interface
dma: ti: k3-udma: Implement
Get flow ID information for RX DMA channel using dma_get_cfg() interface
instead of reading from DT. This is required in order to avoid DT update
whenever there is change in the range of flow ID allocated to the host.
Signed-off-by: Vignesh Raghavendra
Acked-by: Joe Hershberger
Reviewed
. Clients can use unique configuration ID flags to get different
configuration data from DMA driver.
Signed-off-by: Vignesh Raghavendra
Acked-by: Joe Hershberger
Reviewed-by: Grygorii Strashko
---
drivers/dma/dma-uclass.c | 12
include/dma-uclass.h | 11 +++
include/dma.h
Add DT nodes related to DMA and CPSW to -u-boot.dtsi to get networking
up on J721e EVM.
Signed-off-by: Vignesh Raghavendra
Acked-by: Joe Hershberger
Reviewed-by: Grygorii Strashko
---
.../k3-j721e-common-proc-board-u-boot.dtsi| 238 ++
1 file changed, 238 insertions
UDMA always expects 64 bit address pointer of the transfer descriptor in
the Ring. But on 32 bit cores like R5, pointer is always 32 bit in size.
Therefore copy over 32 bit pointer value to 64 bit variable before
pushing it over to the ring, so that upper 32 bits are 0s.
Signed-off-by: Vignesh
Exposed ring mode works well with 32 bit and 64 bit cores without need
for Proxies for 32 bit cores. Therefore switch to exposed ring mode.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Grygorii Strashko
---
drivers/dma/ti/k3-udma.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
Add new compatible to handle J721e SoC
Signed-off-by: Vignesh Raghavendra
Acked-by: Joe Hershberger
Reviewed-by: Grygorii Strashko
---
drivers/dma/ti/k3-udma.c| 2 +-
drivers/net/ti/am65-cpsw-nuss.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/ti/k3
Instead of looking getting reference to SYSFW device using name which
is not guaranteed to be constant, use phandle supplied in the DT node to
get reference to SYSFW
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Grygorii Strashko
---
drivers/soc/ti/k3-navss-ringacc.c | 3 ++-
1 file changed
MA channel. In order for basic ethernet to work, CPSW slave must be
aware of the flow ID allocated for the RX channel by the DMA driver.
This interface allows CPSW to query flow ID from DMA provider and
configure it in CPSW HW.
Signed-off-by: Vignesh Raghavendra
Acked-by: Joe Hershberger
Reviewed-by
On K3 SoCs, DMA channels are shared across multiple entities, therefore
U-Boot DMA driver needs to query resource range from centralised
resource management controller i.e SystemFirmware and use DMA channels
allocated for A72 host. Add support for the same.
Signed-off-by: Vignesh Raghavendra
Flush caches when pushing an element to ring and invalidate caches when
popping an element from ring in Exposed Ring mode. Otherwise DMA
transfers don't work properly in R5 SPL (with caches enabled) where the
core is not in coherency domain.
Signed-off-by: Vignesh Raghavendra
Reviewed
Add new compatible to handle UDMA support for J721e SoC
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Grygorii Strashko
---
drivers/dma/ti/k3-udma.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index 92c7af910406..cccffb600c4c 100644
Cast pointers properly so as to avoid warnings when driver is built for
32 bit platforms
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Grygorii Strashko
---
drivers/dma/ti/k3-udma.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/dma/ti/k3-udma.c
Remove redundant coherency checks before calling cache ops in UDMA
driver. This is now handled in arch specific cache operation
implementation based on Kconfig option
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Grygorii Strashko
---
drivers/dma/ti/k3-udma.c | 49
Fix up the debug prints that were dumping state of TCHAN RT registers to
use tchan for MEM_TO_DEV transfers.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Grygorii Strashko
---
drivers/dma/ti/k3-udma.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/ti/k3
Import few basic bitmap functions (bitmap_{weight,fill,set,clear,or}())
and their dependencies from Linux. These are required for upcoming DMA
resource allocation support for TI's K3 SoCs.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Grygorii Strashko
---
include/linux/bitmap.h | 133
v3:
Address comments by Grygorii and add R-by
Vignesh Raghavendra (10):
lib: Import few bitmap functions from Linux
dma: ti: k3-udma: Query DMA channels allocated from Resource Manager
soc: ti: k3-navss-ringacc: Flush/invalidate caches on ring push/pop
soc: ti: k3-navss-ringacc: Get
Hi,
On 26/11/19 12:39 pm, Michal Simek wrote:
> On 19. 11. 19 15:20, Ashok Reddy Soma wrote:
>> Add dual parallel and dual stacked support in spi-nor framework.
>> Add dual flash support for nor-scan, read and write.
>>
How does the DT representation of these flashes look like?
Is it in
Get flow ID information for RX DMA channel using dma_get_cfg() interface
instead of reading from DT. This is required in order to avoid DT update
whenever there is change in the range of flow ID allocated to the host.
Signed-off-by: Vignesh Raghavendra
Acked-by: Joe Hershberger
---
drivers/net
and configs.
Depends on [1] for ethernet to work
[1] http://patchwork.ozlabs.org/project/uboot/list/?series=145954
v2:
Address comments from Grygorii.
Collect Acks
Vignesh Raghavendra (6):
dma: Introduce dma_get_cfg() interface
dma: ti: k3-udma: Implement dma_get_cfg() interface
net: ti: am65
Add DT nodes related to DMA and CPSW to -u-boot.dtsi to get networking
up on J721e EVM.
Signed-off-by: Vignesh Raghavendra
Acked-by: Joe Hershberger
---
.../k3-j721e-common-proc-board-u-boot.dtsi| 239 ++
1 file changed, 239 insertions(+)
diff --git a/arch/arm/dts/k3-j721e
Enable configs related to DMA and Ethernet so as to support networking at
U-Boot prompt
Signed-off-by: Vignesh Raghavendra
Acked-by: Joe Hershberger
---
configs/j721e_evm_a72_defconfig | 8
1 file changed, 8 insertions(+)
diff --git a/configs/j721e_evm_a72_defconfig b/configs
Add new compatible to handle J721e SoC
Signed-off-by: Vignesh Raghavendra
Acked-by: Joe Hershberger
---
drivers/dma/ti/k3-udma.c| 2 +-
drivers/net/ti/am65-cpsw-nuss.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3
. Clients can use unique configuration ID flags to get different
configuration data from DMA driver.
Signed-off-by: Vignesh Raghavendra
Acked-by: Joe Hershberger
---
drivers/dma/dma-uclass.c | 12
include/dma-uclass.h | 11 +++
include/dma.h| 11 +++
3
MA channel. In order for basic ethernet to work, CPSW slave must be
aware of the flow ID allocated for the RX channel by the DMA driver.
This interface allows CPSW to query flow ID from DMA provider and
configure it in CPSW HW.
Signed-off-by: Vignesh Raghavendra
Acked-by: Joe Hershberger
---
drivers
On K3 SoCs, DMA channels are shared across multiple entities, therefore
U-Boot DMA driver needs to query resource range from centralised
resource management controller i.e SystemFirmware and use DMA channels
allocated for A72 host. Add support for the same.
Signed-off-by: Vignesh Raghavendra
Flush caches when pushing an element to ring and invalidate caches when
popping an element from ring in Exposed Ring mode. Otherwise DMA
transfers don't work properly in R5 SPL (with caches enabled) where the
core is not in coherency domain.
Reviewed-by: Grygorii Strashko
Signed-off-by: Vignesh
Fix up the debug prints that were dumping state of TCHAN RT registers to
use tchan for MEM_TO_DEV transfers.
Signed-off-by: Vignesh Raghavendra
---
drivers/dma/ti/k3-udma.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3
Remove redundant coherency checks before calling cache ops in UDMA
driver. This is now handled in arch specific cache operation
implementation based on Kconfig option
Signed-off-by: Vignesh Raghavendra
---
drivers/dma/ti/k3-udma.c | 49 +---
1 file changed
Instead of looking getting reference to SYSFW device using name which
is not guaranteed to be constant, use phandle supplied in the DT node to
get reference to SYSFW
Signed-off-by: Vignesh Raghavendra
---
drivers/soc/ti/k3-navss-ringacc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion
Add new compatible to handle UDMA support for J721e SoC
Signed-off-by: Vignesh Raghavendra
---
drivers/dma/ti/k3-udma.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index 03c48c9d1ee2..def3c5c38c66 100644
--- a/drivers/dma/ti/k3-udma.c
Import few basic bitmap functions (bitmap_{weight,fill,set,clear,or}())
and their dependencies from Linux. These are required for upcoming DMA
resource allocation support for TI's K3 SoCs.
Signed-off-by: Vignesh Raghavendra
---
include/linux/bitmap.h | 133
Exposed ring mode works well with 32 bit and 64 bit cores without need
for Proxies for 32 bit cores. Therefore switch to exposed ring mode.
Signed-off-by: Vignesh Raghavendra
---
drivers/dma/ti/k3-udma.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/ti/k3
Cast pointers properly so as to avoid warnings when driver is built for
32 bit platforms
Signed-off-by: Vignesh Raghavendra
---
drivers/dma/ti/k3-udma.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index
UDMA always expects 64 bit address pointer of the transfer descriptor in
the Ring. But on 32 bit cores like R5, pointer is always 32 bit in size.
Therefore copy over 32 bit pointer value to 64 bit variable before
pushing it over to the ring, so that upper 32 bits are 0s.
Signed-off-by: Vignesh
Vignesh Raghavendra (10):
lib: Import few bitmap functions from Linux
dma: ti: k3-udma: Query DMA channels allocated from Resource Manager
soc: ti: k3-navss-ringacc: Flush/invalidate caches on ring push/pop
soc: ti: k3-navss-ringacc: Get SYSFW reference from DT phandle
dma: ti: k3-udma
On 21-Nov-19 6:02 PM, Grygorii Strashko wrote:
On 18/11/2019 12:59, Vignesh Raghavendra wrote:
This patch enables networking support for TI's J721e SoC.
Patch 1 adds a new interface to DMA uclass to get channel specific
private/configuration data. Patch 2 to 4 use this interface to pass
On 20/11/19 2:46 PM, Grygorii Strashko wrote:
>
>
> On 20/11/2019 06:30, Lokesh Vutla wrote:
>>
>>
>> On 20/11/19 12:14 AM, Grygorii Strashko wrote:
>>> Move BOOTP_DNS2 and PHY_TI from dra7xx_evm.h to
>>> dra7xx_evm_defconfig.
>>>
>>> Signed-off-by: Grygorii Strashko
>>> ---
>>>
Hi,
On 19/11/19 7:03 PM, Bin Meng wrote:
> +Vignesh
>
> On Mon, Oct 21, 2019 at 11:40 AM Simon Glass wrote:
>>
>> We don't normally need this on x86 unless the size of SPI flash devices is
>> larger than 16MB. This can be enabled by particular SoCs as needed, since
>> it adds to code size.
>>
in future.
For better performance, driver uses DMA to copy data from flash in
direct mode using dma_memcpy().
Signed-off-by: Vignesh Raghavendra
---
v2: Add DMA support and update commit message
drivers/spi/cadence_qspi.c | 40 -
drivers/spi/cadence_qspi.h | 19
://patchwork.ozlabs.org/patch/1195556/
Vignesh Raghavendra (2):
spi: cadence_qspi: Move to spi-mem framework
spi: cadence-qspi: Add direct mode support
drivers/spi/cadence_qspi.c | 148 +++---
drivers/spi/cadence_qspi.h | 24 +++--
drivers/spi/cadence_qspi_apb.c
-by: Vignesh Raghavendra
---
v2: No change
drivers/spi/cadence_qspi.c | 136 +
drivers/spi/cadence_qspi.h | 9 +--
drivers/spi/cadence_qspi_apb.c | 124 --
3 files changed, 91 insertions(+), 178 deletions(-)
diff --git a/drivers/spi
Hi Marek,
On 18/11/19 7:42 PM, Marek Vasut wrote:
> On 11/18/19 2:46 PM, Vignesh Raghavendra wrote:
>> xhci.h has now been moved to include/usb/ folder. Therefore, update the
>
> s/folder/directory/ ; I can update it while applying.
Agree, Thanks!
>
>> path in
On 19/11/19 12:57 AM, Grygorii Strashko wrote:
>
>
> On 14/11/2019 11:14, Vignesh Raghavendra wrote:
>> On K3 SoCs, DMA channels are shared across multiple entities, therefore
>> U-Boot DMA driver needs to query resource range from centralised
>> resourc
Enable USB host and device related configs.
Signed-off-by: Vignesh Raghavendra
---
configs/j721e_evm_a72_defconfig | 28
1 file changed, 28 insertions(+)
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index 748179e82317..0abbfc02e614
Setup env variables for updating firmwares on eMMC/OSPI/MMC via DFU
Signed-off-by: Vignesh Raghavendra
---
include/configs/j721e_evm.h | 10 +++
include/environment/ti/k3_dfu.h | 46 +
2 files changed, 56 insertions(+)
create mode 100644 include
J721e has two instances of Cadence USB3 controller. Add DT nodes for the
same. USB0 is configured to device mode and USB1 is configured to host
mode. For now only high speed mode is supported.
Signed-off-by: Vignesh Raghavendra
---
.../k3-j721e-common-proc-board-u-boot.dtsi| 14
arch
xhci.h has now been moved to include/usb/ folder. Therefore, update the
path in the Cadence USB drivers.
Signed-off-by: Vignesh Raghavendra
---
drivers/usb/cdns3/core.c | 2 +-
drivers/usb/cdns3/host.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/cdns3
Add USB support for J721e SoC.
First patch fixes a compile issue with Cadence USB driver. Rest of the
patches add env, DT and configs related to USB.
Vignesh Raghavendra (4):
usb: cdns3: Fix include file path
environment: ti: Add DFU environment variables k3_dfu.h
arm: dts: k3-j721e: Add DT
will be accessible
> by getting the UCLASS_SPI_FLASH's private data.
>
> The SST's SFDP table is particularly of interest because contains
> pre-programmed globally unique EUI-48 and EUI-64 identifiers.
>
> Signed-off-by: Tudor Ambarus
> ---
Reviewed-by: Vignesh Raghavendr
Get flow ID information for RX DMA channel using dma_get_cfg() interface
instead of reading from DT. This is required in order to avoid DT update
whenever there is change in the range of flow ID allocated to the host.
Signed-off-by: Vignesh Raghavendra
---
drivers/net/ti/am65-cpsw-nuss.c | 13
Enable configs related to DMA and Ethernet so as to support networking at
U-Boot prompt
Signed-off-by: Vignesh Raghavendra
---
configs/j721e_evm_a72_defconfig | 8
1 file changed, 8 insertions(+)
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index
. Clients can use unique configuration ID flags to get different
configuration data from DMA driver.
Signed-off-by: Vignesh Raghavendra
---
drivers/dma/dma-uclass.c | 12
include/dma-uclass.h | 11 +++
include/dma.h| 11 +++
3 files changed, 34 insertions
Add DT nodes related to DMA and CPSW to -u-boot.dtsi to get networking
up on J721e EVM.
Signed-off-by: Vignesh Raghavendra
---
.../k3-j721e-common-proc-board-u-boot.dtsi| 268 ++
1 file changed, 268 insertions(+)
diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u
and configs.
Vignesh Raghavendra (6):
dma: Introduce dma_get_cfg() interface
dma: ti: k3-udma: Implement dma_get_cfg() interface
net: ti: am65-cpsw-nuss: Rework RX flow ID handling
net: ti: am65-cpsw-nuss: Add new compatible for J721e
arm: dts: k3-j721e-common-proc-board: Add DMA and CPSW
Add new compatible to handle J721e SoC
Signed-off-by: Vignesh Raghavendra
---
drivers/net/ti/am65-cpsw-nuss.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
index 2e14f4be862f..b606ff0ade2a 100644
--- a/drivers/net/ti/am65
MA channel. In order for basic ethernet to work, CPSW slave must be
aware of the flow ID allocated for the RX channel by the DMA driver.
This interface allows CPSW to query flow ID from DMA provider and
configure it in CPSW HW.
Signed-off-by: Vignesh Raghavendra
---
drivers/dma/ti/k3-udma.c
Now that arch specific dma mapping APIs take care of cache
flush/invalidate, drop local cache flush operation.
Signed-off-by: Vignesh Raghavendra
---
drivers/net/macb.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index
Drop local dma_map_single() and dma_unmap_single() and use arch specific
common implementation
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/nand/raw/denali.c | 34 +++---
1 file changed, 3 insertions(+), 31 deletions(-)
diff --git a/drivers/mtd/nand/raw
Drop local dma_map_single() and dma_unmap_single() and use arch specific
common implementation
Signed-off-by: Vignesh Raghavendra
---
drivers/mmc/tmio-common.c | 25 +++--
1 file changed, 3 insertions(+), 22 deletions(-)
diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc
etc..)
Update arch specific dma_map_single() and dma_unmap_single() APIs to do
cache flush/invalidate operations, so that drivers need not implement
them locally.
Signed-off-by: Vignesh Raghavendra
---
arch/arm/include/asm/dma-mapping.h | 22 --
arch/nds32/include/asm/dma
file so that per driver implementation of these APIs can
be avoided.
I don't have all the affected hardwares. Would greatly appreciate if
these patches work fine on the affected platforms.
Vignesh Raghavendra (4):
asm: dma-mapping.h: Fix dma mapping functions
mmc: tmio-common: Drop custom dma
Add stub for dma_memcpy() and dma_get_device when CONFIG_DMA is
disabled. This avoids ifdefs in driver code using DMA APIs
Signed-off-by: Vignesh Raghavendra
---
include/dma.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/include/dma.h b/include/dma.h
index d1c3d0df7d91
Rename CONFIG_SPL_DMA_SUPPORT to CONFIG_SPL_DMA. This allows to use
macros such as CONFIG_IS_ENABLED() that allow conditional compilation of
code for SPL and U-Boot.
Signed-off-by: Vignesh Raghavendra
---
common/spl/Kconfig | 2 +-
configs/am57xx_evm_defconfig | 2
Hi,
On 14/11/19 4:44 PM, Lokesh Vutla wrote:
>
>
> On 14/11/19 2:44 PM, Vignesh Raghavendra wrote:
>> Instead of looking getting reference to SYSFW device using name which
>> is not guaranteed to be constant, use phandle supplied in the DT node to
>> get referenc
Cast pointers properly so as to avoid warnings when driver is built for
32 bit platforms
Signed-off-by: Vignesh Raghavendra
---
drivers/dma/ti/k3-udma.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index
Exposed ring mode works well with 32 bit and 64 bit cores without need
for Proxies for 32 bit cores. Therefore switch to exposed ring mode.
Signed-off-by: Vignesh Raghavendra
---
drivers/dma/ti/k3-udma.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/ti/k3
Remove redundant coherency checks before calling cache ops in UDMA
driver. This is now handled in arch specific cache operation
implementation based on Kconfig option
Signed-off-by: Vignesh Raghavendra
---
drivers/dma/ti/k3-udma.c | 50 +---
1 file changed
Instead of looking getting reference to SYSFW device using name which
is not guaranteed to be constant, use phandle supplied in the DT node to
get reference to SYSFW
Signed-off-by: Vignesh Raghavendra
---
drivers/soc/ti/k3-navss-ringacc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion
Flush caches when pushing an element to ring and invalidate caches when
popping an element from ring in Exposed Ring mode. Otherwise DMA
transfers don't work properly in R5 SPL (with caches enabled) where the
core is not in coherency domain.
Reviewed-by: Grygorii Strashko
Signed-off-by: Vignesh
Fix up the debug prints that were dumping state of TCHAN RT registers to
use tchan for MEM_TO_DEV transfers.
Signed-off-by: Vignesh Raghavendra
---
drivers/dma/ti/k3-udma.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3
Instead of looking getting reference to SYSFW device using name which
is not guaranteed to be constant, use phandle supplied in the DT node to
get reference to SYSFW
Signed-off-by: Vignesh Raghavendra
---
drivers/dma/ti/k3-udma.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
UDMA always expects 64 bit address pointer of the transfer descriptor in
the Ring. But on 32 bit cores like R5, pointer is always 32 bit in size.
Therefore copy over 32 bit pointer value to 64 bit variable before
pushing it over to the ring, so that upper 32 bits are 0s.
Signed-off-by: Vignesh
Add new compatible to handle UDMA support for J721e SoC
Signed-off-by: Vignesh Raghavendra
---
drivers/dma/ti/k3-udma.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index ebf773d9ca67..7336bad99412 100644
--- a/drivers/dma/ti/k3-udma.c
Import few basic bitmap functions (bitmap_{weight,fill,set,clear,or}())
and their dependencies from Linux. These are required for upcoming DMA
resource allocation support for TI's K3 SoCs.
Signed-off-by: Vignesh Raghavendra
---
include/linux/bitmap.h | 133
On K3 SoCs, DMA channels are shared across multiple entities, therefore
U-Boot DMA driver needs to query resource range from centralised
resource management controller i.e SystemFirmware and use DMA channels
allocated for A72 host. Add support for the same.
Signed-off-by: Vignesh Raghavendra
Vignesh Raghavendra (11):
lib: Import few bitmap functions from Linux
dma: ti: k3-udma: Query DMA channels allocated from Resource Manager
soc: ti: k3-navss-ringacc: Flush/invalidate caches on ring push/pop
soc: ti: k3-navss-ringacc: Get SYSFW reference from DT phandle
dma: ti: k3-udma
On 12/11/19 4:57 PM, Simon Goldschmidt wrote:
> On Tue, Nov 12, 2019 at 10:30 AM Tan, Ley Foon wrote:
>>
[...]
But, unfortunately, such stub does not exists for clk_get_rate().
So on platforms w/o CONFIG_CLK set:
arm-linux-gnueabihf-ld.bfd: drivers/spi/built-in.o: in
On 12/11/19 2:44 PM, Simon Goldschmidt wrote:
> On Tue, Nov 12, 2019 at 9:59 AM Tan, Ley Foon wrote:
>>
>>
>>
>>> -Original Message-
>>> From: Simon Goldschmidt
>>> Sent: Tuesday, November 12, 2019 5:43 AM
>>> To: Jaga
On 10/11/19 5:11 PM, Vignesh Raghavendra wrote:
> Hi Simon,
>
> On 24-Oct-19 11:53 PM, Simon Goldschmidt wrote:
>> From: Simon Goldschmidt
>>
>> Support loading clk speed via DM instead of requiring ad-hoc code.
>>
>> Signed-off-by: Simon Goldschmi
Hi Simon,
On 24-Oct-19 11:53 PM, Simon Goldschmidt wrote:
> From: Simon Goldschmidt
>
> Support loading clk speed via DM instead of requiring ad-hoc code.
>
> Signed-off-by: Simon Goldschmidt
> Signed-off-by: Simon Goldschmidt
> ---
[...]
> @@ -22,12 +23,29 @@ static int
Static checker warns 'ret' variable may be used uninitialized in
spi_nor_erase() and spi_nor_write() in case of zero length requests.
Fix these warnings by checking for zero length requests and returning
early.
Reported-by: Dan Murphy
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/spi/spi
Hi Simon,
On 07/11/19 1:25 AM, Simon Goldschmidt wrote:
> Hi Vignesh,
>
> On Thu, Oct 17, 2019 at 2:31 PM Vignesh Raghavendra wrote:
>>
>> Hi Simon,
>>
>> On 17/10/19 4:50 PM, Simon Goldschmidt wrote:
>>> On Mon, Oct 14, 2019 at 3:27 PM Vignesh Raghaven
Hi JJ,
On 05/11/19 5:20 PM, Jean-Jacques Hiblot wrote:
> This will probe the multiplexer devices that have a "u-boot,mux-autoprobe"
> property. As a consequence they will be put in their idle state.
>
> Signed-off-by: Jean-Jacques Hiblot
>
> ---
[...]
> diff --git a/drivers/mux/mux-uclass.c
x-idk: Configure the CDCE913 clock
synthesizer")
Reported-by: Sam Protsenko
Signed-off-by: Vignesh Raghavendra
---
drivers/usb/dwc3/dwc3-generic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 40
301 - 400 of 536 matches
Mail list logo
