From: Hou Zhiqiang
Add a new callback release_core to the cpu_ops, which is used to
release a CPU core to run baremetal or RTOS application on a SoC
with multiple CPU cores.
Signed-off-by: Hou Zhiqiang
---
drivers/cpu/cpu-uclass.c | 10 ++
include/cpu.h| 15 +++
From: Hou Zhiqiang
Add a new subcommand 'release' to bring up a core to run baremetal
and RTOS applications.
For example on i.MX8M Plus EVK, release the LAST core to run a RTOS
application, passing the sequence number of the CPU core to release,
here it is 3:
u-boot=> cpu list
0:
From: Hou Zhiqiang
Enable the 'cpu' command to display the CPU info and release CPU core to
run baremetal or RTOS applications.
Signed-off-by: Hou Zhiqiang
---
configs/imx93_11x11_evk_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/imx93_11x11_evk_defconfig
From: Hou Zhiqiang
Enable the 'cpu' command and the depended imx CPU driver to
display the CPU info and release CPU core to run baremetal
or RTOS applications.
Signed-off-by: Hou Zhiqiang
---
configs/imx8mm_evk_defconfig | 3 +++
configs/imx8mn_evk_defconfig | 3 +++
From: Hou Zhiqiang
Release the secondary cores through the PSCI request.
Signed-off-by: Hou Zhiqiang
---
drivers/cpu/imx8_cpu.c | 26 +-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c
index
From: Hou Zhiqiang
This patch set is to add a subcommand 'release' to the 'cpu' command
in cmd/cpu.c, making the command is able to release a core to run
baremetal and RTOS applications.
And enabled the 'cpu' command and imx CPU driver for i.MX 8M series
EVK boards and i.MX 93 EVK board.
Hou
From: Tao Yang
Enable the cpu command support for the default config.
Signed-off-by: Tao Yang
Signed-off-by: Hou Zhiqiang
---
configs/imx93_11x11_evk_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/imx93_11x11_evk_defconfig
b/configs/imx93_11x11_evk_defconfig
index
From: Tao Yang
Add definition for determining the implemented CPU numbers.
Signed-off-by: Tao Yang
Signed-off-by: Hou Zhiqiang
---
include/configs/imx93_evk.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h
From: Tao Yang
Implement the cpu command to kick cpu core to run barematel or RTOS
applications.
Signed-off-by: Tao Yang
Signed-off-by: Hou Zhiqiang
---
arch/arm/mach-imx/imx9/Makefile | 4 +-
arch/arm/mach-imx/imx9/mp.c | 81 +
2 files changed, 84
From: Hou Zhiqiang
This patch set is to enable the 'cpu' command for i.MX93 EVK,
so that it can kick one CPU core to run the barematel or RTOS
applicatons under U-Boot.
Tao Yang (3):
mp: imx9: add cpu command support
imx93_evk: add definition CONFIG_MAX_CPUS
configs: imx93-11x11-evk:
From: Hou Zhiqiang
Implement the cpu command to kick cpu core to run barematel or RTOS
applications.
Signed-off-by: Hou Zhiqiang
Signed-off-by: Yi Zhao
Signed-off-by: Jiafei Pan
---
arch/arm/mach-imx/imx8m/Makefile | 3 +-
arch/arm/mach-imx/imx8m/mp.c | 100
From: Jiafei Pan
Enable the cpu command support for the default config.
Signed-off-by: Jiafei Pan
Signed-off-by: Hou Zhiqiang
---
configs/imx8mm_evk_defconfig | 1 +
configs/imx8mn_ddr4_evk_defconfig | 1 +
configs/imx8mp_evk_defconfig | 1 +
3 files changed, 3 insertions(+)
diff
From: Hou Zhiqiang
This patch set is to enable the 'cpu' command for i.MX8M Plus,
Mini and Nano EVK, so that it can kick one CPU core to run the
barematel or RTOS applicatons under U-Boot.
Hou Zhiqiang (1):
mp: imx8m: add cpu command support
Jiafei Pan (1):
mp: imx8m: enable CONFIG_MP to
From: Hou Zhiqiang
The current implementation needs the caller provides the memory region
for the property and pending tables and the number of re-distibutor,
and it doesn't handle the address alignment of the tables and doesn't
help to add the reserved-memory node for the tables.
This patch
From: Hou Zhiqiang
The Layerscape platforms have different RCW header value from FSL
PowerPC platforms, the current image header verification callback
is only working on PowerPC, it will fail on Layerscape, this patch
is to fix this issue.
This is a historical problem and exposed by the
From: Hou Zhiqiang
Let the check pass when patches have these patterns in their context.
Signed-off-by: Hou Zhiqiang
---
scripts/checkpatch.pl | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index 5696d3a5f3..cf59e2bb70 100755
From: Hou Zhiqiang
The current fixup of LX2160A PCIe nodes is based on non-production
rev1 silicon, and in Linux the nodes have been updated for rev2
silicon, so update the searching compatible string to match the
kernel changes. And for compatibility with the rev1 nodes, move
forward the board
From: Hou Zhiqiang
The current fixup of LX2160A PCIe nodes is based on non-production
rev1 silicon, and in Linux the nodes have been updated for rev2
silicon, so update the searching compatible string to match the
kernel changes. And for compatibility with the rev1 nodes, move
forward the board
From: Hou Zhiqiang
In the current code, it doesn't reset the cursors of LUT entry and
StreamID at the beginning of the fixup, so it can result in LUT entry
setup and msi-map mismatch and LUT entries and StreamID leaking
when reload and fixup the DTB.
This patch move the initialization of LUT
From: Hou Zhiqiang
In the current code, it doesn't reset the cursors of LUT entry and
StreamID at the beginning of the fixup, so it can result in LUT entry
setup and msi-map mismatch and LUT entries and StreamID leaking
when reload and fixup the DTB.
This patch move the initialization of LUT
From: Hou Zhiqiang
On Layerscape platforms, the DTB is loaded from boot filesystem,
per the fdt_addr description in doc/README.distro, it must be
removed.
Signed-off-by: Hou Zhiqiang
---
V2:
- Removed unrelated description in change log.
include/configs/ls1012a2g5rdb.h | 1 -
From: Hou Zhiqiang
On Layerscape platforms, the DTB is loaded from boot filesystem,
per the fdt_addr description in doc/README.distro, it must be
removed.
And on many platforms, like ls1046a, ls1088a, ls2088a and lx216xa,
the 'fdt_addr' pointed address is not accessible.
And with the current
From: Hou Zhiqiang
The feature BOOTENV_SHARED_EFI is not supported on layerscape
boards, it didn't result kernel boot crash previously since
there isn't the efi/boot/"BOOTEFI_NAME" and it skip calling of
'boot_efi_binary'.
But since the commit f3866909e350 ("distro_bootcmd: call EFI
bootmgr
From: Hou Zhiqiang
Fix a memory leak issue in the RX port initialization.
Signed-off-by: Hou Zhiqiang
---
drivers/net/fm/eth.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 0e89e663f7..7c23ccc1f0 100644
---
From: Hou Zhiqiang
Added check for return value of e1000_read_phy_reg().
Signed-off-by: Hou Zhiqiang
---
drivers/net/e1000.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index 694114eca7..1f0d559415 100644
---
From: Hou Zhiqiang
As on some incipient Layerscape platforms (LS1043A series) there isn't
separate PF control register block, these registers reside in the LUT
register block, so when the driver detected there isn't 'ctrl', it will
assign the 'lut' address to the ls_pcie->ctrl.
The current code
From: Hou Zhiqiang
The GICv3 RM requires "The first 1KB of memory for the LPI Pending tables
must contain only zeros on initial allocation, and this must be visible
to the Redistributors, or else the effect is UNPREDICTABLE".
And as the following statement, we here clear the whole Pending
From: Hou Zhiqiang
The GICv3 RM requires "The first 1KB of memory for the LPI Pending tables
must contain only zeros on initial allocation, and this must be visible
to the Redistributors, or else the effect is UNPREDICTABLE".
And as the following statement, we here clear the whole Pending
From: Hou Zhiqiang
The GICv3 RM requires "The first 1KB of memory for the LPI Pending tables
must contain only zeros on initial allocation, and this must be visible
to the Redistributors, or else the effect is UNPREDICTABLE".
And as the following statement, we here clear the whole Pending
From: Hou Zhiqiang
Drop the CONFIG_VIDEO to fix the following build warning.
= WARNING ==
This board does not use CONFIG_DM_VIDEO Please update
the board to use CONFIG_DM_VIDEO before the v2019.07 release.
UPD include/generated/dt.h
Failure to update
From: Hou Zhiqiang
Enable the I-Cache to speed up the boot time, especailly for the NOR
boot, currently it takes about 15 seconds from power up to the U-Boot
prompt, and with the I-Cache enabled it only takes around 2.5 seconds.
Signed-off-by: Hou Zhiqiang
---
arch/arm/cpu/armv7/ls102xa/cpu.c
From: Hou Zhiqiang
LX2162A is not like LX2160A which has different PCIe controller
in rev1 and rev2 silicon. It supports only one configuration of
PCIe controller, which is same as LS2088A. So update PCIe
compatible string same as LS2088A.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/Kconfig |
From: Hou Zhiqiang
This patch moves the SVR definitions to a new svr.h for
Layerscape armv7 and armv8 platforms respectively, so that
the PCIe driver can reuse them.
Signed-off-by: Hou Zhiqiang
---
V2:
- rebase the patch and correct the typos in the subject
From: Hou Zhiqiang
The commit 8ec619f8fd84 added the PCIe EP nodes fixup of LX2160A, but it
didn't update the condition value when there isn't a property 'apio-wins'.
Fixes: 8ec619f8fd84 ("pci: layerscape: Fixup PCIe EP mode DT nodes for LX2160A
rev2")
Signed-off-by: Hou Zhiqiang
---
From: Hou Zhiqiang
The register to enable/disable the write-permission of DBI RO
registers should be accessed via the CFG_ADDR/CFG_DATA registers
instead of accessing directly.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/pcie_fsl.c | 20
drivers/pci/pcie_fsl.h | 2 ++
2
From: Hou Zhiqiang
LX2160A rev2 uses different PCIe controller, so EP mode DT
nodes also need to be fixed up.
Signed-off-by: Hou Zhiqiang
---
V2:
- Fix a dead loop issue.
drivers/pci/pcie_layerscape_fixup_common.c | 28 ++
1 file changed, 28 insertions(+)
diff --git
From: Hou Zhiqiang
P2020RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII switch VSC7385
eTSEC2: Connected to SGMII PHY VSC8221
eTSEC3: Connected to SGMII PHY AR8021
Signed-off-by: Hou Zhiqiang
---
V6:
- No
From: Hou Zhiqiang
P1010RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII PHY AR8033
eTSEC2: Connected to SGMII PHY AR8033
eTSEC3: Connected to SGMII PHY AR8033
Signed-off-by: Hou Zhiqiang
---
V6:
- No change.
From: Hou Zhiqiang
Enable the DM_ETH and DM_MDIO config.
Signed-off-by: Hou Zhiqiang
---
V6:
- No change.
configs/P1010RDB-PA_36BIT_NAND_defconfig | 2 ++
configs/P1010RDB-PA_36BIT_NOR_defconfig | 2 ++
configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 2 ++
From: Hou Zhiqiang
The board_eth_init() is only used by legacy ethernet driver framework,
so do not compile it when DM_ETH config has been selected.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V6:
- No change.
board/freescale/p1010rdb/p1010rdb.c | 2 ++
1 file changed, 2
From: Vladimir Oltean
The tsec driver now requires DM_MDIO when DM_ETH is enabled. To avoid
build errors, enable DM_MDIO in these boards' configs before we actually
add DM_MDIO support to tsec.
Signed-off-by: Vladimir Oltean
Signed-off-by: Hou Zhiqiang
---
V6:
- No code change, just move it
From: Hou Zhiqiang
Enable the DM_ETH and DM_MDIO config.
On P2020RDB, the eTSEC1 is connecting with a switch VSC7385,
so also enable the fixed PHY support.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V6:
- No change.
configs/P2020RDB-PC_36BIT_NAND_defconfig | 3 +++
From: Hou Zhiqiang
Enable the DM_ETH and DM_MDIO config.
On P1020RDB, the eTSEC1 is connecting with a switch VSC7385,
so also enable the fixed PHY support.
Signed-off-by: Hou Zhiqiang
---
V6:
- No change.
configs/P1020RDB-PC_36BIT_NAND_defconfig | 3 +++
From: Hou Zhiqiang
For the platforms on which the eTSEC driver uses DM_ETH, convert its
MDIO controller code to also use DM_MDIO.
Note that for handling the TBI PHY (the MAC PCS for SGMII), we still
don't register a udevice for it, since we can drive it locally and there
is no point in doing
From: Hou Zhiqiang
P1020RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII switch VSC7385
eTSEC2: Connected to SGMII PHY VSC8221
eTSEC3: Connected to SGMII PHY AR8021
Signed-off-by: Hou Zhiqiang
Reviewed-by:
From: Hou Zhiqiang
Add the environment 'vscfw_addr' to assign a default address for
vsc7385 firmware uploading.
Signed-off-by: Hou Zhiqiang
---
V6:
- No change.
include/configs/p1_p2_rdb_pc.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/p1_p2_rdb_pc.h
From: Hou Zhiqiang
The board_eth_init() is only used by legacy ethernet driver framework,
so do not compile it when DM_ETH config has been selected.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V6:
- No change.
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 ++
1 file
From: Hou Zhiqiang
The cpu_eth_init() is only used by the legacy ethernet driver framework.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V6:
- No change.
arch/powerpc/cpu/mpc8xxx/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c
From: Vladimir Oltean
It is utterly pointless to require an MDIO bus pointer for a fixed PHY
device. The fixed.c implementation does not require it, only
phy_device_create. Fix that.
Signed-off-by: Vladimir Oltean
Signed-off-by: Hou Zhiqiang
Reviewed-by: Hou Zhiqiang
---
V6:
- No change.
From: Hou Zhiqiang
Move vsc7835 firmware uploading to board_early_init_r(), so that
the switch also can work in DM eTSEC driver.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V6:
- No change.
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 35 +++--
1 file
From: Hou Zhiqiang
The info of fixed-link PHY is described in DT node instead of
getting from MII, so detect the fixed-link PHY DT node first,
if it doesn't exist then probe the MII.
Signed-off-by: Vladimir Oltean
Signed-off-by: Hou Zhiqiang
---
V6:
- No change.
drivers/net/tsec.c | 5
From: Hou Zhiqiang
The MII management register block offset is different between
gianfar and etsec2 compatible devices, this patch is to fix
this issue by adding driver data for different compatible
string.
Fixes: 2932c5a802a9 ("net: tsec: fsl_mdio: add DM MDIO support")
Signed-off-by: Hou
From: Hou Zhiqiang
Use virtual address to access the MII block registers instead
of physical address.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V6:
- No change.
drivers/net/fsl_mdio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Hou Zhiqiang
Add compatible string "gianfar" support and update the
device-tree-bindings doc.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V6:
- No change.
doc/device-tree-bindings/net/fsl-tsec-phy.txt | 2 +-
drivers/net/tsec.c| 16
From: Hou Zhiqiang
This patchset is to convert P1010, P1020 and P2020 RDB boards to DM_ETH.
V5:
Merged the following thread:
https://patchwork.ozlabs.org/project/uboot/list/?series=174343=both=*
Hou Zhiqiang (16):
net: fsl_mdio: Change to use virtual address
net: fsl_mdio: Correct the MII
From: Vladimir Oltean
The tsec driver now requires DM_MDIO when DM_ETH is enabled. To avoid
build errors, enable DM_MDIO in these boards' configs before we actually
add DM_MDIO support to tsec.
Signed-off-by: Vladimir Oltean
Signed-off-by: Hou Zhiqiang
---
V6:
- No code change, just move it
From: Hou Zhiqiang
P2020RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII switch VSC7385
eTSEC2: Connected to SGMII PHY VSC8221
eTSEC3: Connected to SGMII PHY AR8021
Signed-off-by: Hou Zhiqiang
---
V6:
- No
From: Hou Zhiqiang
Enable the DM_ETH and DM_MDIO config.
Signed-off-by: Hou Zhiqiang
---
V6:
- No change.
configs/P1010RDB-PA_36BIT_NAND_defconfig | 2 ++
configs/P1010RDB-PA_36BIT_NOR_defconfig | 2 ++
configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 2 ++
From: Hou Zhiqiang
Enable the DM_ETH and DM_MDIO config.
On P2020RDB, the eTSEC1 is connecting with a switch VSC7385,
so also enable the fixed PHY support.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V6:
- No change.
configs/P2020RDB-PC_36BIT_NAND_defconfig | 3 +++
From: Hou Zhiqiang
P1020RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII switch VSC7385
eTSEC2: Connected to SGMII PHY VSC8221
eTSEC3: Connected to SGMII PHY AR8021
Signed-off-by: Hou Zhiqiang
Reviewed-by:
From: Hou Zhiqiang
Enable the DM_ETH and DM_MDIO config.
On P1020RDB, the eTSEC1 is connecting with a switch VSC7385,
so also enable the fixed PHY support.
Signed-off-by: Hou Zhiqiang
---
V6:
- No change.
configs/P1020RDB-PC_36BIT_NAND_defconfig | 3 +++
From: Hou Zhiqiang
The board_eth_init() is only used by legacy ethernet driver framework,
so do not compile it when DM_ETH config has been selected.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V6:
- No change.
board/freescale/p1010rdb/p1010rdb.c | 2 ++
1 file changed, 2
From: Hou Zhiqiang
The board_eth_init() is only used by legacy ethernet driver framework,
so do not compile it when DM_ETH config has been selected.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V6:
- No change.
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 ++
1 file
From: Hou Zhiqiang
P1010RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII PHY AR8033
eTSEC2: Connected to SGMII PHY AR8033
eTSEC3: Connected to SGMII PHY AR8033
Signed-off-by: Hou Zhiqiang
---
V6:
- No change.
From: Hou Zhiqiang
Add compatible string "gianfar" support and update the
device-tree-bindings doc.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V6:
- No change.
doc/device-tree-bindings/net/fsl-tsec-phy.txt | 2 +-
drivers/net/tsec.c| 16
From: Hou Zhiqiang
The cpu_eth_init() is only used by the legacy ethernet driver framework.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V6:
- No change.
arch/powerpc/cpu/mpc8xxx/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c
From: Hou Zhiqiang
Add the environment 'vscfw_addr' to assign a default address for
vsc7385 firmware uploading.
Signed-off-by: Hou Zhiqiang
---
V6:
- No change.
include/configs/p1_p2_rdb_pc.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/p1_p2_rdb_pc.h
From: Hou Zhiqiang
Move vsc7835 firmware uploading to board_early_init_r(), so that
the switch also can work in DM eTSEC driver.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V6:
- No change.
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 35 +++--
1 file
From: Hou Zhiqiang
The info of fixed-link PHY is described in DT node instead of
getting from MII, so detect the fixed-link PHY DT node first,
if it doesn't exist then probe the MII.
Signed-off-by: Vladimir Oltean
Signed-off-by: Hou Zhiqiang
---
V6:
- No change.
drivers/net/tsec.c | 5
From: Vladimir Oltean
It is utterly pointless to require an MDIO bus pointer for a fixed PHY
device. The fixed.c implementation does not require it, only
phy_device_create. Fix that.
Signed-off-by: Vladimir Oltean
Signed-off-by: Hou Zhiqiang
Reviewed-by: Hou Zhiqiang
---
V6:
- No change.
From: Hou Zhiqiang
The MII management register block offset is different between
gianfar and etsec2 compatible devices, this patch is to fix
this issue by adding driver data for different compatible
string.
Fixes: 2932c5a802a9 ("net: tsec: fsl_mdio: add DM MDIO support")
Signed-off-by: Hou
From: Hou Zhiqiang
Use virtual address to access the MII block registers instead
of physical address.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V6:
- No change.
drivers/net/fsl_mdio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Hou Zhiqiang
For the platforms on which the eTSEC driver uses DM_ETH, convert its
MDIO controller code to also use DM_MDIO.
Note that for handling the TBI PHY (the MAC PCS for SGMII), we still
don't register a udevice for it, since we can drive it locally and there
is no point in doing
From: Hou Zhiqiang
This patchset is to convert P1010, P1020 and P2020 RDB boards to DM_ETH.
V5:
Merged the following thread:
https://patchwork.ozlabs.org/project/uboot/list/?series=174343=both=*
Hou Zhiqiang (16):
net: fsl_mdio: Change to use virtual address
net: fsl_mdio: Correct the MII
From: Hou Zhiqiang
This patch moves the SVR definitiones to a new svr.h for
Layerscape armv7 and armv8 platforms respectively, so that
the PCIe driver can reuse them.
Signed-off-by: Hou Zhiqiang
---
.../arm/include/asm/arch-fsl-layerscape/soc.h | 30 +---
From: Hou Zhiqiang
LX2160A rev2 uses different PCIe controller, so EP mode DT
nodes also need to be fixed up.
Signed-off-by: Hou Zhiqiang
---
drivers/pci/pcie_layerscape_fixup_common.c | 26 ++
1 file changed, 26 insertions(+)
diff --git
From: Hou Zhiqiang
The workaround of LPI one-way reset issue is broken by the series:
https://patchwork.ozlabs.org/project/uboot/list/?series=192398
This patch is to add DT node for GIC RD tables and create corresponding
reserved-memory node in kernel DT to fix it.
Signed-off-by: Hou Zhiqiang
From: Hou Zhiqiang
P1020RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII switch VSC7385
eTSEC2: Connected to SGMII PHY VSC8221
eTSEC3: Connected to SGMII PHY AR8021
Signed-off-by: Hou Zhiqiang
Reviewed-by:
From: Hou Zhiqiang
Enable the DM_ETH and DM_MDIO config.
On P2020RDB, the eTSEC1 is connecting with a switch VSC7385,
so also enable the fixed PHY support.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V5:
- No change.
configs/P2020RDB-PC_36BIT_NAND_defconfig | 3 +++
From: Hou Zhiqiang
P2020RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII switch VSC7385
eTSEC2: Connected to SGMII PHY VSC8221
eTSEC3: Connected to SGMII PHY AR8021
Signed-off-by: Hou Zhiqiang
---
V5:
- No
From: Hou Zhiqiang
Move vsc7835 firmware uploading to board_early_init_r(), so that
the switch also can work in DM eTSEC driver.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V5:
- No change.
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 35 +++--
1 file
From: Hou Zhiqiang
The board_eth_init() is only used by legacy ethernet driver framework,
so do not compile it when DM_ETH config has been selected.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V5:
- No change.
board/freescale/p1010rdb/p1010rdb.c | 2 ++
1 file changed, 2
From: Hou Zhiqiang
Enable the DM_ETH and DM_MDIO config.
Signed-off-by: Hou Zhiqiang
---
V5:
- No change.
configs/P1010RDB-PA_36BIT_NAND_defconfig | 2 ++
configs/P1010RDB-PA_36BIT_NOR_defconfig | 2 ++
configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 2 ++
From: Hou Zhiqiang
P1010RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII PHY AR8033
eTSEC2: Connected to SGMII PHY AR8033
eTSEC3: Connected to SGMII PHY AR8033
Signed-off-by: Hou Zhiqiang
---
V5:
- No change.
From: Hou Zhiqiang
Add the environment 'vscfw_addr' to assign a default address for
vsc7385 firmware uploading.
Signed-off-by: Hou Zhiqiang
---
V5:
- No change.
include/configs/p1_p2_rdb_pc.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/p1_p2_rdb_pc.h
From: Hou Zhiqiang
Enable the DM_ETH and DM_MDIO config.
On P1020RDB, the eTSEC1 is connecting with a switch VSC7385,
so also enable the fixed PHY support.
Signed-off-by: Hou Zhiqiang
---
V5:
- No change.
configs/P1020RDB-PC_36BIT_NAND_defconfig | 3 +++
From: Hou Zhiqiang
The board_eth_init() is only used by legacy ethernet driver framework,
so do not compile it when DM_ETH config has been selected.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V5:
- No change.
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 ++
1 file
From: Hou Zhiqiang
The info of fixed-link PHY is described in DT node instead of
getting from MII, so detect the fixed-link PHY DT node first,
if it doesn't exist then probe the MII.
Signed-off-by: Vladimir Oltean
Signed-off-by: Hou Zhiqiang
---
V5:
- No change.
drivers/net/tsec.c | 5
From: Hou Zhiqiang
For the platforms on which the eTSEC driver uses DM_ETH, convert its
MDIO controller code to also use DM_MDIO.
Note that for handling the TBI PHY (the MAC PCS for SGMII), we still
don't register a udevice for it, since we can drive it locally and there
is no point in doing
From: Hou Zhiqiang
Add compatible string "gianfar" support and update the
device-tree-bindings doc.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V5:
- No change.
doc/device-tree-bindings/net/fsl-tsec-phy.txt | 2 +-
drivers/net/tsec.c| 16
From: Hou Zhiqiang
The cpu_eth_init() is only used by the legacy ethernet driver framework.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V5:
- No change.
arch/powerpc/cpu/mpc8xxx/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c
From: Vladimir Oltean
The tsec driver now requires DM_MDIO when DM_ETH is enabled. To avoid
build errors, enable DM_MDIO in these boards' configs before we actually
add DM_MDIO support to tsec.
Signed-off-by: Vladimir Oltean
Signed-off-by: Hou Zhiqiang
---
V5:
- Pick from
From: Vladimir Oltean
It is utterly pointless to require an MDIO bus pointer for a fixed PHY
device. The fixed.c implementation does not require it, only
phy_device_create. Fix that.
Signed-off-by: Vladimir Oltean
Reviewed-by: Hou Zhiqiang
Signed-off-by: Hou Zhiqiang
---
V5:
- Pick from
From: Hou Zhiqiang
Use virtual address to access the MII block registers instead
of physical address.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
---
V5:
- No change.
drivers/net/fsl_mdio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Hou Zhiqiang
The MII management register block offset is different between
gianfar and etsec2 compatible devices, this patch is to fix
this issue by adding driver data for different compatible
string.
Fixes: 2932c5a802a9 ("net: tsec: fsl_mdio: add DM MDIO support")
Signed-off-by: Hou
From: Hou Zhiqiang
This patchset is to convert P1010, P1020 and P2020 RDB boards to DM_ETH.
V5:
Merged the following thread:
https://patchwork.ozlabs.org/project/uboot/list/?series=174343=both=*
Hou Zhiqiang (16):
net: fsl_mdio: Change to use virtual address
net: fsl_mdio: Correct the MII
From: Hou Zhiqiang
Add Root Complex and Endpoint mode specific config entries, such that
it's feasible to enable the RC and/or EP mode driver indepently.
Signed-off-by: Hou Zhiqiang
---
V2:
- New patch.
configs/ls1012afrdm_qspi_defconfig| 2 +-
configs/ls1012afrdm_tfa_defconfig
From: Xiaowei Bao
Add the INBOUND configuration for VFs of PF.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
---
V2:
- Rebase the patch without change intent.
drivers/pci/pcie_layerscape.c| 8 +---
drivers/pci/pcie_layerscape.h| 13 +++-
From: Xiaowei Bao
Add the PCIe EP mode support for lx2160a-v2 platform.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
---
V2:
- Rebase the patch without change intent.
drivers/pci/pcie_layerscape.h| 9 -
drivers/pci/pcie_layerscape_ep.c | 8 +++-
2 files changed,
From: Xiaowei Bao
Modify the ls_pcie_dump_atu function, make it can print the INBOUND
windows registers.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
---
V2:
- Rebase the patch without change intent.
drivers/pci/pcie_layerscape.c| 25 +
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