ll occupy the address range starting from 0x1000.
Signed-off-by: Chee Hong Ang
---
configs/socfpga_agilex_atf_defconfig| 71
configs/socfpga_stratix10_atf_defconfig | 73 +
2 files changed, 144 insertions(+)
create mode 10064
SPL already setup the Clock Manager with the handoff data
from OCRAM. When the Clock Manager's driver get probed again
in SSBL, it shall skip the handoff data access in OCRAM.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/wrap_pll_config_s10.c | 3 ++-
1 file changed, 2 insertions
Since SSBL is running in DRAM, it shall setup the stack in DRAM
instead of OCRAM which is occupied by SPL and handoff data.
Signed-off-by: Chee Hong Ang
---
include/configs/socfpga_soc64_common.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/configs/socfpga_soc64_common.h
b
In non-secure mode (EL2), FPGA reconfiguration driver calls the
SMC/PSCI services provided by ATF to configure the FPGA.
Signed-off-by: Chee Hong Ang
---
drivers/fpga/intel_sdm_mb.c | 139
1 file changed, 139 insertions(+)
diff --git a/drivers/fpga
In non-secure mode (EL2), Reset Manager driver calls the
SMC/PSCI service provided by ATF to enable/disable the
SOCFPGA bridges.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/reset_manager_s10.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/mach-socfpga
mbox_reset_cold() will invoke ATF's PSCI service when running in
non-secure mode (EL2).
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/mailbox_s10.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c
b/arch/arm/mach-socfpga/mailbox_s10.c
index
In non-secure mode (EL2), MAC driver calls the SMC/PSCI services
provided by ATF to setup the PHY interface.
Signed-off-by: Chee Hong Ang
---
drivers/net/dwmac_socfpga.c | 43 +
1 file changed, 39 insertions(+), 4 deletions(-)
diff --git a/drivers/net
bitstream FPGA reconfiguration, Remote
System Update (RSU) and etc.
Signed-off-by: Chee Hong Ang
---
include/linux/intel-smc.h | 573 ++
1 file changed, 573 insertions(+)
create mode 100644 include/linux/intel-smc.h
diff --git a/include/linux/intel-smc.h b/include
Standard PSCI function "CPU_ON" provided by ATF is now used
by Linux kernel to bring up the secondary CPUs to enable SMP
booting in Linux on SoC 64bits platform.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/Kconfig | 2 --
1 file changed, 2 deletions(-)
diff --git a/arc
In non-secure mode (EL2), MMC driver calls the SMC/PSCI services
provided by ATF to set SDMMC's DRVSEL and SMPLSEL.
Signed-off-by: Chee Hong Ang
---
drivers/mmc/socfpga_dw_mmc.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc
Override 'lowlevel_init' to make sure secondary CPUs trapped
in ATF instead of SPL. After ATF is initialized, it will signal
the secondary CPUs to jump from SPL to ATF waiting to be 'activated'
by Linux OS via PSCI call.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/Makefile
which invokes
the ATF's PSCI runtime service (function ID: INTEL_SIP_SMC_MBOX_SEND_CMD)
to send mailbox messages to Secure Device Manager (SDM).
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/Makefile | 2 +
arch/arm/mach-socfpga/include/mach/smc_api.h | 13 +
arch/arm
Instead of loading u-boot proper image (u-boot.img), SPL
now loads FIT image (u-boot.itb) which includes u-boot
proper, ATF and u-boot proper's DTB.
Signed-off-by: Chee Hong Ang
---
include/configs/socfpga_soc64_common.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/configs
Generate a FIT image for Intel SOCFPGA (64bits) which
include U-boot proper, ATF and DTB for U-boot proper.
Signed-off-by: Chee Hong Ang
---
board/altera/soc64/fit_spl_atf.sh | 91 +++
1 file changed, 91 insertions(+)
create mode 100755 board/altera/soc64
are allowed to override this 'weak' function in their
specific board implementation.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/board.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index
CONFIG_OF_EMBED was primarily enabled to support the S10/Agilex
spl hex file requirements. Since this option now produces a
warning during build, and the spl hex can be created using
alternate methods, CONFIG_OF_EMBED is no longer needed.
Signed-off-by: Chee Hong Ang
---
configs
pport for SoCFPGA SoC64 platforms
https://lists.denx.de/pipermail/u-boot/2020-August/422509.html
arm: socfpga: soc64: Disable CONFIG_PSCI_RESET
https://lists.denx.de/pipermail/u-boot/2020-August/423373.html
Chee Hong Ang (16):
arm: socfpga: soc64: Remove CONFIG_OF_EMBED
arm: socfpga: soc64: Add FIT ge
Don't invoke 'SYSTEM_RESET' PSCI function because PSCI
function calls are not supported by u-boot running in EL3.
Signed-off-by: Chee Hong Ang
---
configs/socfpga_agilex_defconfig| 1 +
configs/socfpga_stratix10_defconfig | 1 +
2 files changed, 2 insertions(+)
diff --git a/configs
Foon Tan
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/mailbox_s10.c | 40 ++---
1 file changed, 31 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c
b/arch/arm/mach-socfpga/mailbox_s10.c
index a9ec818492..18d44924e6 100644
--- a/arch
Add miliseconds delay when waiting for mailbox event to happen
before timeout. This will ensure the timeout duration is predictive.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/mailbox_s10.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/arch/arm
From: Ley Foon Tan
Sync latest mailbox response codes from SDM firmware.
Signed-off-by: Ley Foon Tan
Signed-off-by: Chee Hong Ang
---
.../mach-socfpga/include/mach/mailbox_s10.h | 38 ++-
1 file changed, 36 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-socfpga
Fixes:
- Proper timeout implementation
- Always read mailbox response data before returning
mailbox status to caller
Enhancement:
- Auto retry on mailbox sending
- Send large mailbox message
Chee Hong Ang (3):
arm: socfpga: mailbox: Refactor mailbox timeout event handling
arm: socfpga
Mailbox command which is too large to fit into the mailbox
FIFO command buffer can be sent to SDM in multiple parts.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/mailbox_s10.c | 113 +++-
1 file changed, 78 insertions(+), 35 deletions(-)
diff --git a/arch/arm
Mailbox driver should always check for the length of the response
and read the response data before returning the response status to
caller.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/mailbox_s10.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm
-padding).
4 x (SPL(64KB) + zero-padding(64KB)) = 512KB
Signed-off-by: Chee Hong Ang
---
v3 changes:
- add 'u-boot-splx4.sfp' make target (4 x SPL image without paddings)
- add 'u-boot-spl-padx4.sfp' make target (4 x SPL image with 64KB paddings)
- Update commit message (refer to commit message
is followed by
64KB of zero-padding).
Signed-off-by: Chee Hong Ang
---
Makefile | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/Makefile b/Makefile
index 4483a9b..f4631f1 100644
--- a/Makefile
+++ b/Makefile
@@ -1582,8 +1582,9 @@ u-boot.spr: spl/u-boot-spl.img u
Add timeout waiting for NOC idle ACK during FPGA bridge
disable/enable.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/reset_manager_s10.c | 25 -
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c
b/arch/arm
Enable FPGA full reconfiguration support with Intel FPGA SDM
Mailbox driver for Agilex.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/Kconfig | 1 +
drivers/fpga/Kconfig | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch
- Rename Stratix10 FPGA driver to 'Intel FPGA SDM Mailbox'.
- Add watchdog reset when configuring the FPGA.
- Enable 'Intel FPGA SDM Mailbox' for Agilex.
Chee Hong Ang (3):
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox
fpga: intel_sdm_mb: Add watchdog reset
arm: socfpga
Ensure watchdog reset is not triggered if the fpga
reconfiguration is taking too long.
Signed-off-by: Chee Hong Ang
---
drivers/fpga/intel_sdm_mb.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/fpga/intel_sdm_mb.c b/drivers/fpga/intel_sdm_mb.c
index 3508231191..9a1dc2c0c8
Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver
because it is using generic SDM (Secure Device Manager) Mailbox
interface shared by other platform (e.g. Agilex) as well.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/Kconfig| 2 +-
arch/arm/mach-socfpga
All SoCFPGA platforms (except Cyclone V) are now switching
to CONFIG_WDT (driver model for watchdog timer drivers)
from CONFIG_HW_WATCHDOG.
Signed-off-by: Chee Hong Ang
---
arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi| 4
arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi | 4
arch
Instead of querying SDM for FPGA configuration status through mailbox
messages, U-Boot now checks System Manager's FPGA Config status register
for FPGA configuration status before resetting bridge.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/include/mach/misc.h | 5
All SoCFPGA platforms (except Cyclone V) are now switching
to CONFIG_WDT (driver model for watchdog timer drivers)
from CONFIG_HW_WATCHDOG.
Signed-off-by: Chee Hong Ang
---
arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 4
arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi | 4
arch/arm
Show reset information such as reset types (cold/warm) and
which events triggered the reset.
Chee Hong Ang (2):
arm: socfpga: soc64: Add SDM triggered warm reset bit mask
arm: socfpga: soc64: Show reset state in SPL
.../include/mach/reset_manager_soc64.h | 12 ++--
arch
Include SDM triggered warm reset bit (BIT1) in Reset Manager's stat
register when checking for HPS warm reset status.
Refactor the warm reset mask macro for clarity purpose.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h | 11 +--
1 file
Print reset state (warm/cold) together with the
source (watchdog/MPU) which has triggered the warm
reset on S10 & Agilex.
Signed-off-by: Chee Hong Ang
---
.../include/mach/reset_manager_soc64.h | 1 +
arch/arm/mach-socfpga/reset_manager_s10.c
Instead of querying SDM for FPGA configuration status through mailbox
messages, U-Boot now checks System Manager's FPGA Config status register
for FPGA configuration status before resetting bridge.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/include/mach/misc.h | 5
Enable sysreset support for Agilex platform.
Signed-off-by: Chee Hong Ang
---
arch/arm/Kconfig | 2 +-
drivers/sysreset/Kconfig | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 03fc614..617d5ad 100644
--- a/arch/arm/Kconfig
Rename S10 sysreset driver to common name (SoC64).
SoCFPGA sysreset driver supports S10 and Agilex platforms now.
Chee Hong Ang (2):
sysreset: socfpga: soc64: Rename SYSRESET SoCFPGA driver for S10 to
SoC64
sysreset: socfpga: agilex: Enable sysreset support
arch/arm/Kconfig
Rename the driver from S10 to SoC64 because Intel Agilex platform
also using the this SYSRESET SoCFPGA driver for S10.
Signed-off-by: Chee Hong Ang
---
arch/arm/Kconfig| 2 +-
drivers/sysreset/Kconfig
, watchdog shall be triggered and Remote System Update mechanism
shall load the next production image or factory safe image.
Signed-off-by: Chin Liang See
Signed-off-by: Chee Hong Ang
---
configs/socfpga_agilex_defconfig| 1 +
configs/socfpga_stratix10_defconfig | 1 +
2 files changed, 2
If the QSPI clock is not set (read as 0), QSPI driver probe shall fail
and prevent further QSPI access.
Signed-off-by: Chee Hong Ang
---
drivers/spi/cadence_qspi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 1e85749209
Enable sysreset support for Agilex platform.
Signed-off-by: Chee Hong Ang
---
arch/arm/Kconfig | 2 +-
drivers/sysreset/Kconfig | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6b8a32c38d..105b5f08a9 100644
--- a/arch
device.
This patch prevent the driver from disable/enable the QSPI
controller too soon and inadvertently halting any ongoing flash
read/write access by ensuring the QSPI controller is always in
idle mode after each read/write access.
Signed-off-by: Chee Hong Ang
---
drivers/spi/cadence_qspi_apb.c
Generate spl/u-boot-splx4.sfp which consist of 4 SPL images required
for booting up Cyclone5/Arria10.
Signed-off-by: Chee Hong Ang
---
Makefile | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Makefile b/Makefile
index 2629a74..13429a0 100644
--- a/Makefile
+++ b
Timer only need to be initialized once in SPL.
This patch remove the redundancy of initializing the
timer again in U-Boot proper
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/timer_s10.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga
'dwmac_socfpga' driver will setup the PHY interface during probe.
PHY interface setup in arch_misc_init() is no longer needed.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/misc_s10.c | 84 +---
1 file changed, 1 insertion(+), 83 deletions(-)
diff --git
Add additional membus writes to configure main and peripheral PLL
for Agilex's clock manager.
Signed-off-by: Chee Hong Ang
---
drivers/clk/altera/clk-agilex.c | 94 +++--
1 file changed, 78 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/altera/clk-agilex.c
being setup by SPL (Clock Manager NOT in 'boot
mode') to prevent any inaccurate clocking issues happened on HPS
peripherals such as UART, MAC and etc.
Signed-off-by: Chee Hong Ang
---
drivers/clk/altera/clk-agilex.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/clk/altera
- Add clock enable.
- Add clock source for NAND.
- Add additional PLL configurations via mebus writes.
- U-Boot proper will not re-initialize the clock again if it's already
initialized by SPL.
Chee Hong Ang (2):
clk: agilex: Handle clock configuration differently in SPL and U-Boot
proper
From: Ley Foon Tan
Add get nand_clk and nand_x clock support.
Signed-off-by: Ley Foon Tan
Signed-off-by: Chee Hong Ang
---
drivers/clk/altera/clk-agilex.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c
index 0042958f4c
Tan
Signed-off-by: Chee Hong Ang
---
drivers/clk/altera/clk-agilex.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c
index 2ef9292f93..b5cf187364 100644
--- a/drivers/clk/altera/clk-agilex.c
+++ b/drivers/clk/altera/clk
From: "Ang, Chee Hong"
Booting Agilex and Stratix 10 with ATF support.
SPL now loads ATF (BL31), U-Boot proper and DTB from FIT
image. The new boot flow with ATF support is as follow:
SPL -> ATF (BL31) -> U-Boot proper -> OS (Linux)
U-Boot proper now starts at 0x20 (CONFIG_SYS_TEXT_BASE).
From: Chee Hong Ang
mbox_reset_cold() will invoke ATF's PSCI service when running in
non-secure mode (EL2).
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/mailbox_s10.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c
b/arch/arm/mach-socfpga
From: Chee Hong Ang
In non-secure mode (EL2), FPGA reconfiguration driver calls the
SMC/PSCI services provided by ATF to configure the FPGA.
Signed-off-by: Chee Hong Ang
---
drivers/fpga/stratix10.c | 141 ++-
1 file changed, 140 insertions(+), 1
From: Chee Hong Ang
In non-secure mode (EL2), MAC driver calls the SMC/PSCI services
provided by ATF to setup the PHY interface.
Signed-off-by: Chee Hong Ang
---
drivers/net/dwmac_socfpga.c | 43 +++
1 file changed, 39 insertions(+), 4 deletions
From: Chee Hong Ang
Initialize timer in SPL running in secure mode (EL3)
and skip timer initialization in U-Boot proper running in
non-secure mode (EL2).
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/timer_s10.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
From: Chee Hong Ang
In non-secure mode (EL2), Reset Manager driver calls the
SMC/PSCI services provided by ATF to enable/disable the
SOCFPGA bridges.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/reset_manager_s10.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch
From: Chee Hong Ang
In EL3, do_bridge_reset() directly send mailbox commands to SDM to
query the FPGA configuration status. If running in non-secure
mode (EL2), it invokes SMC service calls to ATF (EL3) to perform the
query.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/misc_s10.c
From: Chee Hong Ang
'dwmac_socfpga' driver will setup the PHY interface during probe.
PHY interface setup in arch_misc_init() is no longer needed.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/misc_s10.c | 85 +---
1 file changed, 1 insertion
From: Chee Hong Ang
In non-secure mode (EL2), MMC driver calls the SMC/PSCI services
provided by ATF to set SDMMC's DRVSEL and SMPLSEL.
Signed-off-by: Chee Hong Ang
---
drivers/mmc/socfpga_dw_mmc.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/mmc
From: Chee Hong Ang
This header file defines the Secure Monitor Call (SMC) message
protocol for ATF (BL31) PSCI runtime services. It includes all
the PSCI SiP function identifiers for the secure runtime services
provided by ATF. The secure runtime services include System Manager's
registers
From: Chee Hong Ang
Override 'lowlevel_init' to make sure secondary CPUs
trapped in ATF instead of SPL. After ATF is initialized,
it will signal the secondary CPUs to jump from SPL to
ATF waiting to be 'activated' by Linux OS via PSCI call.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach
From: Chee Hong Ang
Allow U-Boot proper running in non-secure mode (EL2) to invoke
SMC call to ATF's PSCI runtime services such as System Manager's
registers access, 2nd phase bitstream FPGA reconfiguration,
Remote System Update (RSU) and etc.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach
From: Chee Hong Ang
Standard PSCI function "CPU_ON" provided by ATF is now used
by Linux kernel to bring up the secondary CPUs to enable
SMP booting in Linux on SoC 64bits platform.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/Kconfig | 2 --
1 file changed, 2 deletion
on:
https://lists.denx.de/pipermail/u-boot/2019-September/384906.html
Ang, Chee Hong (1):
configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF
support
Chee Hong Ang (16):
configs: agilex: Remove CONFIG_OF_EMBED
arm: socfpga: add fit source file for pack itb with ATF
arm: so
From: Chee Hong Ang
Add board_fit_config_name_match() for matching board name with
device tree files in FIT image. This will ensure correct DTB
file is loaded for different board type. Currently, we are not
supporting multiple device tree files in FIT image therefore this
function basically do
From: Chee Hong Ang
Generate a FIT image for Intel SOCFPGA (64bits) which
include U-boot proper, ATF and DTB for U-boot proper.
Signed-off-by: Chee Hong Ang
---
board/altera/soc64/its/fit_spl_atf.its | 52 ++
1 file changed, 52 insertions(+)
create mode 100644
From: Chee Hong Ang
CONFIG_OF_EMBED was primarily enabled to support the agilex
spl hex file requirements. Since this option now produces a
warning during build, and the spl hex can be created using
alternate methods, CONFIG_OF_EMBED is no longer needed.
Signed-off-by: Chee Hong Ang
From: Chee Hong Ang
Instead of loading u-boot proper image (u-boot.img), SPL
now loads FIT image (u-boot.itb) which includes u-boot
proper, ATF and u-boot proper's DTB.
Signed-off-by: Chee Hong Ang
---
include/configs/socfpga_soc64_common.h | 4
1 file changed, 4 insertions(+)
diff
From: Chee Hong Ang
Booting Agilex and Stratix 10 without ATF support.
SPL -> U-Boot proper -> OS (Linux)
Signed-off-by: Chee Hong Ang
---
configs/socfpga_agilex_nofw_defconfig| 59 ++
configs/socfpga_stratix10_nofw_defconfi
From: Chee Hong Ang
mbox_reset_cold() will invoke ATF's PSCI service when running in
non-secure mode (EL2).
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/mailbox_s10.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c
b/arch/arm/mach-socfpga
From: Chee Hong Ang
In non-secure mode (EL2), FPGA reconfiguration driver calls the
SMC/PSCI services provided by ATF to configure the FPGA.
Signed-off-by: Chee Hong Ang
---
drivers/fpga/stratix10.c | 141 ++-
1 file changed, 140 insertions(+), 1
From: Chee Hong Ang
Initialize timer in SPL running in secure mode (EL3)
and skip timer initialization in U-Boot proper running in
non-secure mode (EL2).
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/timer_s10.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
From: Chee Hong Ang
In EL3, do_bridge_reset() directly send mailbox commands to SDM to
query the FPGA configuration status. If running in non-secure
mode (EL2), it invokes SMC service calls to ATF (EL3) to perform the
query.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/misc_s10.c
From: Chee Hong Ang
In non-secure mode (EL2), Reset Manager driver calls the
SMC/PSCI services provided by ATF to enable/disable the
SOCFPGA bridges.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/reset_manager_s10.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch
From: Chee Hong Ang
MAC driver now access System Manger's EMAC0/EMAC1/EMAC2 registers
to set PHY mode via 'altera_sysmgr' driver.
Signed-off-by: Chee Hong Ang
---
drivers/net/dwmac_socfpga.c | 37 +
1 file changed, 17 insertions(+), 20 deletions(-)
diff
From: Chee Hong Ang
MMC driver now access System Manager's SDMMC control register
to set SDMMC's clock phase shift via 'altera_sysmgr' driver.
Following entry need to be specified under MMC node in device tree:
altr,sysmgr-syscon = < 'x' 'y' 'z'>;
x = offset of the SDMCC control re
From: Chee Hong Ang
Enable this misc driver model for 'altera_sysmgr' driver for
socfpga platforms.
Signed-off-by: Chee Hong Ang
---
arch/arm/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8d9f7fc..4ee8ae0 100644
--- a/arch/arm/Kconfig
From: Chee Hong Ang
In device tree for all socfpga platforms, a phandle to System Manager
('altr,sysmgr-syscon') is needed for MMC node to enable the MMC driver
to configure the SDMMC's clock phase shift via System Manager driver
(altera_sysmgr).
This phandle specifies the offset of the SDMCC
From: Chee Hong Ang
This header file defines the Secure Monitor Call (SMC) message
protocol for ATF (BL31) PSCI runtime services. It includes all
the PSCI SiP function identifiers for the secure runtime services
provided by ATF. The secure runtime services include System Manager's
registers
From: Chee Hong Ang
Allow U-Boot proper running in non-secure mode (EL2) to invoke
SMC call to ATF's PSCI runtime services such as System Manager's
registers access, 2nd phase bitstream FPGA reconfiguration,
Remote System Update (RSU) and etc.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach
From: Chee Hong Ang
'dwmac_socfpga' driver will setup the PHY interface during probe.
PHY interface setup in arch_misc_init() is no longer needed.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/misc_s10.c | 85 +---
1 file changed, 1 insertion
From: Chee Hong Ang
Override 'lowlevel_init' to make sure secondary CPUs
trapped in ATF instead of SPL. After ATF is initialized,
it will signal the secondary CPUs to jump from SPL to
ATF waiting to be 'activated' by Linux OS via PSCI call.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach
From: Chee Hong Ang
This driver (misc uclass) handle the read/write access to
System Manager. For 64 bits platforms, processor needs to be
in secure mode to has write access to most of the System Manager's
registers (except boot scratch registers). When the processor is
running in EL2 (non
From: Chee Hong Ang
Instead of loading u-boot proper image (u-boot.img), SPL
now loads FIT image (u-boot.itb) which includes u-boot
proper, ATF and u-boot proper's DTB.
Signed-off-by: Chee Hong Ang
---
include/configs/socfpga_soc64_common.h | 4
1 file changed, 4 insertions(+)
diff
From: Chee Hong Ang
Standard PSCI function "CPU_ON" provided by ATF is now used
by Linux kernel to bring up the secondary CPUs to enable
SMP booting in Linux on SoC 64bits platform.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/Kconfig | 2 --
1 file changed, 2 deletion
From: Chee Hong Ang
SPL now loads ATF (BL31), U-Boot proper and DTB from FIT
image. The new boot flow with ATF support is as follow:
SPL -> ATF (BL31) -> U-Boot proper -> OS (Linux)
U-Boot proper now starts at 0x20 (CONFIG_SYS_TEXT_BASE).
ATF will occupy the address range star
From: Chee Hong Ang
Add board_fit_config_name_match() for matching board name with
device tree files in FIT image. This will ensure correct DTB
file is loaded for different board type. Currently, we are not
supporting multiple device tree files in FIT image therefore this
function basically do
From: Chee Hong Ang
CONFIG_OF_EMBED was primarily enabled to support the agilex
spl hex file requirements. Since this option now produces a
warning during build, and the spl hex can be created using
alternate methods, CONFIG_OF_EMBED is no longer needed.
Signed-off-by: Chee Hong Ang
From: Chee Hong Ang
Generate a FIT image for Intel SOCFPGA (64bits) which
include U-boot proper, ATF and DTB for U-boot proper.
Signed-off-by: Chee Hong Ang
---
board/altera/soc64/its/fit_spl_atf.its | 52 ++
1 file changed, 52 insertions(+)
create mode 100644
access System Manager via the System Manager driver
v3:
https://lists.denx.de/pipermail/u-boot/2020-February/400986.html
These patchsets have dependency on:
https://lists.denx.de/pipermail/u-boot/2019-September/384906.html
Chee Hong Ang (21):
configs: agilex: Remove CONFIG_OF_EMBED
arm: so
From: Chee Hong Ang
Replace FDT API with more generic ofnode API.
Signed-off-by: Chee Hong Ang
---
drivers/clk/altera/clk-arria10.c | 52 +++-
1 file changed, 25 insertions(+), 27 deletions(-)
diff --git a/drivers/clk/altera/clk-arria10.c b/drivers/clk
From: Chee Hong Ang
This commit (82de42fa14682d408da935adfb0f935354c5008f) calls child's
ofdata_to_platdata() method before the parent is probed in dm core.
This has caused the driver no longer able to get the correct parent
clock's register base in the ofdata_to_platdata() method because
a()
method is called. Adjust the logic slightly so that probing parents is
not done until afterwards.
Signed-off-by: Simon Glass
These patchsets fix the A10 driver issue and replce the FDT API with
ofnode API.
Chee Hong Ang (2):
clk: socfpga: Read the clock parent's register base in probe func
From: Chee Hong Ang
mbox_reset_cold() will invoke ATF's PSCI service when running in
non-secure mode (EL2).
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/mailbox_s10.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c
b/arch/arm/mach-socfpga
From: Chee Hong Ang
FPGA recpnfiguration driver will call the ATF's PSCI runtime
services if it's running in non-secure mode (EL2).
Signed-off-by: Chee Hong Ang
---
drivers/fpga/stratix10.c | 141 ++-
1 file changed, 140 insertions(+), 1 deletion
From: Chee Hong Ang
Booting Agilex and Stratix 10 without ATF support.
SPL -> U-Boot proper -> OS (Linux)
Signed-off-by: Chee Hong Ang
---
configs/socfpga_agilex_nofw_defconfig| 59 ++
configs/socfpga_stratix10_nofw_defconfi
From: Chee Hong Ang
Allow MAC driver to access System Manager's EMAC control
registers in non-secure mode.
Signed-off-by: Chee Hong Ang
---
drivers/net/dwmac_socfpga.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net
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