Hi U-Boot,
I've been given a MIPS reference board with a fairly old vendor U-Boot
on it. It does seem to support the Mutli-File Image format but I'm
running into an issue where the kernel expects the initrd on a page
boundary.
I'm using a command like the following to produce and image
cat
On 1/05/24 14:41, Tom Rini wrote:
> Remove from this board vendor directory and when needed
> add missing include files directly.
>
> Signed-off-by: Tom Rini
> ---
> Cc: Chris Packham
Reviewed-by: Chris Packham
> ---
> board/alliedtelesis/SBx81LIFKW/sbx81lif
On 1/05/24 14:40, Tom Rini wrote:
> Remove from this board vendor directory and when needed
> add missing include files directly.
>
> Signed-off-by: Tom Rini
> ---
> Cc: Stefan Roese
> Cc: Chris Packham
> Cc: Tony Dinh
> Cc: Jason Cooper
> Cc: Siddarth Gore
tected at PEB 125
> ubi0: run torture test for PEB 125
> ubi0: fixable bit-flip detected at PEB 125
> ubi0 error: torture_peb: read problems on freshly erased PEB 125,
> must be bad
> ubi0 error: erase_worker: failed to erase PEB 125, error -5
> ubi0: mark PEB 125 as bad
>
>
On Fri, 10 Nov 2023, 10:33 am Tom Rini, wrote:
> On Fri, Oct 27, 2023 at 01:22:37PM -0400, Tom Rini wrote:
> > On Fri, Oct 27, 2023 at 10:49:47AM +0100, Pierre-Clément Tosi wrote:
> > > Hi Chris,
> > >
> > > On Fri, Oct 27, 2023 at 01:23:51PM +1300, Chris
Hi Tom,
On Fri, 27 Oct 2023, 1:54 pm Tom Rini, wrote:
> On Fri, Oct 27, 2023 at 01:44:11PM +1300, Chris Packham wrote:
>
> > The ATF implementation for AC5/AC5X ends up with bl31 living in some
> > internal SRAM. This is in the middle of the large MMIO region that we
>
-off-by: Chris Packham
---
arch/arm/mach-mvebu/alleycat5/cpu.c | 66 ++---
1 file changed, 51 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-mvebu/alleycat5/cpu.c
b/arch/arm/mach-mvebu/alleycat5/cpu.c
index 8204d9627515..0f72ae1709be 100644
--- a/arch/arm/mach
this series is the best course of action.
Signed-off-by: Chris Packham
---
arch/arm/cpu/armv8/cache_v8.c | 16 +---
arch/arm/include/asm/armv8/mmu.h | 14 --
arch/arm/include/asm/global_data.h | 1 -
3 files changed, 5 insertions(+), 26 deletions(-)
diff --git
this series is the best course of action.
Signed-off-by: Chris Packham
---
arch/arm/cpu/armv8/cache_v8.c | 14 --
arch/arm/include/asm/global_data.h | 1 -
2 files changed, 4 insertions(+), 11 deletions(-)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
this series is the best course of action.
Signed-off-by: Chris Packham
---
arch/arm/cpu/armv8/cache_v8.c| 6 +-
arch/arm/include/asm/armv8/mmu.h | 10 ++
2 files changed, 3 insertions(+), 13 deletions(-)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
As discussed this series reverts the HAFDBS changes that caused an issue
on AC5/AC5X. I think there are some improvements that can be made to the
initial memory map for the AC5/AC5X but so far nothing I've found makes
it compatible with the HAFDBS changes.
Chris Packham (3):
Revert "
On Sat, 21 Oct 2023, 2:04 am Marc Zyngier, wrote:
> On 2023-10-18 21:53, Chris Packham wrote:
> > Since commit 6cdf6b7a340d ("arm64: Use FEAT_HAFDBS to track dirty pages
> > when available") the default get_page_table_size() sets some flags for
> > more efficie
On Fri, 20 Oct 2023, 7:18 pm Stefan Roese, wrote:
> Hi Chris,
>
> On 10/18/23 22:53, Chris Packham wrote:
> > Since commit 6cdf6b7a340d ("arm64: Use FEAT_HAFDBS to track dirty pages
> > when available") the default get_page_table_size() sets some flags for
>
le fixed page table size rather than
trying to duplicate the more complicated logic to optimise the table
size.
Signed-off-by: Chris Packham
---
arch/arm/mach-mvebu/alleycat5/cpu.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-mvebu/alleycat5/cpu.c
b/arch/arm/mach-mv
On Tue, Oct 17, 2023 at 12:21 AM Marc Zyngier wrote:
>
> On Mon, 16 Oct 2023 02:42:08 +0100,
> Chris Packham wrote:
> >
> > On Sun, Oct 15, 2023 at 10:29 AM Chris Packham
> > wrote:
> > >
> > >
> > >
> > > On Sat, 14 Oct 2023, 1
On Sun, Oct 15, 2023 at 10:29 AM Chris Packham wrote:
>
>
>
> On Sat, 14 Oct 2023, 11:04 am Marc Zyngier, wrote:
>>
>> On 2023-10-13 03:40, Chris Packham wrote:
>> > Hi Marc, Paul,
>> >
>> > On Sat, Mar 18, 2023 at 5:23 AM Ying-Chun Liu (P
On Sat, 14 Oct 2023, 11:04 am Marc Zyngier, wrote:
> On 2023-10-13 03:40, Chris Packham wrote:
> > Hi Marc, Paul,
> >
> > On Sat, Mar 18, 2023 at 5:23 AM Ying-Chun Liu (PaulLiu)
> > wrote:
> >>
> >> From: Marc Zyngier
> >>
> >&g
is because the physical address of the RAM on the AC5X SoC is
above the 32GiB boundary. As we don't need SMBIOS or EFI this can be
safely disabled.
Signed-off-by: Chris Packham
---
This probably should have been part of the series I sent as
https://lore.kernel.org/u-boot/20231003035800.2626121-1
Hi Marc, Paul,
On Sat, Mar 18, 2023 at 5:23 AM Ying-Chun Liu (PaulLiu)
wrote:
>
> From: Marc Zyngier
>
> Some recent arm64 cores have a facility that allows the page
> table walker to track the dirty state of a page. This makes it
> really efficient to perform CMOs by VA as we only need to look
offload feature so is not susceptible to the lockup.
We can therefore safely return to using the built-in I2C controller.
Signed-off-by: Chris Packham
---
arch/arm/dts/ac5-98dx35xx-atl-x240.dts | 30 ++
configs/x240_defconfig | 1 -
2 files changed, 7
the physical address of the RAM on the AC5X SoC is
above the 32GiB boundary. As we don't need SMBIOS or EFI this can be
safely disabled.
Signed-off-by: Chris Packham
---
configs/x240_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/x240_defconfig b/configs/x240_defconfig
The cn9130.dtsi defines a pinctrl node for SPI1 (until recently it was
mislabeled as spi0). Use this instead of having a duplicate definition
with a different label.
Signed-off-by: Chris Packham
---
arch/arm/dts/cn9130-crb.dtsi | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff
The CN9130-DB uses the SPI1 interface but had the pinctrl node labelled
as "cp0_spi0_pins". Use the label "cp0_spi1_pins" and update the node
name to "cp0-spi-pins-1" to avoid confusion with the pinctrl options for
SPI0.
Signed-off-by: Chris Packham
---
arch/arm/d
On Mon, Jul 31, 2023 at 9:29 AM Pierre Bourdon wrote:
>
> On Sun, Jul 30, 2023 at 11:21 PM Chris Packham
> wrote:
> > On Sun, Jul 30, 2023 at 6:08 AM Pierre Bourdon wrote:
> > >
> > > Chunked raw reads get accumulated to the data buffer, but in some
> &g
On Mon, 31 Jul 2023, 9:29 am Pierre Bourdon, wrote:
> On Sun, Jul 30, 2023 at 11:21 PM Chris Packham
> wrote:
> > On Sun, Jul 30, 2023 at 6:08 AM Pierre Bourdon
> wrote:
> > >
> > > Chunked raw reads get accumulated to the data buffer, but in some
> > >
Hi Pierre,
On Sun, Jul 30, 2023 at 6:08 AM Pierre Bourdon wrote:
>
> Chunked raw reads get accumulated to the data buffer, but in some
> ECC configurations they can end up being larger than the originally
> computed size (write page size + OOB size). For example:
>
> 4K page size, ECC strength
controller and avoids
triggering the Errata.
Signed-off-by: Chris Packham
Reviewed-by: Stefan Roese
---
Changes in v2:
- Update i2c0 alias
- Move i2c-gpio definition to root of device tree
- Remove instead of just disabling it
- Add r-by from Stefan
arch/arm/dts/ac5-98dx35xx-atl-x240.dts | 30
gpio_request_list_by_name() returns the number of gpios requested.
Notably it swallows the underlying -ENOENT when the "gpios" property
does not exist.
Update the i2c-gpio driver to check for ret == 0 before trying the new
sda-gpios/scl-gpios properties.
Signed-off-by: Chr
Hi Me,
On Thu, Jul 20, 2023 at 3:03 PM Chris Packham wrote:
>
> There is an Errata with the built-in I2C controller where various I2C
> hardware errors cause a complete lockup of the CPU (which eventually
> results in an watchdog reset).
>
> Put the I2C MPP pins into GPIO mo
controller and avoids
triggering the Errata.
Signed-off-by: Chris Packham
---
This is dependent on a bug-fix for the i2c-gpio driver I just sent
out[1] (sorry I should have sent them as a series but I thought this
would take me longer to test than it did).
[1] -
https://lore.kernel.org/u-boot
gpio_request_list_by_name() returns the number of gpios requested.
Notably it swallows the underlying -ENOENT when the "gpios" property
does not exist.
Update the i2c-gpio driver to check for ret == 0 before trying the new
sda-gpios/scl-gpios properties.
Signed-off-by: Chr
In some designs the MAX313xx RTC may need calibration to cope with
oscillator inaccuracies. Provide read8/write8 ops so that the registers
can be accessed. Because the driver covers a range of MAX313xx variants
no attempt is made to ensure the register is valid.
Signed-off-by: Chris Packham
The sar-reg0 alias was left over from an earlier iteration of the
patches adding support for this board. Remove the unused alias.
Fixes: 6cc8b5db40 ("arm: mvebu: Add RD-AC5X board")
Signed-off-by: Chris Packham
---
arch/arm/dts/ac5-98dx35xx-rd.dts | 1 -
1 file changed, 1 deletio
The x240 and SE240 are a series of L2+ switches from Allied Telesis.
There are a number of them in the range but as far as U-Boot is
concerned all the CPU block components are the same so there's only one
board defined.
Signed-off-by: Chris Packham
---
Notes:
Changes in v2:
- drop
unless the NfArbiterEn bit is set. Setting the bit enables
arbitration between the Device Bus and the NAND flash.
Since there is no obvious downside in enabling this for designs that
don't require arbitration, we always enable it.
Signed-off-by: Chris Packham
---
drivers/mtd/nand/raw/pxa3xx_nand.c
The NAND flash controller (NFC) on the AC5/AC5X SoC is the same as
the NFC used on other Marvell SoCs. It does have the additional
restriction of only supporting SDR timing modes up to 3.
Signed-off-by: Chris Packham
---
drivers/mtd/nand/raw/pxa3xx_nand.c | 17 ++---
1 file changed
The NF_CLK for the AC5 SoC runs at 400MHz. There's no strapping
or gating require so just add a mvebu_get_nand_clock() that
returns this value.
Signed-off-by: Chris Packham
---
arch/arm/mach-mvebu/alleycat5/soc.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-mvebu
The AC5/AC5X SoC has a NAND flash controller. Add this to the
SoC device tree.
Signed-off-by: Chris Packham
---
arch/arm/dts/ac5-98dx25xx.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/dts/ac5-98dx25xx.dtsi b/arch/arm/dts/ac5-98dx25xx.dtsi
index 3c68355f323a
hing the NAND
driver.
Chris Packham (6):
arm: mvebu: ac5: Add nand-controller node
arm: mvebu: ac5: Define mvebu_get_nand_clock()
mtd: nand: pxa3xx: Add support for the Marvell AC5 SoC
mtd: nand: pxa3xx: Enable devbus/nand arbiter on Armada 8K
arm: mvebu: Add Allied Telesis x240 board
arm:
On Mon, Jul 3, 2023 at 3:39 PM Chris Packham wrote:
>
> The x240 and SE240 are a series of L2+ switches from Allied Telesis.
> There are a number of them in the range but as far as U-Boot is
> concerned all the CPU block components are the same so there's only one
> board defined.
The sar-reg0 alias was left over from an earlier iteration of the
patches adding support for this board. Remove the unused alias.
Fixes: 6cc8b5db40 ("arm: mvebu: Add RD-AC5X board")
Signed-off-by: Chris Packham
---
arch/arm/dts/ac5-98dx35xx-rd.dts | 1 -
1 file changed, 1 deletio
The x240 and SE240 are a series of L2+ switches from Allied Telesis.
There are a number of them in the range but as far as U-Boot is
concerned all the CPU block components are the same so there's only one
board defined.
Signed-off-by: Chris Packham
---
arch/arm/dts/Makefile
unless the NfArbiterEn bit is set. Setting the bit enables
arbitration between the Device Bus and the NAND flash.
Since there is no obvious downside in enabling this for designs that
don't require arbitration, we always enable it.
Signed-off-by: Chris Packham
---
drivers/mtd/nand/raw/pxa3xx_nand.c
The NAND flash controller (NFC) on the AC5/AC5X SoC is the same as
the NFC used on other Marvell SoCs. It does have the additional
restriction of only supporting SDR timing modes up to 3.
Signed-off-by: Chris Packham
---
drivers/mtd/nand/raw/pxa3xx_nand.c | 17 ++---
1 file changed
The AC5/AC5X SoC has a NAND flash controller. Add this to the
SoC device tree.
Signed-off-by: Chris Packham
---
arch/arm/dts/ac5-98dx25xx.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/dts/ac5-98dx25xx.dtsi b/arch/arm/dts/ac5-98dx25xx.dtsi
index 3c68355f323a
The NF_CLK for the AC5 SoC runs at 400MHz. There's no strapping
or gating require so just add a mvebu_get_nand_clock() that
returns this value.
Signed-off-by: Chris Packham
---
arch/arm/mach-mvebu/alleycat5/soc.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-mvebu
hing the NAND
driver.
Chris Packham (6):
arm: mvebu: ac5: Add nand-controller node
arm: mvebu: ac5: Define mvebu_get_nand_clock()
mtd: nand: pxa3xx: Add support for the Marvell AC5 SoC
mtd: nand: pxa3xx: Enable devbus/nand arbiter on Armada 8K
arm: mvebu: Add Allied Telesis x240 board
arm:
Answering my own question (I think)
On Mon, Jul 3, 2023 at 12:10 PM Chris Packham wrote:
>
> Hi,
>
> I'm looking to upstream support for a new board with the Marvell AC5X
> SoC and some NAND driver changes to support the SoC/board. I've got
> things working when chain loading v
Hi,
I'm looking to upstream support for a new board with the Marvell AC5X
SoC and some NAND driver changes to support the SoC/board. I've got
things working when chain loading vendor based u-boot -> upstream
u-boot but when I boot directly the NAND controller reports
"pxa3xx-nand
set is added
Signed-off-by: Chris Packham
Reviewed-by: Simon Glass
---
Changes in v2:
- Enable in sandbox for compile testing
- Note feature omissions in Kconfig
- Incorporate review comments from Simon
- Collect r-by from Simon
configs/sandbox_defconfig | 1 +
drivers/rtc/Kconfig |
The find_closest() macro can be used to find an element in a sorted
array that is closest to an input value. Bring in this macro from
Linux v6.3-rc1-2-g8ca09d5fa354.
Signed-off-by: Chris Packham
Reviewed-by: Simon Glass
---
Changes in v2:
- Add note on which Linux version this came from
- Enable in sandbox for compile testing
- Note feature omissions in Kconfig
- Incorporate review comments from Simon
- Collect r-by from Simon
Chris Packham (2):
include: kernel.h: port find_closest() from Linux
drivers: rtc: add max313xx series rtc driver
configs/sandbox_defconfig | 1 +
drivers
set is added
Signed-off-by: Chris Packham
---
drivers/rtc/Kconfig| 8 +
drivers/rtc/Makefile | 1 +
drivers/rtc/max313xx.c | 442 +
3 files changed, 451 insertions(+)
create mode 100644 drivers/rtc/max313xx.c
diff --git a/drivers/rtc/Kconfi
The find_closest() macro can be used to find an element in a sorted
array that is closest to an input value.
Signed-off-by: Chris Packham
---
include/linux/kernel.h | 24
1 file changed, 24 insertions(+)
diff --git a/include/linux/kernel.h b/include/linux/kernel.h
to keep things such that the U-Boot and Linux
versions can be compared and kept in sync.
[1] -
https://lore.kernel.org/all/20221108122254.1185-2-ibrahim.ti...@analog.com/
Chris Packham (2):
include: kernel.h: port find_closest() from Linux
drivers: rtc: add max313xx series rtc driver
drivers
On 16/02/23 16:36, Tom Rini wrote:
> In this platform, arch_misc_init doesn't perform any real function. The
> call to get_soc_type_rev has no lasting side effects.
>
> Cc: Chris Packham
> Signed-off-by: Tom Rini \
A hangover from the Marvell code I started with. T
Bx81LIFXCAT_defconfig | 2 +-
> configs/x530_defconfig | 2 +-
For these boards
Reviewed-by: Chris Packham
On Wed, 4 Jan 2023, 8:52 PM Pali Rohár, wrote:
> On Wednesday 04 January 2023 08:50:28 Pali Rohár wrote:
> > Hello!
> >
> > On Tuesday 03 January 2023 17:55:41 Tony Dinh wrote:
> > > Hi Pali,
> > >
> > > I'm building a new u-boot for the Thecus N2350 board (Armada 385
> > > dual-core 1Ghz 1GB
T/MTDPARTS_DEFAULT
For x530, SBx81LIFXCAT and SBx81LIFKW
Reviewed-by: Chris Packham
> cmd/mtdparts.c| 5 +
> configs/SBx81LIFKW_defconfig | 1 +
> configs/SBx81LIFXCAT_defconfig| 1 +
> configs/am335x_guardian_defconfig | 1 +
>
On Mon, Nov 7, 2022 at 9:45 PM Pali Rohár wrote:
>
> On Monday 07 November 2022 09:13:37 Stefan Roese wrote:
> > Hi Chris,
> >
> > On 07.11.22 09:11, Chris Packham wrote:
> > >
> > >
> > > On Mon, 7 Nov 2022, 7:23 PM Stefan Roese, > &g
On Mon, 7 Nov 2022, 7:23 PM Stefan Roese, wrote:
> Hi Chris,
>
> On 05.11.22 05:08, Chris Packham wrote:
> > On Sat, Nov 5, 2022 at 5:03 PM Chris Packham
> wrote:
> >>
> >> Hi Stefan,
> >>
> >> On Fri, Sep 16, 2022 at 2:23 AM Stefan Ro
780W
* LED interfaces per network port/POE
* LED interfaces (common) showing system status
* PTP TC mode Supported (Reserved M.2 connector to support BC mode)
Signed-off-by: Chris Packham
---
Changes in v6:
- Set CONFIG_DEFAULT_DEVICE_TREE and CONFIG_TEXT_BASE
Changes in v5:
- Remove unused
-off-by: Chris Packham
---
(no changes since v5)
Changes in v5:
- Minor fixup for checkpatch.pl complaint
Changes in v4:
- Remove unused mvebu_get_nand_clock() (will return in a later series)
- Remove unnecessary #ifdefs
- Misc style cleanups
- Replace CONFIG_MVEBU_SAR with simpler code
Unlike the other 64-bit mvebu SoCs the AlleyCat5 uses the older ehci
block from the 32-bit SoCs. Adapt the ehci-marvell.c driver to cope with
the fact that the ac5 does not have the mbus infrastructure the 32-bit
SoCs have and ensure USB_EHCI_IS_TDI is selected.
Signed-off-by: Chris Packham
This uses the same IP block as the Armada-8K SoCs.
Signed-off-by: Chris Packham
Reviewed-by: Stefan Roese
---
(no changes since v4)
Changes in v4:
- Collect r-by from Stefan
drivers/pinctrl/mvebu/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl
Add support for the AlleyCat5 SoC. This lacks the mbus from the other
users of the mvneta.c driver so a new compatible string is needed to
allow for a different window configuration.
Signed-off-by: Chris Packham
Reviewed-by: Stefan Roese
---
(no changes since v3)
Changes in v3:
- Remove
The 64-bit mvebu SoCs don't have a suitable timer driver so add a !ARM64
condition to the select.
Fixes: 7b530bb19e ("arm: mvebu: Use CONFIG_TIMER on all MVEBU & KIRKWOOD
platforms")
Signed-off-by: Chris Packham
---
(no changes since v1)
arch/arm/Kconfig | 2 +-
1 file change
from dts so the value passed by the DDR FW will be
used
Changes in v2:
- Use distro boot by default
- remove unnecessary SPI-NOR partitions
Chris Packham (6):
arm: mvebu: Don't use CONFIG_TIMER on ARM64
net: mvneta: Add support for AlleyCat5
usb: ehci: ehci-marvell: Support for marvell,ac5
On Sat, Nov 5, 2022 at 5:03 PM Chris Packham wrote:
>
> Hi Stefan,
>
> On Fri, Sep 16, 2022 at 2:23 AM Stefan Roese wrote:
> >
> > Now that the new timer support is available for these platforms, let's
> > select this IF for all these platforms. This way it's not
Hi Stefan,
On Fri, Sep 16, 2022 at 2:23 AM Stefan Roese wrote:
>
> Now that the new timer support is available for these platforms, let's
> select this IF for all these platforms. This way it's not necessary
> that each board changes it's config header.
>
> Signed-off-by: Stefan Roese
>
On Thu, Nov 3, 2022 at 9:29 AM Chris Packham wrote:
>
> On Thu, Nov 3, 2022 at 2:40 AM Stefan Roese wrote:
> >
> > Hi Chris,
> >
> > On 22.09.22 05:31, Chris Packham wrote:
> > > The RD-AC5X-32G16HVG6HLG-A0 development board main components and
> > &
On Thu, Nov 3, 2022 at 2:40 AM Stefan Roese wrote:
>
> Hi Chris,
>
> On 22.09.22 05:31, Chris Packham wrote:
> > The RD-AC5X-32G16HVG6HLG-A0 development board main components and
> > features include:
> > * Main 12V/54V power supply
> > * 270 Gbps throughpu
780W
* LED interfaces per network port/POE
* LED interfaces (common) showing system status
* PTP TC mode Supported (Reserved M.2 connector to support BC mode)
Signed-off-by: Chris Packham
---
Changes in v5:
- Remove unused bpard_{early,late}_init{,_r,_f} functions
- Remove CONFIG_PCI
-off-by: Chris Packham
---
Changes in v5:
- Minor fixup for checkpatch.pl complaint
Changes in v4:
- Remove unused mvebu_get_nand_clock() (will return in a later series)
- Remove unnecessary #ifdefs
- Misc style cleanups
- Replace CONFIG_MVEBU_SAR with simpler code implemented directly in
soc.c
This uses the same IP block as the Armada-8K SoCs.
Signed-off-by: Chris Packham
Reviewed-by: Stefan Roese
---
(no changes since v4)
Changes in v4:
- Collect r-by from Stefan
drivers/pinctrl/mvebu/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl
Unlike the other 64-bit mvebu SoCs the AlleyCat5 uses the older ehci
block from the 32-bit SoCs. Adapt the ehci-marvell.c driver to cope with
the fact that the ac5 does not have the mbus infrastructure the 32-bit
SoCs have and ensure USB_EHCI_IS_TDI is selected.
Signed-off-by: Chris Packham
Add support for the AlleyCat5 SoC. This lacks the mbus from the other
users of the mvneta.c driver so a new compatible string is needed to
allow for a different window configuration.
Signed-off-by: Chris Packham
Reviewed-by: Stefan Roese
---
(no changes since v3)
Changes in v3:
- Remove
:
- Use distro boot by default
- remove unnecessary SPI-NOR partitions
Chris Packham (5):
net: mvneta: Add support for AlleyCat5
usb: ehci: ehci-marvell: Support for marvell,ac5-ehci
pinctrl: mvebu: Add AlleyCat5 support
arm: mvebu: Support for 98DX25xx/98DX35xx SoC
arm: mvebu: Add RD
On Thu, Sep 22, 2022 at 5:10 PM Stefan Roese wrote:
>
> On 22.09.22 05:31, Chris Packham wrote:
> > The RD-AC5X-32G16HVG6HLG-A0 development board main components and
> > features include:
> > * Main 12V/54V power supply
> > * 270 Gbps throughput packet processo
On Thu, Sep 22, 2022 at 5:18 PM Stefan Roese wrote:
>
> On 22.09.22 05:31, Chris Packham wrote:
> > Unlike the other 64-bit mvebu SoCs the AlleyCat5 uses the older ehci
> > block from the 32-bit SoCs. Adapt the ehci-marvell.c driver to cope with
> > the fact that the ac
780W
* LED interfaces per network port/POE
* LED interfaces (common) showing system status
* PTP TC mode Supported (Reserved M.2 connector to support BC mode)
Signed-off-by: Chris Packham
---
Changes in v4:
- Move CONFIG_DISPLAY_BOARDINFO_LATE and CONFIG_ENV_OVERWRITE to
the defconfig
-off-by: Chris Packham
---
Changes in v4:
- Remove unused mvebu_get_nand_clock() (will return in a later series)
- Remove unnecessary #ifdefs
- Misc style cleanups
- Replace CONFIG_MVEBU_SAR with simpler code implemented directly in
soc.c based around get_sar_freq which the 32-bit platforms
This uses the same IP block as the Armada-8K SoCs.
Signed-off-by: Chris Packham
Reviewed-by: Stefan Roese
---
Changes in v4:
- Collect r-by from Stefan
drivers/pinctrl/mvebu/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers
Unlike the other 64-bit mvebu SoCs the AlleyCat5 uses the older ehci
block from the 32-bit SoCs. Adapt the ehci-marvell.c driver to cope with
the fact that the ac5 does not have the mbus infrastructure the 32-bit
SoCs have and ensure USB_EHCI_IS_TDI is selected.
Signed-off-by: Chris Packham
Add support for the AlleyCat5 SoC. This lacks the mbus from the other
users of the mvneta.c driver so a new compatible string is needed to
allow for a different window configuration.
Signed-off-by: Chris Packham
Reviewed-by: Stefan Roese
---
(no changes since v3)
Changes in v3:
- Remove
unnecessary SPI-NOR partitions
Chris Packham (5):
net: mvneta: Add support for AlleyCat5
usb: ehci: ehci-marvell: Support for marvell,ac5-ehci
pinctrl: mvebu: Add AlleyCat5 support
arm: mvebu: Support for 98DX25xx/98DX35xx SoC
arm: mvebu: Add RD-AC5X board
arch/arm/dts/Makefile
On Thu, Sep 22, 2022 at 9:55 AM Pali Rohár wrote:
>
> On Wednesday 21 September 2022 16:59:41 Chris Packham wrote:
> > diff --git a/arch/arm/dts/ac5-98dx35xx-rd.dts
> > b/arch/arm/dts/ac5-98dx35xx-rd.dts
> ...
> > +/ {
> > + model = "Marvell RD-AC5X Boar
On Thu, Sep 22, 2022 at 9:40 AM Pali Rohár wrote:
>
> On Thursday 22 September 2022 09:25:37 Chris Packham wrote:
> > On Wed, Sep 21, 2022 at 5:58 PM Stefan Roese wrote:
> > >
> > > On 21.09.22 06:59, Chris Packham wrote:
> > > > Add support for the Alle
On Wed, Sep 21, 2022 at 5:58 PM Stefan Roese wrote:
>
> On 21.09.22 06:59, Chris Packham wrote:
> > Add support for the Allecat5/Alleycat5X SoC. These are L3 switches with
> > an integrated CPU (referred to as the CnM block in Marvell's
> > documentation). These have dual
On Wed, Sep 21, 2022 at 5:58 PM Stefan Roese wrote:
>
> On 21.09.22 06:59, Chris Packham wrote:
> > Add support for the Allecat5/Alleycat5X SoC. These are L3 switches with
> > an integrated CPU (referred to as the CnM block in Marvell's
> > documentation). These have dual
780W
* LED interfaces per network port/POE
* LED interfaces (common) showing system status
* PTP TC mode Supported (Reserved M.2 connector to support BC mode)
Signed-off-by: Chris Packham
---
Changes in v3:
- Remove MMC and UBIFS distroboot options (MMC driver is not currently
functional, NAND
-off-by: Chris Packham
---
Changes in v3:
- Remove unnecessary dma-ranges property from ethernet nodes (mvneta now
correctly parses the property from the parent node).
- Keep soc_print_clock_info and soc_print_device_info local to
alleycat5.
arch/arm/dts/ac5-98dx25xx.dtsi | 290
Add a new UCLASS_SAR, the generic SAR code and an Alleycat5 driver. This
has been adapted from the Marvell SDK but only the AC5 driver has been
brought through (other drivers exist for the ap806, ap807 and cp110 IP
blocks).
Signed-off-by: Chris Packham
---
Changes in v3:
- None. Note some
This uses the same IP block as the Armada-8K SoCs.
Signed-off-by: Chris Packham
---
(no changes since v1)
drivers/pinctrl/mvebu/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig
index 574fb4dfb0
Unlike the other 64-bit mvebu SoCs the AlleyCat5 uses the older ehci
block from the 32-bit SoCs. Adapt the ehci-marvell.c driver to cope with
the fact that the ac5 does not have the mbus infrastructure the 32-bit
SoCs have and ensure USB_EHCI_IS_TDI is selected.
Signed-off-by: Chris Packham
Add support for the AlleyCat5 SoC. This lacks the mbus from the other
users of the mvneta.c driver so a new compatible string is needed to
allow for a different window configuration.
Signed-off-by: Chris Packham
Reviewed-by: Stefan Roese
---
Changes in v3:
- Remove unnecessary changes to RX
- remove unnecessary SPI-NOR partitions
Chris Packham (6):
net: mvneta: Add support for AlleyCat5
usb: ehci: ehci-marvell: Support for marvell,ac5-ehci
pinctrl: mvebu: Add AlleyCat5 support
misc: mvebu: Add sample at reset driver
arm: mvebu: Support for 98DX25xx/98DX35xx SoC
arm: mvebu: Add
On Tue, Sep 20, 2022 at 9:22 PM Pali Rohár wrote:
>
> On Tuesday 20 September 2022 20:31:52 Chris Packham wrote:
> > Add support for the Allecat5/Alleycat5X SoC. These are L3 switches with
> > an integrated CPU (referred to as the CnM block in Marvell's
> > documentation).
On Tue, Sep 20, 2022 at 10:48 PM Pali Rohár wrote:
>
> On Tuesday 20 September 2022 20:31:48 Chris Packham wrote:
> > diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c
> > index d2c42c4396..07919d6d35 100644
> > --- a/drivers/net/mvneta.c
> > +++ b/drivers/n
On Tue, Sep 20, 2022 at 9:17 PM Stefan Roese wrote:
>
> On 20.09.22 10:31, Chris Packham wrote:
> > Add support for the AlleyCat5 SoC. This lacks the mbus from the other
> > users of the mvneta.c driver so a new compatible string is needed to
> > allow for a differ
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