From: Dinesh Maniyam
This patch is to enable SPL_SYS_NAND_SELF_INIT for Cadence NAND SPL.
Signed-off-by: Dinesh Maniyam
---
drivers/mtd/nand/raw/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 90f8f4b688..32444c2468
From: Dinesh Maniyam
This patch is to remove SYS_NAND_BLOCK_SIZE dependency for cadence NAND.
This config is not needed as the driver will send command read
parameter page to identify the NAND block size during initialization.
Signed-off-by: Dinesh Maniyam
---
drivers/mtd/nand/raw/Kconfig | 2
From: Dinesh Maniyam
This patch is to enable the Kconfig and Makefile for the Cadence-Nand
SPL support in agilex5 family device.
Signed-off-by: Dinesh Maniyam
---
drivers/mtd/nand/raw/Kconfig | 7 +++
drivers/mtd/nand/raw/Makefile | 1 +
2 files changed, 8 insertions(+)
diff --git a
From: Dinesh Maniyam
This patch is add support for spl nand to load binary image from NAND
to RAM.
Signed-off-by: Dinesh Maniyam
---
drivers/mtd/nand/raw/cadence_spl.c | 96 ++
1 file changed, 96 insertions(+)
create mode 100644 drivers/mtd/nand/raw/cadence_spl.c
From: Dinesh Maniyam
This patch is to leverage linux code to support hardware ECC interface
in verify nand bad block.
Signed-off-by: Dinesh Maniyam
---
drivers/mtd/nand/raw/nand_base.c | 71 +---
include/linux/mtd/rawnand.h | 13 ++
2 files changed, 60
From: Dinesh Maniyam
This patch is to enable configs for nand boot.
Signed-off-by: Dinesh Maniyam
---
configs/socfpga_agilex5_nand2_defconfig | 169
1 file changed, 169 insertions(+)
create mode 100644 configs/socfpga_agilex5_nand2_defconfig
diff --git a/configs
From: Dinesh Maniyam
This patch is to enable the Kconfig and Makefile for the
Cadence NAND driver for the agilex5 family device.
Signed-off-by: Dinesh Maniyam
---
drivers/mtd/nand/raw/Kconfig | 9 +
drivers/mtd/nand/raw/Makefile | 1 +
2 files changed, 10 insertions(+)
diff --git a
From: Dinesh Maniyam
The patch is to enable nand to use bounce buffer. In bounce buffer,
read/write buf will use cadence->buf which has been allocated
using malloc. This will align the memory and avoid memory to be
allocated in different addresses.
Signed-off-by: Dinesh Maniyam
---
driv
From: Dinesh Maniyam
The patch is to poll for thread complete status to ensure the
descriptor processing is complete. If complete then can ensure
controller already update the descriptor status.
Signed-off-by: Dinesh Maniyam
---
drivers/mtd/nand/raw/cadence_nand.c | 9 +
1 file
From: Dinesh Maniyam
The patch is to ensure ddr memory is updated with the data from dcache,
This would help to ensure cdma always reading the latest dma descriptor
in ddr memory.
Signed-off-by: Dinesh Maniyam
---
drivers/mtd/nand/raw/cadence_nand.c | 4
1 file changed, 4 insertions
From: Dinesh Maniyam
This patch is to support NAND_CMD_SET_FEATURES & NAND_CMD_GET_FEATURES.
These commands is one of the basic commands of NAND. Params get from
these commands will be used to set timing mode of NAND data interface.
Signed-off-by: Dinesh Maniyam
---
drivers/mtd/nand
From: Dinesh Maniyam
The patch is to support nand reset command for Cadence Nand Driver.
Signed-off-by: Dinesh Maniyam
---
drivers/mtd/nand/raw/cadence_nand.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/mtd/nand/raw/cadence_nand.c
b/drivers/mtd
From: Dinesh Maniyam
This patch is to add support for reading param page of NAND device.
These paramaters are unique and used for identification purpose.
Signed-off-by: Dinesh Maniyam
---
drivers/mtd/nand/raw/cadence_nand.c | 30 +
1 file changed, 30 insertions
From: Dinesh Maniyam
This patch will add support for read status command
in Cadence NAND driver. This status bit is important to check
whether the flash is write-protected.
Signed-off-by: Dinesh Maniyam
---
drivers/mtd/nand/raw/cadence_nand.c | 46 -
include
From: Dinesh Maniyam
This patch will add support for readid command in Cadence NAND driver.
The id is unique and used for flash identification.
Signed-off-by: Dinesh Maniyam
---
drivers/mtd/nand/raw/cadence_nand.c | 32 -
1 file changed, 31 insertions(+), 1
From: Dinesh Maniyam
This patch is to enable driver for Cadence NAND for the family
device agilex5. This driver is leveraged from linux.
Signed-off-by: Dinesh Maniyam
---
drivers/mtd/nand/raw/cadence_nand.c | 2210 +++
include/cadence-nand.h | 526
From: Dinesh Maniyam
The patch is to extend support read and write 64-bits of buffer.
This is required for Cadence NAND Driver to
read/write ONFI parameter page. The parameter page is mapped to 64-bit.
With only read/write 32 bits of buffer,there is an issue of overwriting
last 4 bits of buffer
From: Dinesh Maniyam
This patch is to enable cdns-nand dts setting for the socfpga_agilex5
family device.
Signed-off-by: Dinesh Maniyam
---
arch/arm/dts/socfpga_agilex5.dtsi | 14 ++
.../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 28 +++
2 files changed
From: Dinesh Maniyam
The Cadence NAND is a configurable mtd raw block which
supports multiple options for chipsets, clocking and reset structure, and
feature list.
Signed-off-by: Dinesh Maniyam
---
.../mtd/cadence,nand.yaml | 98 +++
1 file changed, 98
From: Dinesh Maniyam
This patchset add Cadence NAND driver support for
Intel Agilex5 devices.
The NAND driver is leveraged from the cadence-nand-controller.c
from Linux. U-Boot will support read, write and erase NAND with
Cadence driver. The driver further enhanced in U-Boot to support
NAND
From: Dinesh Maniyam
The reserved space is extended to 32MB in Linux kernel because
additional space is needed for authorization execution of JIC/RBF file.
U-Boot required to align with Linux.
Signed-off-by: Dinesh Maniyam
---
arch/arm/dts/socfpga_agilex.dtsi | 4 ++--
1 file changed, 2
From: Dinesh Maniyam
MEMCLKMGR_EXTCNTRST_C0CNTRST register defined as BIT[0] in documentation
but it is wrongly defined as BIT[7] in u-boot code. This register is used
to hold associated pingpong counter in reset
while PLL and 5:1 mux configuration is changed.
Signed-off-by: Dinesh Maniyam
From: Dinesh Maniyam
This patch is to add SPI clock support for stratix10. Get clock rate
function always returning 0 because the DW-SPI driver get the rate
from clock node in dts but Stratix10 does not support device tree
clock node.To overcome this spi will get the clock_rate directly
from spi
From: Dinesh Maniyam
Convert the constant integer to 'phys_size_t' to avoid overflow
when calculating the SDRAM size.
Signed-off-by: Dinesh Maniyam
---
v3->v2
- copyright year updated and alignment updated.
v2->v1
- add space in title
---
drivers/ddr/altera/sdram_soc64.c |
From: Dinesh Maniyam
There is hardware bug in NCORE CCU IP and it is causing an issue in the
coherent directory tracking of outstanding cache lines.
The workaround is disabling snoop filter.
Signed-off-by: Dinesh Maniyam
---
drivers/cache/cache-ncore.c | 6 +++---
1 file changed, 3 insertions
From: Dinesh Maniyam
Override __udelay() as 'always inlined' function so that PSCI code
run in '__secure' section can call this delay function as well.
Signed-off-by: Chee Hong Ang
Signed-off-by: Dinesh Maniyam
---
arch/arm/mach-socfpga/timer_s10.c | 35 ++
From: Dinesh Maniyam
The freeze controller is required for FPGA partial reconfig.
This node is disable on default.
Enable this node via u-boot fdt command when needed.
Signed-off-by: Yau Wai Gan
Signed-off-by: Dinesh Maniyam
---
arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 11
From: Dinesh Maniyam
The freeze controller is required for FPGA partial reconfig.
This node is disable on default.
Enable this node via u-boot fdt command when needed.
Signed-off-by: Yau Wai Gan
Signed-off-by: Dinesh Maniyam
---
arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 11
From: Dinesh Maniyam
Status busy means transfer is accepted but SDM does not have more freed
buffer. It is not an error. Continue process the data if receive OK or
BUSY status.
Signed-off-by: Dinesh Maniyam
---
v2->v3
-Copyright year updated and alignment adjusted.
---
drivers/f
From: Dinesh Maniyam
Status busy means transfer is accepted but SDM does not have more freed
buffer. It is not an error. Continue process the data if receive OK or
BUSY status.
Signed-off-by: Ley Foon Tan
Signed-off-by: Dinesh Maniyam
---
v1 -> v2
- change to "OK or Busy status i
From: Dinesh Maniyam
Prior U-Boot pass control to Linux, U-Boot will send a mailbox command
"HPS_STAGE_NOTIFY" to notify Secure Device Manager (SDM) on HPS SW
transition.
Signed-off-by: Dinesh Maniyam
---
v1->v2
Add space in title
---
arch/arm/mach-socfpga/misc_soc64.c | 5
From: Dinesh Maniyam
Convert the constant integer to 'phys_size_t' to avoid overflow
when calculating the SDRAM size.
Signed-off-by: Dinesh Maniyam
---
v1->v2
- Add space in title
---
drivers/ddr/altera/sdram_soc64.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
From: Dinesh Maniyam
Prior SPL pass control to U-Boot, SPL will send a mailbox command
"HPS_STAGE_NOTIFY" to notify Secure Device Manager (SDM) on HPS SW
transition. The purpose is for debug as user can query
SDM on HPS error details when HPS enters a warm reset due
to error such a
From: Dinesh Maniyam
Add a new mailbox command "HPS_STAGE_NOTIFY" to notify Secure Device
Manager (SDM) on the stage of HPS code execution. In general, there
are three main code execution stages: First Stage Boot Loader (FSBL)
which is U-Boot SPL, Second Stage Boot Loader (SSBL) which
From: Dinesh Maniyam
Prior U-Boot pass control to Linux, U-Boot will send a mailbox command
"HPS_STAGE_NOTIFY" to notify Secure Device Manager (SDM) on HPS SW
transition.
Signed-off-by: Chin Liang See
Signed-off-by: Dinesh Maniyam
---
arch/arm/mach-socfpga/misc_soc64.c | 5 +++
From: Dinesh Maniyam
Convert the constant integer to 'phys_size_t' to avoid overflow
when calculating the SDRAM size.
Signed-off-by: Chee Hong Ang
Signed-off-by: Dinesh Maniyam
---
drivers/ddr/altera/sdram_soc64.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
From: Dinesh Maniyam
Status busy means transfer is accepted but SDM does not have more freed
buffer. It is not an error. Continue process the data if receive OK and
BUSY status.
Signed-off-by: Ley Foon Tan
Signed-off-by: Dinesh Maniyam
---
drivers/fpga/intel_sdm_mb.c | 3 ++-
1 file changed
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