On Mon, 6 Jun 2022 23:00:08 +0200 (CEST)
Mark Kettenis wrote:
Hi Mark,
> > From: Andre Przywara
> > Date: Mon, 9 May 2022 17:08:49 +0100
> >
> > The AArch64 TCR_ELx register is a 64-bit register, and many newer
> > architecture features use bits in the upper half. So far U-Boot was
> > igoran
> From: Andre Przywara
> Date: Mon, 9 May 2022 17:08:49 +0100
>
> The AArch64 TCR_ELx register is a 64-bit register, and many newer
> architecture features use bits in the upper half. So far U-Boot was
> igorant of those bits, trying to leave them alone.
> However, in an effort to set bit 31 to
On Mon, May 09, 2022 at 05:08:49PM +0100, Andre Przywara wrote:
> The AArch64 TCR_ELx register is a 64-bit register, and many newer
> architecture features use bits in the upper half. So far U-Boot was
> igorant of those bits, trying to leave them alone.
> However, in an effort to set bit 31 to 1,
On Tue, May 10, 2022 at 12:56 AM Peng Fan wrote:
>
> > Subject: [PATCH] armv8: Fix TCR 64-bit writes
> >
> > The AArch64 TCR_ELx register is a 64-bit register, and many newer
> > architecture
> > features use bits in the upper half. So far U-Boot was igorant
> Subject: [PATCH] armv8: Fix TCR 64-bit writes
>
> The AArch64 TCR_ELx register is a 64-bit register, and many newer architecture
> features use bits in the upper half. So far U-Boot was igorant of those bits,
> trying to leave them alone.
> However, in an effort to set bit
The AArch64 TCR_ELx register is a 64-bit register, and many newer
architecture features use bits in the upper half. So far U-Boot was
igorant of those bits, trying to leave them alone.
However, in an effort to set bit 31 to 1, it failed doing so, because
the compiler sign-extended "1 << 31", so tha
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