On Thu, 1 Feb 2024 14:30:14 +0100
Ludwig Kormann wrote:
Hi,
> This option can be used to modify the initial SPL
> CPU clock frequency.
>
> This follows an earlier discussion regarding A20
> CPUs dying after reboot in SPL initialization due to
> incompatible CPU clock frequency and core
On Thu, Feb 01, 2024 at 02:30:14PM +0100, Ludwig Kormann wrote:
> This option can be used to modify the initial SPL
> CPU clock frequency.
>
> This follows an earlier discussion regarding A20
> CPUs dying after reboot in SPL initialization due to
> incompatible CPU clock frequency and core
This option can be used to modify the initial SPL
CPU clock frequency.
This follows an earlier discussion regarding A20
CPUs dying after reboot in SPL initialization due to
incompatible CPU clock frequency and core voltage. [1]
First attempt was to update PLL1_CFG_DEFAULT to a fixed
lower
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