On 2023/1/20 2:30, Conor Dooley wrote:
> Hey Seán, David,
>
> On Thu, Jan 19, 2023 at 01:26:52AM -0500, Sean Anderson wrote:
>> On 1/19/23 01:18, David Abdurachmanov wrote:
>> > On Wed, Jan 18, 2023 at 10:19 AM Yanhong Wang
>> > wrote:
>
>> > > + U74_4: cpu@4 {
>> > > +
On 1/19/23 14:25, Conor Dooley wrote:
On Thu, Jan 19, 2023 at 02:16:51PM -0500, Sean Anderson wrote:
On 1/19/23 13:30, Conor Dooley wrote:
Hey Seán, David,
On Thu, Jan 19, 2023 at 01:26:52AM -0500, Sean Anderson wrote:
On 1/19/23 01:18, David Abdurachmanov wrote:
On Wed, Jan 18, 2023 at 10:1
On Thu, Jan 19, 2023 at 02:16:51PM -0500, Sean Anderson wrote:
> On 1/19/23 13:30, Conor Dooley wrote:
> > Hey Seán, David,
> >
> > On Thu, Jan 19, 2023 at 01:26:52AM -0500, Sean Anderson wrote:
> >> On 1/19/23 01:18, David Abdurachmanov wrote:
> >> > On Wed, Jan 18, 2023 at 10:19 AM Yanhong Wang
On 1/19/23 13:30, Conor Dooley wrote:
> Hey Seán, David,
>
> On Thu, Jan 19, 2023 at 01:26:52AM -0500, Sean Anderson wrote:
>> On 1/19/23 01:18, David Abdurachmanov wrote:
>> > On Wed, Jan 18, 2023 at 10:19 AM Yanhong Wang
>> > wrote:
>
>> > > + U74_4: cpu@4 {
>> > > +
Hey Seán, David,
On Thu, Jan 19, 2023 at 01:26:52AM -0500, Sean Anderson wrote:
> On 1/19/23 01:18, David Abdurachmanov wrote:
> > On Wed, Jan 18, 2023 at 10:19 AM Yanhong Wang
> > wrote:
> > > + U74_4: cpu@4 {
> > > + compatible = "sifive,u74-mc", "riscv";
>
On 1/19/23 01:18, David Abdurachmanov wrote:
On Wed, Jan 18, 2023 at 10:19 AM Yanhong Wang
wrote:
Add initial device tree for the JH7110 RISC-V SoC.
Signed-off-by: Yanhong Wang
---
arch/riscv/dts/jh7110.dtsi | 497 +
1 file changed, 497 insertions(+)
On Wed, Jan 18, 2023 at 10:19 AM Yanhong Wang
wrote:
>
> Add initial device tree for the JH7110 RISC-V SoC.
>
> Signed-off-by: Yanhong Wang
> ---
> arch/riscv/dts/jh7110.dtsi | 497 +
> 1 file changed, 497 insertions(+)
> create mode 100644 arch/riscv/dts/jh7
Add initial device tree for the JH7110 RISC-V SoC.
Signed-off-by: Yanhong Wang
---
arch/riscv/dts/jh7110.dtsi | 497 +
1 file changed, 497 insertions(+)
create mode 100644 arch/riscv/dts/jh7110.dtsi
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh
8 matches
Mail list logo