Re: [PATCH v2 2/2] arm: stm32mp: activate data cache on DDR in SPL

On 4/9/20 8:10 PM, Patrick DELAUNAY wrote: > Dear Marek, > >> From: Marek Vasut >> Sent: vendredi 3 avril 2020 23:33 >> >> On 4/3/20 11:25 AM, Patrick Delaunay wrote: >>> Activate cache on DDR to improves the accesses to DDR used by SPL: >>> - CONFIG_SPL_BSS_START_ADDR >>> - CONFIG_SYS_SPL_MALLOC

RE: [PATCH v2 2/2] arm: stm32mp: activate data cache on DDR in SPL

Dear Marek, > From: Marek Vasut > Sent: vendredi 3 avril 2020 23:33 > > On 4/3/20 11:25 AM, Patrick Delaunay wrote: > > Activate cache on DDR to improves the accesses to DDR used by SPL: > > - CONFIG_SPL_BSS_START_ADDR > > - CONFIG_SYS_SPL_MALLOC_START > > > > Cache is configured only when DDR i

Re: [PATCH v2 2/2] arm: stm32mp: activate data cache on DDR in SPL

On 4/3/20 11:25 AM, Patrick Delaunay wrote: > Activate cache on DDR to improves the accesses to DDR used by SPL: > - CONFIG_SPL_BSS_START_ADDR > - CONFIG_SYS_SPL_MALLOC_START > > Cache is configured only when DDR is fully initialized, > to avoid speculative access and issue in get_ram_size(). > Da

[PATCH v2 2/2] arm: stm32mp: activate data cache on DDR in SPL

Activate cache on DDR to improves the accesses to DDR used by SPL: - CONFIG_SPL_BSS_START_ADDR - CONFIG_SYS_SPL_MALLOC_START Cache is configured only when DDR is fully initialized, to avoid speculative access and issue in get_ram_size(). Data cache is deactivated at the end of SPL, to flush the da