[PATCH v2 5/5] imx8mn-var-som: adjust PHY reset gpios according to hardware configuration

2023-07-12 Thread sbabic
> From: Hugo Villeneuve > For SOM with the EC configuration, the ethernet PHY is located on the > SOM itself, and connected to the CPU ethernet controller. It has a > reset line controlled via GPIO1_IO9. In this configuration, the PHY > located on the carrier board is not connected to anything

Re: [RESEND PATCH v2 5/5] imx8mn-var-som: adjust PHY reset gpios according to hardware configuration

2023-07-12 Thread Stefano Babic
On 12.07.23 15:31, Hugo Villeneuve wrote: On Wed, 12 Jul 2023 12:42:26 +0200 Stefano Babic wrote: Hi Hugo, On 11.07.23 17:45, Hugo Villeneuve wrote: From: Hugo Villeneuve For SOM with the EC configuration, the ethernet PHY is located on the SOM itself, and connected to the CPU ethernet

Re: [RESEND PATCH v2 5/5] imx8mn-var-som: adjust PHY reset gpios according to hardware configuration

2023-07-12 Thread Hugo Villeneuve
On Wed, 12 Jul 2023 12:42:26 +0200 Stefano Babic wrote: > Hi Hugo, > > On 11.07.23 17:45, Hugo Villeneuve wrote: > > From: Hugo Villeneuve > > > > For SOM with the EC configuration, the ethernet PHY is located on the > > SOM itself, and connected to the CPU ethernet controller. It has a > >

Re: [RESEND PATCH v2 5/5] imx8mn-var-som: adjust PHY reset gpios according to hardware configuration

2023-07-12 Thread Stefano Babic
Hi Hugo, On 11.07.23 17:45, Hugo Villeneuve wrote: From: Hugo Villeneuve For SOM with the EC configuration, the ethernet PHY is located on the SOM itself, and connected to the CPU ethernet controller. It has a reset line controlled via GPIO1_IO9. In this configuration, the PHY located on the

[PATCH v2 5/5] imx8mn-var-som: adjust PHY reset gpios according to hardware configuration

2023-07-12 Thread sbabic
> From: Hugo Villeneuve > For SOM with the EC configuration, the ethernet PHY is located on the > SOM itself, and connected to the CPU ethernet controller. It has a > reset line controlled via GPIO1_IO9. In this configuration, the PHY > located on the carrier board is not connected to anything

[RESEND PATCH v2 5/5] imx8mn-var-som: adjust PHY reset gpios according to hardware configuration

2023-07-11 Thread Hugo Villeneuve
From: Hugo Villeneuve For SOM with the EC configuration, the ethernet PHY is located on the SOM itself, and connected to the CPU ethernet controller. It has a reset line controlled via GPIO1_IO9. In this configuration, the PHY located on the carrier board is not connected to anything and is

[PATCH v2 5/5] imx8mn-var-som: adjust PHY reset gpios according to hardware configuration

2023-05-25 Thread Hugo Villeneuve
From: Hugo Villeneuve For SOM with the EC configuration, the ethernet PHY is located on the SOM itself, and connected to the CPU ethernet controller. It has a reset line controlled via GPIO1_IO9. In this configuration, the PHY located on the carrier board is not connected to anything and is