> From: Hugo Villeneuve
> For SOM with the EC configuration, the ethernet PHY is located on the
> SOM itself, and connected to the CPU ethernet controller. It has a
> reset line controlled via GPIO1_IO9. In this configuration, the PHY
> located on the carrier board is not connected to anything
On 12.07.23 15:31, Hugo Villeneuve wrote:
On Wed, 12 Jul 2023 12:42:26 +0200
Stefano Babic wrote:
Hi Hugo,
On 11.07.23 17:45, Hugo Villeneuve wrote:
From: Hugo Villeneuve
For SOM with the EC configuration, the ethernet PHY is located on the
SOM itself, and connected to the CPU ethernet
On Wed, 12 Jul 2023 12:42:26 +0200
Stefano Babic wrote:
> Hi Hugo,
>
> On 11.07.23 17:45, Hugo Villeneuve wrote:
> > From: Hugo Villeneuve
> >
> > For SOM with the EC configuration, the ethernet PHY is located on the
> > SOM itself, and connected to the CPU ethernet controller. It has a
> >
Hi Hugo,
On 11.07.23 17:45, Hugo Villeneuve wrote:
From: Hugo Villeneuve
For SOM with the EC configuration, the ethernet PHY is located on the
SOM itself, and connected to the CPU ethernet controller. It has a
reset line controlled via GPIO1_IO9. In this configuration, the PHY
located on the
> From: Hugo Villeneuve
> For SOM with the EC configuration, the ethernet PHY is located on the
> SOM itself, and connected to the CPU ethernet controller. It has a
> reset line controlled via GPIO1_IO9. In this configuration, the PHY
> located on the carrier board is not connected to anything
From: Hugo Villeneuve
For SOM with the EC configuration, the ethernet PHY is located on the
SOM itself, and connected to the CPU ethernet controller. It has a
reset line controlled via GPIO1_IO9. In this configuration, the PHY
located on the carrier board is not connected to anything and is
From: Hugo Villeneuve
For SOM with the EC configuration, the ethernet PHY is located on the
SOM itself, and connected to the CPU ethernet controller. It has a
reset line controlled via GPIO1_IO9. In this configuration, the PHY
located on the carrier board is not connected to anything and is
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