Re: [PATCH v3 1/4] riscv: dts: Update memory configuration

alentina.fernandezala...@microchip.com; nagasuresh.re...@microchip.com; > Padmarao Begari > Subject: [PATCH v3 1/4] riscv: dts: Update memory configuration > > In the v2022.10 Icicle reference design, the seg registers have been changed, > resulting in a required change to the memory map. >

[PATCH v3 1/4] riscv: dts: Update memory configuration

In the v2022.10 Icicle reference design, the seg registers have been changed, resulting in a required change to the memory map. A small 4MB reservation is made at the end of 32-bit DDR to provide some memory for the HSS to use, so that it can cache its payload between reboots of a specific context.