On 05/21/2013 02:38 PM, Marek Vasut wrote:
Dear Sergey Yanovich,
Dear Marek Vasut,
On Tue, 2013-05-21 at 22:07 +0200, Marek Vasut wrote:
The OneNAND has 1kbyte limit on code it will directly address when
booting from it, you can't even make generate the MMU table there.
Do you mean there
Dear Marek Vasut,
On Tue, 2013-05-21 at 23:38 +0200, Marek Vasut wrote:
Do you mean there is no space left inside that 1K for
lock_cache_for_stack()?
How would you do that ? You need MMU enabled to lock lines IIRC.
I see I don't know enough to continue the discussion, yet.
Concerning the
Dear Sergey Yanovich,
Dear Marek Vasut,
On Tue, 2013-05-21 at 23:38 +0200, Marek Vasut wrote:
Do you mean there is no space left inside that 1K for
lock_cache_for_stack()?
How would you do that ? You need MMU enabled to lock lines IIRC.
I see I don't know enough to continue the
Dear Marek Vasut,
On Wed, 2013-05-22 at 15:04 +0200, Marek Vasut wrote:
Concerning the patch in question, is it possible to allow cache for ram
on PXA270 somehow before we have a final solution?
I dont mind discussing this further and even using DCache for stack in
board_init_f(), but we
Dear Sergey Yanovich,
Dear Marek Vasut,
On Wed, 2013-05-22 at 15:04 +0200, Marek Vasut wrote:
Concerning the patch in question, is it possible to allow cache for ram
on PXA270 somehow before we have a final solution?
I dont mind discussing this further and even using DCache for
Dear Sergey Yanovich,
2.2.5.2 of Marvell PXA27x Processor Family Developers Manual says:
The PXA27x processor cache configuration is identical to that of
the PXA255 processor.
As a result, it is perfectly legitimate to use PXA25X
'lock_cache_for_stack' on PXA27X as well.
Signed-off-by:
Dear Marek Vasut,
On Tue, 2013-05-21 at 12:39 +0200, Marek Vasut wrote:
2.2.5.2 of Marvell PXA27x Processor Family Developers Manual says:
The PXA27x processor cache configuration is identical to that of
the PXA255 processor.
As a result, it is perfectly legitimate to use PXA25X
Dear Sergey Yanovich,
Dear Marek Vasut,
On Tue, 2013-05-21 at 12:39 +0200, Marek Vasut wrote:
2.2.5.2 of Marvell PXA27x Processor Family Developers Manual says:
The PXA27x processor cache configuration is identical to that of
the PXA255 processor.
As a result, it is perfectly
Dear Marek Vasut,
On Tue, 2013-05-21 at 12:54 +0200, Marek Vasut wrote:
SRAM is just the in-CPU bit of fast RAM. What do you mean by battery-backup
?
Yes, you are right. It is 'for high speed code or data storage preserved
during low-power states' using a quote from PXA270 EMTS (top of page
Dear Sergey Yanovich,
Dear Marek Vasut,
On Tue, 2013-05-21 at 12:54 +0200, Marek Vasut wrote:
SRAM is just the in-CPU bit of fast RAM. What do you mean by
battery-backup ?
Yes, you are right. It is 'for high speed code or data storage preserved
during low-power states' using a quote
Dear Marek Vasut,
On Tue, 2013-05-21 at 13:38 +0200, Marek Vasut wrote:
Yes, it's just an in-CPU RAM.
Well, it is not 'just' RAM. It preserves its state during deep sleep and
power off modes.
Anyway, SRAM preserves its state when power is off. Poweroff time could
be in years with a backup
Dear Sergey Yanovich,
Dear Marek Vasut,
On Tue, 2013-05-21 at 13:38 +0200, Marek Vasut wrote:
Yes, it's just an in-CPU RAM.
Well, it is not 'just' RAM. It preserves its state during deep sleep and
power off modes.
So does RAM during sleep state ;-)
Anyway, SRAM preserves its state
On Tue, 2013-05-21 at 17:00 +0200, Marek Vasut wrote:
Yes, the patch as it is will only affects relocation speed and preserve
SRAM from corruption.
Now this is the right (convincing) argument! What kind of corruption ? When
does
it occur ?
The whole 256 kB of SRAM could be used for
Dear Sergey Yanovich,
On Tue, 2013-05-21 at 17:00 +0200, Marek Vasut wrote:
Yes, the patch as it is will only affects relocation speed and preserve
SRAM from corruption.
Now this is the right (convincing) argument! What kind of corruption ?
When does it occur ?
The whole 256 kB
Dear Marek Vasut,
On Tue, 2013-05-21 at 21:02 +0200, Marek Vasut wrote:
The whole 256 kB of SRAM could be used for persistent storage with the
patch. Without it, part of SRAM should be dedicated for U-Boot stack or
be overwritten on boot.
This won't hold on any PXA that uses SPL, like
Dear Sergey Yanovich,
Dear Marek Vasut,
On Tue, 2013-05-21 at 21:02 +0200, Marek Vasut wrote:
The whole 256 kB of SRAM could be used for persistent storage with the
patch. Without it, part of SRAM should be dedicated for U-Boot stack or
be overwritten on boot.
This won't hold on
Dear Marek Vasut,
On Tue, 2013-05-21 at 21:24 +0200, Marek Vasut wrote:
I'd love to have a uniform way to do this cache thing, really ...
Requoting the spec 'The PXA27x processor cache configuration is
identical to that of the PXA255 processor'. It looks safe to configure
all PXA2XX chipsets
Dear Sergey Yanovich,
Dear Marek Vasut,
On Tue, 2013-05-21 at 21:24 +0200, Marek Vasut wrote:
I'd love to have a uniform way to do this cache thing, really ...
Requoting the spec 'The PXA27x processor cache configuration is
identical to that of the PXA255 processor'. It looks safe to
Dear Marek Vasut,
On Tue, 2013-05-21 at 22:07 +0200, Marek Vasut wrote:
The OneNAND has 1kbyte limit on code it will directly address when booting
from
it, you can't even make generate the MMU table there.
Do you mean there is no space left inside that 1K for
lock_cache_for_stack()?
I
Dear Sergey Yanovich,
Dear Marek Vasut,
On Tue, 2013-05-21 at 22:07 +0200, Marek Vasut wrote:
The OneNAND has 1kbyte limit on code it will directly address when
booting from it, you can't even make generate the MMU table there.
Do you mean there is no space left inside that 1K for
2.2.5.2 of Marvell PXA27x Processor Family Developers Manual says:
The PXA27x processor cache configuration is identical to that of
the PXA255 processor.
As a result, it is perfectly legitimate to use PXA25X
'lock_cache_for_stack' on PXA27X as well.
Signed-off-by: Sergey Yanovich
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