Re: [U-Boot] [PATCH] dwc: ep0: Allocate and flush dwc->ep0_trb in a cache aligned manner

On Wednesday 11 October 2017 02:28 PM, Kishon Vijay Abraham I wrote: > Hi, > > On Wednesday 11 October 2017 01:53 PM, Faiz Abbas wrote: >> Hi, >> >> On Tuesday 10 October 2017 07:19 PM, Marek Vasut wrote: >>> On 10/10/2017 12:45 PM, Faiz Abbas wrote: Hi Marek, On Tuesday 10

Re: [U-Boot] [PATCH] dwc: ep0: Allocate and flush dwc->ep0_trb in a cache aligned manner

Hi, On Wednesday 11 October 2017 01:53 PM, Faiz Abbas wrote: > Hi, > > On Tuesday 10 October 2017 07:19 PM, Marek Vasut wrote: >> On 10/10/2017 12:45 PM, Faiz Abbas wrote: >>> Hi Marek, >>> >>> On Tuesday 10 October 2017 01:30 PM, Marek Vasut wrote: On 10/10/2017 07:48 AM, Kishon Vijay

Re: [U-Boot] [PATCH] dwc: ep0: Allocate and flush dwc->ep0_trb in a cache aligned manner

Hi, On Tuesday 10 October 2017 07:19 PM, Marek Vasut wrote: > On 10/10/2017 12:45 PM, Faiz Abbas wrote: >> Hi Marek, >> >> On Tuesday 10 October 2017 01:30 PM, Marek Vasut wrote: >>> On 10/10/2017 07:48 AM, Kishon Vijay Abraham I wrote: Hi, >>> >>> Hi, >>> >>> [...] >>> >> -

Re: [U-Boot] [PATCH] dwc: ep0: Allocate and flush dwc->ep0_trb in a cache aligned manner

On 10/10/2017 12:45 PM, Faiz Abbas wrote: > Hi Marek, > > On Tuesday 10 October 2017 01:30 PM, Marek Vasut wrote: >> On 10/10/2017 07:48 AM, Kishon Vijay Abraham I wrote: >>> Hi, >> >> Hi, >> >> [...] >> > - dwc3_flush_cache((uintptr_t)trb, sizeof(*trb)); > +

Re: [U-Boot] [PATCH] dwc: ep0: Allocate and flush dwc->ep0_trb in a cache aligned manner

Hi, On Tuesday 10 October 2017 11:07 AM, Faiz Abbas wrote: > +Kishon > > On Friday 06 October 2017 05:03 PM, Faiz Abbas wrote: >> Hi, >> >> On Thursday 05 October 2017 04:57 PM, Marek Vasut wrote: >>> On 10/04/2017 03:11 PM, Faiz Abbas wrote: Hi, On Wednesday 04 October 2017 06:01

Re: [U-Boot] [PATCH] dwc: ep0: Allocate and flush dwc->ep0_trb in a cache aligned manner

Hi Marek, On Tuesday 10 October 2017 01:30 PM, Marek Vasut wrote: > On 10/10/2017 07:48 AM, Kishon Vijay Abraham I wrote: >> Hi, > > Hi, > > [...] > - dwc3_flush_cache((uintptr_t)trb, sizeof(*trb)); + dwc3_flush_cache((uintptr_t)dwc->ep0_trb_addr, sizeof(*trb) *

Re: [U-Boot] [PATCH] dwc: ep0: Allocate and flush dwc->ep0_trb in a cache aligned manner

On 10/10/2017 07:48 AM, Kishon Vijay Abraham I wrote: > Hi, Hi, [...] >>> - dwc3_flush_cache((uintptr_t)trb, sizeof(*trb)); >>> + dwc3_flush_cache((uintptr_t)dwc->ep0_trb_addr, sizeof(*trb) * >>> 2); >> >> Why *2 ? > > Because its

Re: [U-Boot] [PATCH] dwc: ep0: Allocate and flush dwc->ep0_trb in a cache aligned manner

+Kishon On Friday 06 October 2017 05:03 PM, Faiz Abbas wrote: > Hi, > > On Thursday 05 October 2017 04:57 PM, Marek Vasut wrote: >> On 10/04/2017 03:11 PM, Faiz Abbas wrote: >>> Hi, >>> >>> On Wednesday 04 October 2017 06:01 PM, Marek Vasut wrote: On 10/04/2017 12:51 PM, Faiz Abbas wrote:

Re: [U-Boot] [PATCH] dwc: ep0: Allocate and flush dwc->ep0_trb in a cache aligned manner

Hi, On Thursday 05 October 2017 04:57 PM, Marek Vasut wrote: > On 10/04/2017 03:11 PM, Faiz Abbas wrote: >> Hi, >> >> On Wednesday 04 October 2017 06:01 PM, Marek Vasut wrote: >>> On 10/04/2017 12:51 PM, Faiz Abbas wrote: Hi, On Tuesday 03 October 2017 06:48 PM, Marek Vasut wrote: >

Re: [U-Boot] [PATCH] dwc: ep0: Allocate and flush dwc->ep0_trb in a cache aligned manner

On 10/04/2017 03:11 PM, Faiz Abbas wrote: > Hi, > > On Wednesday 04 October 2017 06:01 PM, Marek Vasut wrote: >> On 10/04/2017 12:51 PM, Faiz Abbas wrote: >>> Hi, >>> On Tuesday 03 October 2017 06:48 PM, Marek Vasut wrote: On 10/03/2017 03:17 PM, Faiz Abbas wrote: > Hi, > On Tuesday

Re: [U-Boot] [PATCH] dwc: ep0: Allocate and flush dwc->ep0_trb in a cache aligned manner

Hi, On Wednesday 04 October 2017 06:01 PM, Marek Vasut wrote: > On 10/04/2017 12:51 PM, Faiz Abbas wrote: >> Hi, >> On Tuesday 03 October 2017 06:48 PM, Marek Vasut wrote: >>> On 10/03/2017 03:17 PM, Faiz Abbas wrote: Hi, On Tuesday 03 October 2017 05:34 PM, Marek Vasut wrote: > On

Re: [U-Boot] [PATCH] dwc: ep0: Allocate and flush dwc->ep0_trb in a cache aligned manner

On 10/04/2017 12:51 PM, Faiz Abbas wrote: > Hi, > > On Tuesday 03 October 2017 06:48 PM, Marek Vasut wrote: >> On 10/03/2017 03:17 PM, Faiz Abbas wrote: >>> Hi, >>> >>> On Tuesday 03 October 2017 05:34 PM, Marek Vasut wrote: On 09/19/2017 01:15 PM, Faiz Abbas wrote: > A flush of the

Re: [U-Boot] [PATCH] dwc: ep0: Allocate and flush dwc->ep0_trb in a cache aligned manner

Hi, On Tuesday 03 October 2017 06:48 PM, Marek Vasut wrote: > On 10/03/2017 03:17 PM, Faiz Abbas wrote: >> Hi, >> >> On Tuesday 03 October 2017 05:34 PM, Marek Vasut wrote: >>> On 09/19/2017 01:15 PM, Faiz Abbas wrote: A flush of the cache is required before any DMA access can take place.

Re: [U-Boot] [PATCH] dwc: ep0: Allocate and flush dwc->ep0_trb in a cache aligned manner

On 10/03/2017 03:17 PM, Faiz Abbas wrote: > Hi, > > On Tuesday 03 October 2017 05:34 PM, Marek Vasut wrote: >> On 09/19/2017 01:15 PM, Faiz Abbas wrote: >>> A flush of the cache is required before any DMA access can take place. >> >> You mean invalidation for inbound DMA, flush for outbound DMA,

Re: [U-Boot] [PATCH] dwc: ep0: Allocate and flush dwc->ep0_trb in a cache aligned manner

Hi, On Tuesday 03 October 2017 05:34 PM, Marek Vasut wrote: > On 09/19/2017 01:15 PM, Faiz Abbas wrote: >> A flush of the cache is required before any DMA access can take place. > > You mean invalidation for inbound DMA, flush for outbound DMA, right ? yes thats what i meant. >> >> -

Re: [U-Boot] [PATCH] dwc: ep0: Allocate and flush dwc->ep0_trb in a cache aligned manner

On 09/19/2017 01:15 PM, Faiz Abbas wrote: > A flush of the cache is required before any DMA access can take place. > The minimum size that can be flushed from the cache is one cache line > size. Therefore, any buffer allocated for DMA should be in multiples > of cache line size. > > Thus,

Re: [U-Boot] [PATCH] dwc: ep0: Allocate and flush dwc->ep0_trb in a cache aligned manner

On 10/03/2017 02:18 PM, Dr. Philipp Tomsich wrote: > Marek, > >> On 3 Oct 2017, at 14:04, Marek Vasut wrote: >> >> On 09/19/2017 01:15 PM, Faiz Abbas wrote: >>> A flush of the cache is required before any DMA access can take place. >> >> You mean invalidation for inbound DMA,

Re: [U-Boot] [PATCH] dwc: ep0: Allocate and flush dwc->ep0_trb in a cache aligned manner

Marek, > On 3 Oct 2017, at 14:04, Marek Vasut wrote: > > On 09/19/2017 01:15 PM, Faiz Abbas wrote: >> A flush of the cache is required before any DMA access can take place. > > You mean invalidation for inbound DMA, flush for outbound DMA, right ? > >> The minimum size that can

Re: [U-Boot] [PATCH] dwc: ep0: Allocate and flush dwc->ep0_trb in a cache aligned manner

On 09/19/2017 01:15 PM, Faiz Abbas wrote: > A flush of the cache is required before any DMA access can take place. You mean invalidation for inbound DMA, flush for outbound DMA, right ? > The minimum size that can be flushed from the cache is one cache line > size. Therefore, any buffer

Re: [U-Boot] [PATCH] dwc: ep0: Allocate and flush dwc->ep0_trb in a cache aligned manner

On 10/03/2017 11:08 AM, Andy Shevchenko wrote: > On Tue, 2017-10-03 at 13:05 +0530, Faiz Abbas wrote: >> Hi, >> >> On Tuesday 19 September 2017 04:45 PM, Faiz Abbas wrote: >>> A flush of the cache is required before any DMA access can take >>> place. >>> The minimum size that can be flushed from

Re: [U-Boot] [PATCH] dwc: ep0: Allocate and flush dwc->ep0_trb in a cache aligned manner

On Tue, 2017-10-03 at 13:05 +0530, Faiz Abbas wrote: > Hi, > > On Tuesday 19 September 2017 04:45 PM, Faiz Abbas wrote: > > A flush of the cache is required before any DMA access can take > > place. > > The minimum size that can be flushed from the cache is one cache > > line > > size. Therefore,

Re: [U-Boot] [PATCH] dwc: ep0: Allocate and flush dwc->ep0_trb in a cache aligned manner

Hi, On Tuesday 19 September 2017 04:45 PM, Faiz Abbas wrote: > A flush of the cache is required before any DMA access can take place. > The minimum size that can be flushed from the cache is one cache line > size. Therefore, any buffer allocated for DMA should be in multiples > of cache line

[U-Boot] [PATCH] dwc: ep0: Allocate and flush dwc->ep0_trb in a cache aligned manner

A flush of the cache is required before any DMA access can take place. The minimum size that can be flushed from the cache is one cache line size. Therefore, any buffer allocated for DMA should be in multiples of cache line size. Thus, allocate memory for ep0_trb in multiples of cache line size.