On 21 October 2015 at 14:42, Simon Glass wrote:
>
> Hi Stephen,
>
> On 21 October 2015 at 10:31, Stephen Warren wrote:
> >
> > On 10/03/2015 08:30 AM, Simon Glass wrote:
> >>
> >> On 3 October 2015 at 00:44, Stephen Warren wrote:
On 10/03/2015 08:30 AM, Simon Glass wrote:
On 3 October 2015 at 00:44, Stephen Warren wrote:
From: Stephen Warren
PCI addresses are always represented as 3 cells in DT. (one cell for bus
and device, and two cells for a 64-bit addres). This does not
Hi Stephen,
On 21 October 2015 at 10:31, Stephen Warren wrote:
>
> On 10/03/2015 08:30 AM, Simon Glass wrote:
>>
>> On 3 October 2015 at 00:44, Stephen Warren wrote:
>>>
>>> From: Stephen Warren
>>>
>>> PCI addresses are always
On Fri, Oct 02, 2015 at 05:44:06PM -0600, Stephen Warren wrote:
> From: Stephen Warren
>
> PCI addresses are always represented as 3 cells in DT. (one cell for bus
> and device, and two cells for a 64-bit addres). This does not vary based
> on either the physical address size
On 3 October 2015 at 00:44, Stephen Warren wrote:
> From: Stephen Warren
>
> PCI addresses are always represented as 3 cells in DT. (one cell for bus
> and device, and two cells for a 64-bit addres). This does not vary based
> on either the physical
From: Stephen Warren
PCI addresses are always represented as 3 cells in DT. (one cell for bus
and device, and two cells for a 64-bit addres). This does not vary based
on either the physical address size of the CPU, nor any #address-cells
property in DT (or more precisely,
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