Hi,
On 08/04/19 10:32 PM, Vignesh Raghavendra wrote:
> This series adds a Kconfig to disable cache maintenance operations on
> a coherent architectures. And disable cache flush/invalidate ops for
> SPL/U-Boot code running on A53 core of AM654 SoC(which is IO coherent)
>
> Vignesh Raghavendra (2):
This series adds a Kconfig to disable cache maintenance operations on
a coherent architectures. And disable cache flush/invalidate ops for
SPL/U-Boot code running on A53 core of AM654 SoC(which is IO coherent)
Vignesh Raghavendra (2):
arch: armv8: Provide a way to disable cache maintenance ops
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