Re: [U-Boot] [PATCH 1/1] ddr cfg: DRAM_RESET needs 0x00020030

2013-07-23 Thread Stefano Babic
Hi Tom, Am 19/07/2013 23:50, schrieb Tom Rini: On Fri, Jul 19, 2013 at 02:34:55PM -0700, Troy Kisky wrote: On 7/19/2013 2:00 PM, Fabio Estevam wrote: Hi Troy, On Wed, Jul 17, 2013 at 4:46 PM, Troy Kisky troy.ki...@boundarydevices.com wrote: The old value of 0x000e0030 will cause ethernet

Re: [U-Boot] [PATCH 1/1] ddr cfg: DRAM_RESET needs 0x00020030

2013-07-23 Thread Tom Rini
On Sat, Jul 20, 2013 at 06:01:56PM +0200, Stefano Babic wrote: Hi Tom, Am 19/07/2013 23:50, schrieb Tom Rini: On Fri, Jul 19, 2013 at 02:34:55PM -0700, Troy Kisky wrote: On 7/19/2013 2:00 PM, Fabio Estevam wrote: Hi Troy, On Wed, Jul 17, 2013 at 4:46 PM, Troy Kisky

Re: [U-Boot] [PATCH 1/1] ddr cfg: DRAM_RESET needs 0x00020030

2013-07-23 Thread Dirk Behme
On 17.07.2013 21:46, Troy Kisky wrote: The old value of 0x000e0030 will cause ethernet timeout issues on the sabrelite and possibly other boards using the KSZ9021. I have no explanation as to why. But this is a correct change, the TRM will be updated to show that 00b is the only valid setting

Re: [U-Boot] [PATCH 1/1] ddr cfg: DRAM_RESET needs 0x00020030

2013-07-19 Thread Fabio Estevam
Hi Troy, On Wed, Jul 17, 2013 at 4:46 PM, Troy Kisky troy.ki...@boundarydevices.com wrote: The old value of 0x000e0030 will cause ethernet timeout issues on the sabrelite and possibly other boards using the KSZ9021. I have no explanation as to why. But this is a correct change, the TRM will

Re: [U-Boot] [PATCH 1/1] ddr cfg: DRAM_RESET needs 0x00020030

2013-07-19 Thread Troy Kisky
On 7/19/2013 2:00 PM, Fabio Estevam wrote: Hi Troy, On Wed, Jul 17, 2013 at 4:46 PM, Troy Kisky troy.ki...@boundarydevices.com wrote: The old value of 0x000e0030 will cause ethernet timeout issues on the sabrelite and possibly other boards using the KSZ9021. I have no explanation as to why.

Re: [U-Boot] [PATCH 1/1] ddr cfg: DRAM_RESET needs 0x00020030

2013-07-19 Thread Fabio Estevam
On Wed, Jul 17, 2013 at 4:46 PM, Troy Kisky troy.ki...@boundarydevices.com wrote: The old value of 0x000e0030 will cause ethernet timeout issues on the sabrelite and possibly other boards using the KSZ9021. I have no explanation as to why. But this is a correct change, the TRM will be

Re: [U-Boot] [PATCH 1/1] ddr cfg: DRAM_RESET needs 0x00020030

2013-07-19 Thread Tom Rini
On Fri, Jul 19, 2013 at 02:34:55PM -0700, Troy Kisky wrote: On 7/19/2013 2:00 PM, Fabio Estevam wrote: Hi Troy, On Wed, Jul 17, 2013 at 4:46 PM, Troy Kisky troy.ki...@boundarydevices.com wrote: The old value of 0x000e0030 will cause ethernet timeout issues on the sabrelite and possibly

Re: [U-Boot] [PATCH 1/1] ddr cfg: DRAM_RESET needs 0x00020030

2013-07-19 Thread Fabio Estevam
Hi Tom, On Fri, Jul 19, 2013 at 6:50 PM, Tom Rini tr...@ti.com wrote: On Fri, Jul 19, 2013 at 02:34:55PM -0700, Troy Kisky wrote: On 7/19/2013 2:00 PM, Fabio Estevam wrote: Hi Troy, On Wed, Jul 17, 2013 at 4:46 PM, Troy Kisky troy.ki...@boundarydevices.com wrote: The old value of

[U-Boot] [PATCH 1/1] ddr cfg: DRAM_RESET needs 0x00020030

2013-07-17 Thread Troy Kisky
The old value of 0x000e0030 will cause ethernet timeout issues on the sabrelite and possibly other boards using the KSZ9021. I have no explanation as to why. But this is a correct change, the TRM will be updated to show that 00b is the only valid setting for bits 19-18 of DRAM_RESET. My thanks