On Wed, Jun 27, 2018 at 2:25 AM Joe Hershberger wrote:
>
> On Tue, Jun 26, 2018 at 5:34 AM, Chris Packham
> wrote:
> > On Tue, Jun 26, 2018 at 6:10 AM Joe Hershberger
> > wrote:
> >>
> >> On Mon, Jun 25, 2018 at 5:34 AM, Chris Packham
> >> wrote:
> >> > Some hardware designs connect a CPU
On Tue, Jun 26, 2018 at 5:34 AM, Chris Packham wrote:
> On Tue, Jun 26, 2018 at 6:10 AM Joe Hershberger
> wrote:
>>
>> On Mon, Jun 25, 2018 at 5:34 AM, Chris Packham
>> wrote:
>> > Some hardware designs connect a CPU MAC directly to the RGMII interface
>> > of a mv88e61xx device. On such
On Tue, Jun 26, 2018 at 6:10 AM Joe Hershberger wrote:
>
> On Mon, Jun 25, 2018 at 5:34 AM, Chris Packham
> wrote:
> > Some hardware designs connect a CPU MAC directly to the RGMII interface
> > of a mv88e61xx device. On such devices a delay on the RX/TX lines is
> > required, this can either
On Mon, Jun 25, 2018 at 5:34 AM, Chris Packham wrote:
> Some hardware designs connect a CPU MAC directly to the RGMII interface
> of a mv88e61xx device. On such devices a delay on the RX/TX lines is
> required, this can either be achieved by adding extra length to the
> traces on the PCB or by
Some hardware designs connect a CPU MAC directly to the RGMII interface
of a mv88e61xx device. On such devices a delay on the RX/TX lines is
required, this can either be achieved by adding extra length to the
traces on the PCB or by implementing the delay in silicon. This is
an implementation of
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