Re: [U-Boot] [PATCH 1/2] pinctrl: a3700: Fix uart2 group selection register mask

2017-06-23 Thread Stefan Roese
On 22.06.2017 11:13, m...@marvell.com wrote: From: Ken Ma If north bridge selection register bit1 is clear, pins [10:8] are for SDIO0 Resetn, Wakeup, and PDN while if bit1 is set, pins [10:8]are for GPIO; when bit1 is clear, pin 9 and pin 10 can be used for uart2 RTSn and CTSn, so bit1 should b

Re: [U-Boot] [PATCH 1/2] pinctrl: a3700: Fix uart2 group selection register mask

2017-06-22 Thread Stefan Roese
Hi Ken, On 22.06.2017 11:13, m...@marvell.com wrote: > From: Ken Ma > > If north bridge selection register bit1 is clear, pins [10:8] are for > SDIO0 Resetn, Wakeup, and PDN while if bit1 is set, pins [10:8]are for > GPIO; when bit1 is clear, pin 9 and pin 10 can be used for uart2 RTSn > and CTS

[U-Boot] [PATCH 1/2] pinctrl: a3700: Fix uart2 group selection register mask

2017-06-22 Thread make
From: Ken Ma If north bridge selection register bit1 is clear, pins [10:8] are for SDIO0 Resetn, Wakeup, and PDN while if bit1 is set, pins [10:8]are for GPIO; when bit1 is clear, pin 9 and pin 10 can be used for uart2 RTSn and CTSn, so bit1 should be added to uart2 group and it must be set for b

[U-Boot] [PATCH 1/2] pinctrl: a3700: Fix uart2 group selection register mask

2017-06-21 Thread make
From: Ken Ma If north bridge selection register bit1 is clear, pins [10:8] are for SDIO0 Resetn, Wakeup, and PDN while if bit1 is set, pins [10:8]are for GPIO; when bit1 is clear, pin 9 and pin 10 can be used for uart2 RTSn and CTSn, so bit1 should be added to uart2 group and it must be set for b