> Ok. I'd prefer we just expand the field to 0x3ff to match the EREF
> spec since the upper bits are reserved we'll always read them
> as 0 so no harm. And we dont have to change the code again in
> the future if we expand into those upper bits.
If match the EREF, it should be 0x7ff.
and it al
On Dec 16, 2008, at 5:47 PM, Liu Dave wrote:
>> was code breaking or just fixing it up to match the docs?
>
> not break the system, because the bit[55] is reserved zero for
> e500/e500mc.
> so just fixied it to match the e500/e500mc docs.
Ok. I'd prefer we just expand the field to 0x3ff to match
> was code breaking or just fixing it up to match the docs?
not break the system, because the bit[55] is reserved zero for
e500/e500mc.
so just fixied it to match the e500/e500mc docs.
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On Dec 15, 2008, at 10:09 PM, Dave Liu wrote:
> The CSIZE is L1CFG0[56-63] in the e500 and e500mc core,
> so we should mask 0xff, not 0x1ff.
>
> Signed-off-by: Dave Liu
> ---
> cpu/mpc85xx/start.S |4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)
was code breaking or just fixing it
The CSIZE is L1CFG0[56-63] in the e500 and e500mc core,
so we should mask 0xff, not 0x1ff.
Signed-off-by: Dave Liu
---
cpu/mpc85xx/start.S |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index 80f9677..cfa53c0 100644
--- a/cpu
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