Re: [U-Boot] [PATCH 2/3] mx6: ddr: pass mx6_ddr_sysinfo to calibration routines

2016-10-30 Thread Marek Vasut
On 10/30/2016 06:19 PM, Eric Nelson wrote: > The DDR calibration routines have scattered support for bus > widths other than 64-bits: > > -- The mmdc_do_write_level_calibration() routine assumes the > presence of PHY1, and > -- The mmdc_do_dqs_calibration() routine tries to determine > whether

[U-Boot] [PATCH 2/3] mx6: ddr: pass mx6_ddr_sysinfo to calibration routines

2016-10-30 Thread Eric Nelson
The DDR calibration routines have scattered support for bus widths other than 64-bits: -- The mmdc_do_write_level_calibration() routine assumes the presence of PHY1, and -- The mmdc_do_dqs_calibration() routine tries to determine whether one or two DDR PHYs are active by reading MDCTL. Since a