On Tue, 2019-01-01 at 21:31 +0100, Marek Vasut wrote:
> On 1/1/19 4:39 AM, Chee, Tien Fong wrote:
> >
> > On Sun, 2018-12-30 at 16:51 +0100, Marek Vasut wrote:
> > >
> > > On 12/30/18 9:13 AM, tien.fong.c...@intel.com wrote:
> > > >
> > > >
> > > > From: Tien Fong Chee
> > > >
> > > > Add sup
On 1/1/19 4:39 AM, Chee, Tien Fong wrote:
> On Sun, 2018-12-30 at 16:51 +0100, Marek Vasut wrote:
>> On 12/30/18 9:13 AM, tien.fong.c...@intel.com wrote:
>>>
>>> From: Tien Fong Chee
>>>
>>> Add support for loading FPGA bitstream to get DDR up running before
>>> U-Boot is loaded into DDR. Boot dev
On Sun, 2018-12-30 at 16:51 +0100, Marek Vasut wrote:
> On 12/30/18 9:13 AM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Add support for loading FPGA bitstream to get DDR up running before
> > U-Boot is loaded into DDR. Boot device initialization, generic
> > firmware
>
On 12/30/18 9:13 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Add support for loading FPGA bitstream to get DDR up running before
> U-Boot is loaded into DDR. Boot device initialization, generic firmware
> loader and SPL FAT support are required for this whole mechanism to work.
From: Tien Fong Chee
Add support for loading FPGA bitstream to get DDR up running before
U-Boot is loaded into DDR. Boot device initialization, generic firmware
loader and SPL FAT support are required for this whole mechanism to work.
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/spl
5 matches
Mail list logo