+while (num_err--) {
+change_bit(0,err_idx[i]);
+change_bit(1,err_idx[i]);
+
+if (err_idx[i] 512 * 8) {
+change_bit(err_idx[i], dat);
+i++;
+}
+}
Is it normal to not count bit flips in the ECC itself?
Correcting bit flip in
Hi Scott,
On 5/16/2012 2:44 AM, Scott Wood wrote:
On 05/07/2012 02:26 AM, Amit Virdi wrote:
+ while (num_err--) {
+ change_bit(0,err_idx[i]);
+ change_bit(1,err_idx[i]);
+
+ if (err_idx[i] 512 * 8) {
+
On 5/16/2012 2:44 AM, Scott Wood wrote:
+case FSMC_VER8:
+/* Busy waiting for ecc computation to finish for 512 bytes */
+while (!(readl(fsmc_regs_p-sts) FSMC_CODE_RDY))
+;
Timeout?
+uint16_t ecc_oob[7];
+uint8_t *oob = (uint8_t *)ecc_oob[0];
Three fixups.
Signed-off-by: Amit Virdiamit.vi...@st.com
Please discard this. I'll send changes in the V3 patchset.
Thanks
Amit Virdi
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On 05/16/2012 05:41 AM, Amit Virdi wrote:
Hi Scott,
On 5/16/2012 2:44 AM, Scott Wood wrote:
On 05/07/2012 02:26 AM, Amit Virdi wrote:
+while (num_err--) {
+change_bit(0,err_idx[i]);
+change_bit(1,err_idx[i]);
+
+if (err_idx[i] 512 * 8) {
+
On 05/07/2012 02:26 AM, Amit Virdi wrote:
+ while (num_err--) {
+ change_bit(0, err_idx[i]);
+ change_bit(1, err_idx[i]);
+
+ if (err_idx[i] 512 * 8) {
+ change_bit(err_idx[i], dat);
+ i++;
+ }
+
From: Vipin KUMAR vipin.ku...@st.com
Flexible static memory controller is a peripheral provided by ST,
which controls the access to NAND chips along with many other
memory device chips eg NOR, SRAM.
This patch adds the driver support for FSMC controller interfacing
with NAND memory.
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